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1 | /*************************************************************************\r |
2 | * *\r | |
3 | * $Id: s100_ss1.c 1773 2008-01-11 05:46:19Z hharte $ *\r | |
4 | * *\r | |
5 | * Copyright (c) 2007-2008 Howard M. Harte. *\r | |
6 | * http://www.hartetec.com *\r | |
7 | * *\r | |
8 | * Permission is hereby granted, free of charge, to any person obtaining *\r | |
9 | * a copy of this software and associated documentation files (the *\r | |
10 | * "Software"), to deal in the Software without restriction, including *\r | |
11 | * without limitation the rights to use, copy, modify, merge, publish, *\r | |
12 | * distribute, sublicense, and/or sell copies of the Software, and to *\r | |
13 | * permit persons to whom the Software is furnished to do so, subject to *\r | |
14 | * the following conditions: *\r | |
15 | * *\r | |
16 | * The above copyright notice and this permission notice shall be *\r | |
17 | * included in all copies or substantial portions of the Software. *\r | |
18 | * *\r | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *\r | |
20 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *\r | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND *\r | |
22 | * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY *\r | |
23 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, *\r | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE *\r | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *\r | |
26 | * *\r | |
27 | * Except as contained in this notice, the name of Howard M. Harte shall *\r | |
28 | * not be used in advertising or otherwise to promote the sale, use or *\r | |
29 | * other dealings in this Software without prior written authorization *\r | |
30 | * Howard M. Harte. *\r | |
31 | * *\r | |
32 | * SIMH Interface based on altairz80_hdsk.c, by Peter Schorn. *\r | |
33 | * *\r | |
34 | * Module Description: *\r | |
35 | * CompuPro System Support 1 module for SIMH. *\r | |
36 | * Note this does not include the Boot ROM on the System Support 1 Card *\r | |
37 | * *\r | |
38 | * Environment: *\r | |
39 | * User mode only *\r | |
40 | * *\r | |
41 | *************************************************************************/\r | |
42 | \r | |
43 | /*#define DBG_MSG */\r | |
44 | \r | |
45 | #include "altairz80_defs.h"\r | |
46 | \r | |
47 | #if defined (_WIN32)\r | |
48 | #include <windows.h>\r | |
49 | #endif\r | |
50 | \r | |
51 | #ifdef DBG_MSG\r | |
52 | #define DBG_PRINT(args) printf args\r | |
53 | #else\r | |
54 | #define DBG_PRINT(args)\r | |
55 | #endif\r | |
56 | \r | |
57 | #define TRACE_MSG 0x01\r | |
58 | #define DMA_MSG 0x02\r | |
59 | \r | |
60 | #define SS1_MAX_DRIVES 1\r | |
61 | \r | |
62 | #define UNIT_V_SS1_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */\r | |
63 | #define UNIT_SS1_VERBOSE (1 << UNIT_V_SS1_VERBOSE)\r | |
64 | \r | |
65 | typedef struct {\r | |
66 | PNP_INFO pnp; /* Plug and Play */\r | |
67 | } SS1_INFO;\r | |
68 | \r | |
69 | static SS1_INFO ss1_info_data = { { 0x0, 0, 0x50, 12 } };\r | |
70 | /* static SS1_INFO *ss1_info = &ss1_info_data;*/\r | |
71 | \r | |
72 | extern t_stat set_iobase(UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
73 | extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
74 | extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,\r | |
75 | int32 (*routine)(const int32, const int32, const int32), uint8 unmap);\r | |
76 | extern uint32 PCX;\r | |
77 | extern REG *sim_PC;\r | |
78 | \r | |
79 | /* These are needed for DMA. PIO Mode has not been implemented yet. */\r | |
80 | extern void PutBYTEWrapper(const uint32 Addr, const uint32 Value);\r | |
81 | extern uint8 GetBYTEWrapper(const uint32 Addr);\r | |
82 | \r | |
83 | static t_stat ss1_reset(DEVICE *ss1_dev);\r | |
84 | static uint8 SS1_Read(const uint32 Addr);\r | |
85 | static uint8 SS1_Write(const uint32 Addr, uint8 cData);\r | |
86 | \r | |
87 | \r | |
88 | static int32 ss1dev(const int32 port, const int32 io, const int32 data);\r | |
89 | \r | |
90 | static int32 trace_level = 0x00; /* Disable all tracing by default */\r | |
91 | \r | |
92 | static UNIT ss1_unit[] = {\r | |
93 | { UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ROABLE, 0) }\r | |
94 | };\r | |
95 | \r | |
96 | static REG ss1_reg[] = {\r | |
97 | { HRDATA (TRACELEVEL, trace_level, 16), },\r | |
98 | { NULL }\r | |
99 | };\r | |
100 | \r | |
101 | static MTAB ss1_mod[] = {\r | |
102 | { MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", &set_iobase, &show_iobase, NULL },\r | |
103 | /* quiet, no warning messages */\r | |
104 | { UNIT_SS1_VERBOSE, 0, "QUIET", "QUIET", NULL },\r | |
105 | /* verbose, show warning messages */\r | |
106 | { UNIT_SS1_VERBOSE, UNIT_SS1_VERBOSE, "VERBOSE", "VERBOSE", NULL },\r | |
107 | { 0 }\r | |
108 | };\r | |
109 | \r | |
110 | DEVICE ss1_dev = {\r | |
111 | "SS1", ss1_unit, ss1_reg, ss1_mod,\r | |
112 | SS1_MAX_DRIVES, 10, 31, 1, SS1_MAX_DRIVES, SS1_MAX_DRIVES,\r | |
113 | NULL, NULL, &ss1_reset,\r | |
114 | NULL, NULL, NULL,\r | |
115 | &ss1_info_data, (DEV_DISABLE | DEV_DIS), 0,\r | |
116 | NULL, NULL, NULL\r | |
117 | };\r | |
118 | \r | |
119 | /* Reset routine */\r | |
120 | static t_stat ss1_reset(DEVICE *dptr)\r | |
121 | {\r | |
122 | PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;\r | |
123 | \r | |
124 | if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */\r | |
125 | sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, TRUE);\r | |
126 | } else {\r | |
127 | /* Connect SS1 at base address */\r | |
128 | if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &ss1dev, FALSE) != 0) {\r | |
129 | printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);\r | |
130 | return SCPE_ARG;\r | |
131 | }\r | |
132 | }\r | |
133 | return SCPE_OK;\r | |
134 | }\r | |
135 | \r | |
136 | static int32 ss1dev(const int32 port, const int32 io, const int32 data)\r | |
137 | {\r | |
138 | DBG_PRINT(("SS1: IO %s, Port %02x\n", io ? "WR" : "RD", port));\r | |
139 | if(io) {\r | |
140 | SS1_Write(port, data);\r | |
141 | return 0;\r | |
142 | } else {\r | |
143 | return(SS1_Read(port));\r | |
144 | }\r | |
145 | }\r | |
146 | \r | |
147 | #define SS1_M8259_L 0x00\r | |
148 | #define SS1_M8259_H 0x01\r | |
149 | #define SS1_S8259_L 0x02\r | |
150 | #define SS1_S8259_H 0x03\r | |
151 | #define SS1_8253_TC0 0x04\r | |
152 | #define SS1_8253_TC1 0x05\r | |
153 | #define SS1_8253_TC2 0x06\r | |
154 | #define SS1_8253_CTL 0x07\r | |
155 | #define SS1_9511A_DATA 0x08\r | |
156 | #define SS1_9511A_CMD 0x09\r | |
157 | #define SS1_RTC_CMD 0x0A\r | |
158 | #define SS1_RTC_DATA 0x0B\r | |
159 | #define SS1_UART_DATA 0x0C\r | |
160 | #define SS1_UART_STAT 0x0D\r | |
161 | #define SS1_UART_MODE 0x0E\r | |
162 | #define SS1_UART_CMD 0x0F\r | |
163 | \r | |
164 | extern int32 sio0d(const int32 port, const int32 io, const int32 data);\r | |
165 | extern int32 sio0s(const int32 port, const int32 io, const int32 data);\r | |
166 | \r | |
167 | static uint8 SS1_Read(const uint32 Addr)\r | |
168 | {\r | |
169 | uint8 cData = 0x00;\r | |
170 | \r | |
171 | switch(Addr & 0x0F) {\r | |
172 | case SS1_M8259_L:\r | |
173 | case SS1_M8259_H:\r | |
174 | case SS1_S8259_L:\r | |
175 | case SS1_S8259_H:\r | |
176 | TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Interrupt Controller not Implemented." NLP, PCX));\r | |
177 | break;\r | |
178 | case SS1_8253_TC0:\r | |
179 | case SS1_8253_TC1:\r | |
180 | case SS1_8253_TC2:\r | |
181 | case SS1_8253_CTL:\r | |
182 | TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Timer not Implemented." NLP, PCX));\r | |
183 | break;\r | |
184 | case SS1_9511A_DATA:\r | |
185 | case SS1_9511A_CMD:\r | |
186 | TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: Math Coprocessor not Implemented." NLP, PCX));\r | |
187 | break;\r | |
188 | case SS1_RTC_CMD:\r | |
189 | case SS1_RTC_DATA:\r | |
190 | TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: RTC not Implemented." NLP, PCX));\r | |
191 | break;\r | |
192 | case SS1_UART_DATA:\r | |
193 | cData = sio0d(Addr, 0, 0);\r | |
194 | break;\r | |
195 | case SS1_UART_STAT:\r | |
196 | cData = sio0s(Addr, 0, 0);\r | |
197 | break;\r | |
198 | case SS1_UART_MODE:\r | |
199 | case SS1_UART_CMD:\r | |
200 | TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " RD: UART not Implemented." NLP, PCX));\r | |
201 | break;\r | |
202 | }\r | |
203 | \r | |
204 | return (cData);\r | |
205 | \r | |
206 | }\r | |
207 | \r | |
208 | static uint8 SS1_Write(const uint32 Addr, uint8 cData)\r | |
209 | {\r | |
210 | \r | |
211 | switch(Addr & 0x0F) {\r | |
212 | case SS1_M8259_L:\r | |
213 | case SS1_M8259_H:\r | |
214 | case SS1_S8259_L:\r | |
215 | case SS1_S8259_H:\r | |
216 | TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Interrupt Controller not Implemented." NLP, PCX));\r | |
217 | break;\r | |
218 | case SS1_8253_TC0:\r | |
219 | case SS1_8253_TC1:\r | |
220 | case SS1_8253_TC2:\r | |
221 | case SS1_8253_CTL:\r | |
222 | TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Timer not Implemented." NLP, PCX));\r | |
223 | break;\r | |
224 | case SS1_9511A_DATA:\r | |
225 | case SS1_9511A_CMD:\r | |
226 | TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: Math Coprocessor not Implemented." NLP, PCX));\r | |
227 | break;\r | |
228 | case SS1_RTC_CMD:\r | |
229 | case SS1_RTC_DATA:\r | |
230 | TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: RTC not Implemented." NLP, PCX));\r | |
231 | break;\r | |
232 | case SS1_UART_DATA:\r | |
233 | sio0d(Addr, 1, cData);\r | |
234 | break;\r | |
235 | case SS1_UART_STAT:\r | |
236 | sio0s(Addr, 1, cData);\r | |
237 | break;\r | |
238 | case SS1_UART_MODE:\r | |
239 | case SS1_UART_CMD:\r | |
240 | TRACE_PRINT(TRACE_MSG, ("SS1: " ADDRESS_FORMAT " WR: UART not Implemented." NLP, PCX));\r | |
241 | break;\r | |
242 | }\r | |
243 | \r | |
244 | return(0);\r | |
245 | }\r | |
246 | \r |