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1 | /* h316_defs.h: Honeywell 316/516 simulator definitions\r |
2 | \r | |
3 | Copyright (c) 1999-2005, Robert M. Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | 15-Feb-05 RMS Added start button interrupt\r | |
27 | 01-Dec-04 RMS Added double precision constants\r | |
28 | 24-Oct-03 RMS Added DMA/DMC support\r | |
29 | 25-Apr-03 RMS Revised for extended file support\r | |
30 | */\r | |
31 | \r | |
32 | #ifndef _H316_DEFS_H_\r | |
33 | #define _H316_DEFS_H_ 0\r | |
34 | \r | |
35 | #include "sim_defs.h" /* simulator defns */\r | |
36 | \r | |
37 | /* Simulator stop codes */\r | |
38 | \r | |
39 | #define STOP_RSRV 1 /* must be 1 */\r | |
40 | #define STOP_IODV 2 /* must be 2 */\r | |
41 | #define STOP_HALT 3 /* HALT */\r | |
42 | #define STOP_IBKPT 4 /* breakpoint */\r | |
43 | #define STOP_IND 5 /* indirect loop */\r | |
44 | #define STOP_DMAER 6 /* DMA error */\r | |
45 | #define STOP_MTWRP 7 /* MT write protected */\r | |
46 | #define STOP_DPOVR 8 /* DP write overrun */\r | |
47 | #define STOP_DPFMT 9 /* DP invalid format */\r | |
48 | \r | |
49 | /* Memory */\r | |
50 | \r | |
51 | #define MAXMEMSIZE 32768 /* max memory size */\r | |
52 | #define MEMSIZE (cpu_unit.capac) /* actual memory size */\r | |
53 | #define X_AMASK (MAXMEMSIZE - 1) /* ext address mask */\r | |
54 | #define NX_AMASK ((MAXMEMSIZE / 2) - 1) /* nx address mask */\r | |
55 | #define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)\r | |
56 | \r | |
57 | /* Architectural constants */\r | |
58 | \r | |
59 | #define SIGN 0100000 /* sign */\r | |
60 | #define DP_SIGN 010000000000\r | |
61 | #define DMASK 0177777 /* data mask */\r | |
62 | #define MMASK (DMASK & ~SIGN) /* magnitude mask */\r | |
63 | #define XR M[0]\r | |
64 | #define M_CLK 061 /* clock location */\r | |
65 | #define M_RSTINT 062 /* restrict int */\r | |
66 | #define M_INT 063 /* int location */\r | |
67 | \r | |
68 | /* CPU options */\r | |
69 | \r | |
70 | #define UNIT_V_MSIZE (UNIT_V_UF + 0) /* dummy mask */\r | |
71 | #define UNIT_V_EXT (UNIT_V_UF + 1) /* extended mem */\r | |
72 | #define UNIT_V_HSA (UNIT_V_UF + 2) /* high speed arith */\r | |
73 | #define UNIT_V_DMC (UNIT_V_UF + 3) /* DMC */\r | |
74 | #define UNIT_MSIZE (1u << UNIT_V_MSIZE)\r | |
75 | #define UNIT_EXT (1u << UNIT_V_EXT)\r | |
76 | #define UNIT_HSA (1u << UNIT_V_HSA)\r | |
77 | #define UNIT_DMC (1u << UNIT_V_DMC)\r | |
78 | \r | |
79 | /* Instruction format */\r | |
80 | \r | |
81 | #define I_M_OP 077 /* opcode */\r | |
82 | #define I_V_OP 10\r | |
83 | #define I_GETOP(x) (((x) >> I_V_OP) & I_M_OP)\r | |
84 | #define I_M_FNC 017 /* function */\r | |
85 | #define I_V_FNC 6\r | |
86 | #define I_GETFNC(x) (((x) >> I_V_FNC) & I_M_FNC)\r | |
87 | #define IA 0100000 /* indirect address */\r | |
88 | #define IDX 0040000 /* indexed */\r | |
89 | #define SC 0001000 /* sector */\r | |
90 | #define DISP 0000777 /* page displacement */\r | |
91 | #define PAGENO 0077000 /* page number */\r | |
92 | #define INCLRA (010 << I_V_FNC) /* INA clear A */\r | |
93 | #define DEVMASK 0000077 /* device mask */\r | |
94 | #define SHFMASK 0000077 /* shift mask */\r | |
95 | \r | |
96 | /* I/O opcodes */\r | |
97 | \r | |
98 | #define ioOCP 0 /* output control */\r | |
99 | #define ioSKS 1 /* skip if set */\r | |
100 | #define ioINA 2 /* input to A */\r | |
101 | #define ioOTA 3 /* output from A */\r | |
102 | #define ioEND 4 /* channel end */\r | |
103 | \r | |
104 | /* Device information block */\r | |
105 | \r | |
106 | struct h316_dib {\r | |
107 | uint32 dev; /* device number */\r | |
108 | uint32 chan; /* dma/dmc channel */\r | |
109 | uint32 num; /* number of slots */\r | |
110 | int32 (*io) (int32 inst, int32 fnc, int32 dat, int32 dev); };\r | |
111 | \r | |
112 | typedef struct h316_dib DIB;\r | |
113 | \r | |
114 | /* DMA/DMC channel numbers */\r | |
115 | \r | |
116 | #define IOBUS 0 /* IO bus */\r | |
117 | #define DMA_MIN 1 /* 4 DMA channels */\r | |
118 | #define DMA_MAX 4\r | |
119 | #define DMC_MIN 1 /* 16 DMC channels */\r | |
120 | #define DMC_MAX 16\r | |
121 | \r | |
122 | #define DMA1 (DMA_MIN)\r | |
123 | #define DMC1 (DMA_MAX+DMC_MIN)\r | |
124 | \r | |
125 | /* DMA/DMC bit assignments in channel request word */\r | |
126 | \r | |
127 | #define DMA_V_DMA1 0 /* DMA channels */\r | |
128 | #define DMC_V_DMC1 4 /* DMC channels */\r | |
129 | #define SET_CH_REQ(x) chan_req = chan_req | (1 << (x))\r | |
130 | #define Q_DMA(x) (((x) >= 0) && ((x) < DMC_V_DMC1))\r | |
131 | \r | |
132 | /* DMA/DMC definitions */\r | |
133 | \r | |
134 | #define DMA_IN 0100000 /* input flag */\r | |
135 | #define DMC_BASE 020 /* DMC memory base */\r | |
136 | \r | |
137 | /* I/O device codes */\r | |
138 | \r | |
139 | #define PTR 001 /* paper tape reader */\r | |
140 | #define PTP 002 /* paper tape punch */\r | |
141 | #define LPT 003 /* line printer */\r | |
142 | #define TTY 004 /* console */\r | |
143 | #define CDR 005 /* card reader */\r | |
144 | #define MT 010 /* mag tape data */\r | |
145 | #define CLK_KEYS 020 /* clock/keys (CPU) */\r | |
146 | #define FHD 022 /* fixed head disk */\r | |
147 | #define DMA 024 /* DMA control */\r | |
148 | #define DP 025 /* moving head disk */\r | |
149 | #define DEV_MAX 64\r | |
150 | \r | |
151 | /* Interrupt flags, definitions correspond to SMK bits */\r | |
152 | \r | |
153 | #define INT_V_CLK 0 /* clock */\r | |
154 | #define INT_V_MPE 1 /* parity error */\r | |
155 | #define INT_V_LPT 2 /* line printer */\r | |
156 | #define INT_V_CDR 4 /* card reader */\r | |
157 | #define INT_V_TTY 5 /* teletype */\r | |
158 | #define INT_V_PTP 6 /* paper tape punch */\r | |
159 | #define INT_V_PTR 7 /* paper tape reader */\r | |
160 | #define INT_V_FHD 8 /* fixed head disk */\r | |
161 | #define INT_V_DP 12 /* moving head disk */\r | |
162 | #define INT_V_MT 15 /* mag tape */\r | |
163 | #define INT_V_START 16 /* start button */\r | |
164 | #define INT_V_NODEF 17 /* int not deferred */\r | |
165 | #define INT_V_ON 18 /* int on */\r | |
166 | \r | |
167 | /* I/O macros */\r | |
168 | \r | |
169 | #define IOT_V_REASON 17\r | |
170 | #define IOT_V_SKIP 16\r | |
171 | #define IOT_SKIP (1u << IOT_V_SKIP)\r | |
172 | #define IORETURN(f,v) (((f)? (v): SCPE_OK) << IOT_V_REASON)\r | |
173 | #define IOBADFNC(x) (((stop_inst) << IOT_V_REASON) | (x))\r | |
174 | #define IOSKIP(x) (IOT_SKIP | (x))\r | |
175 | \r | |
176 | #define INT_CLK (1u << INT_V_CLK)\r | |
177 | #define INT_MPE (1u << INT_V_MPE)\r | |
178 | #define INT_LPT (1u << INT_V_LPT)\r | |
179 | #define INT_CDR (1u << INT_V_CDR)\r | |
180 | #define INT_TTY (1u << INT_V_TTY)\r | |
181 | #define INT_PTP (1u << INT_V_PTP)\r | |
182 | #define INT_PTR (1u << INT_V_PTR)\r | |
183 | #define INT_FHD (1u << INT_V_FHD)\r | |
184 | #define INT_DP (1u << INT_V_DP)\r | |
185 | #define INT_MT (1u << INT_V_MT)\r | |
186 | #define INT_START (1u << INT_V_START)\r | |
187 | #define INT_NODEF (1u << INT_V_NODEF)\r | |
188 | #define INT_ON (1u << INT_V_ON)\r | |
189 | #define INT_NMI (INT_START)\r | |
190 | #define INT_PEND (INT_ON | INT_NODEF)\r | |
191 | \r | |
192 | #define SET_INT(x) dev_int = dev_int | (x)\r | |
193 | #define CLR_INT(x) dev_int = dev_int & ~(x)\r | |
194 | #define TST_INT(x) ((dev_int & (x)) != 0)\r | |
195 | #define CLR_ENB(x) dev_enb = dev_enb & ~(x)\r | |
196 | #define TST_INTREQ(x) ((dev_int & dev_enb & (x)) != 0)\r | |
197 | \r | |
198 | /* Prototypes */\r | |
199 | \r | |
200 | t_stat io_set_iobus (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
201 | t_stat io_set_dma (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
202 | t_stat io_set_dmc (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
203 | t_stat io_show_chan (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
204 | \r | |
205 | #endif\r |