Commit | Line | Data |
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196ba1fc PH |
1 | Bugs Found and Fixed During Simulator Debug\r |
2 | \r | |
3 | 1. CPU: MPY tested sign of AC instead of sign of MQ.\r | |
4 | 2. CPU: VLM, VDP, VDH need alternate opcode decode points for large counts.\r | |
5 | 3. CPU: STL not in decode table.\r | |
6 | 4. CPU: Partial stores lacked initial read in decode table.\r | |
7 | 5. CPU: PXD, PCD needed (t_uint64) cast.\r | |
8 | 6. CPU: SXD, SCD needed (t_uint64) cast.\r | |
9 | 7. CPU: SBM at wrong case offset.\r | |
10 | 8. CPU: All transfers used IR<21:35> instead of calculated effective address.\r | |
11 | 9. CPU: HPR, TRA need alternate negative opcodes.\r | |
12 | 10. CPU: STT missing final write to memory.\r | |
13 | 11. IO: Channel output process model incorrect, extensive revision required.\r | |
14 | 12. IO: Channel connect test should not test channel state, only connection.\r | |
15 | 13. IO: Channel opcode with nostore doesn't increment channel address.\r | |
16 | 14. CDR: Card reader missing activate at end of state 2.\r | |
17 | 15. SYS: Zero operand instructions printed with trailing space.\r | |
18 | 16. CPU: Convert class count bit field start definition incorrect.\r | |
19 | 17. CPU: CAQ cut and paste error from CVR.\r | |
20 | 18. CPU: Shift count is 8b wide, not 9b.\r | |
21 | 19. SYS: Mnemonic is LDQ not LMQ.\r | |
22 | 20. SYS: RQL opcode incorrect in symbolic decode table.\r | |
23 | 21. CPU: Multi-tag mode stores OR'd value of tags on any index read except\r | |
24 | normal effective address.\r | |
25 | 22. CPU: Floating point trap does not write location 0 if trap suppressed.\r | |
26 | 23. SYS: TRA instructions should have symbolic class MXN not MXR.\r | |
27 | 24. CPU: Floating add instructions test for zero result only if normalization enabled.\r | |
28 | 25. CPU: Floating add with unlike signs and equal magnitudes, result sign is sign\r | |
29 | of SR rather than sign of AC.\r | |
30 | 26. CPU: Floating multiply does not test spill prior to normalization step.\r | |
31 | 27. CPU: Channel activity proceeds under HALT.\r | |
32 | 28. MT: Any read error should stop the channel and the tape controller.\r | |
33 | 29. MT: EOR write flag cleared before testing.\r | |
34 | 39. IO: EOR write flag set after data sent to device.\r | |
35 | 40. IO: EOR write flag incorrect set on IOCP, IOCT, IOSP, IOST.\r | |
36 | 41. MT: End of file errors not masked on backspace operations.\r | |
37 | 42. CPU: LCHx, RCHx miscoded in decode table.\r | |
38 | 43. IO: Only 7607 error completions (IOxT without new command) set trap.\r | |
39 | 44. CPU: 7067 channel trap flags misdefined with extraneous decrement shift.\r | |
40 | 45. CPU: pcq array misdeclared as uint32 instead of uint16.\r | |
41 | 46. IO: SDC and SCD tested chan_flags instead of chan_dev.flags.\r | |
42 | 47. SYS: 7907 opcodes defined incorrectly.\r | |
43 | 48. SYS: TCH not decoding bit<19>.\r | |
44 | 49. IO: CTL not clearing EOR after device end.\r | |
45 | 50. DSK: Format code not incrementing track in writing all tracks in cylinder.\r | |
46 | 51. DSK: THA mode overwrites record structure of first record.\r | |
47 | 52. DSK: Write doesn't set channel request for initial word.\r | |
48 | 53. DSK: Saved record number was command digits 3..8 instead of 5..10.\r | |
49 | 54. CLK: Compute 60th's from location 5, so Chrono clock is in sync with interval clock.\r | |
50 | 55. CPU: Enable Chronolog clock if CTSS.\r | |
51 | 56. CPU: Read/write protection error not setting protection trap.\r | |
52 | 57. CPU: SCHx not setting protection trap in user mode.\r | |
53 | 58: CPU: Protection trap overwriting wrong location.\r | |
54 | 59. CPU: Stop message reporting physical, not virtual, PC.\r | |
55 | 60. IO: Test for "request another cycle" in channel processor was inverted.\r | |
56 | 61. IO: Valid bit handling incorrect across multiple transfers.\r | |
57 | 62. IO: BSR doesn't set EOF indicator.\r | |
58 | 63. IO: 7607 channel modeled incorrectly, could stall.\r | |
59 | 64. IO: All 7607 "effective NOP" conditions must be tested when a new command is\r | |
60 | decoded (wc == 0 for IOCx and IOSx, EOR set for IOSx and IORx).\r | |
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