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1 | /* i7094_sys.c: IBM 7094 simulator interface\r |
2 | \r | |
3 | Copyright (c) 2003-2006, Robert M Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | 29-Oct-06 RMS Added additional expanded core instructions\r | |
27 | 08-Jun-06 RMS Added Dave Pitts' binary loader\r | |
28 | */\r | |
29 | \r | |
30 | #include "i7094_defs.h"\r | |
31 | #include <ctype.h>\r | |
32 | #include "i7094_dat.h"\r | |
33 | \r | |
34 | extern DEVICE cpu_dev;\r | |
35 | extern DEVICE ch_dev[NUM_CHAN];\r | |
36 | extern DEVICE mt_dev[NUM_CHAN];\r | |
37 | extern DEVICE drm_dev;\r | |
38 | extern DEVICE dsk_dev;\r | |
39 | extern DEVICE com_dev, coml_dev;\r | |
40 | extern DEVICE cdr_dev, cdp_dev;\r | |
41 | extern DEVICE lpt_dev;\r | |
42 | extern DEVICE clk_dev;\r | |
43 | extern UNIT cpu_unit;\r | |
44 | extern REG cpu_reg[];\r | |
45 | \r | |
46 | uint32 cvt_code_to_ascii (uint32 c, int32 sw);\r | |
47 | uint32 cvt_ascii_to_code (uint32 c, int32 sw);\r | |
48 | \r | |
49 | /* SCP data structures and interface routines\r | |
50 | \r | |
51 | sim_name simulator name string\r | |
52 | sim_PC pointer to saved PC register descriptor\r | |
53 | sim_emax number of words for examine\r | |
54 | sim_devices array of pointers to simulated devices\r | |
55 | sim_stop_messages array of pointers to stop messages\r | |
56 | sim_load binary loader\r | |
57 | */\r | |
58 | \r | |
59 | char sim_name[] = "IBM 7094";\r | |
60 | \r | |
61 | REG *sim_PC = &cpu_reg[0];\r | |
62 | \r | |
63 | int32 sim_emax = 1;\r | |
64 | \r | |
65 | DEVICE *sim_devices[] = { \r | |
66 | &cpu_dev,\r | |
67 | &clk_dev,\r | |
68 | &ch_dev[0],\r | |
69 | &ch_dev[1],\r | |
70 | &ch_dev[2],\r | |
71 | &ch_dev[3],\r | |
72 | &ch_dev[4],\r | |
73 | &ch_dev[5],\r | |
74 | &ch_dev[6],\r | |
75 | &ch_dev[7],\r | |
76 | &mt_dev[0],\r | |
77 | &mt_dev[1],\r | |
78 | &mt_dev[2],\r | |
79 | &mt_dev[3],\r | |
80 | &mt_dev[4],\r | |
81 | &mt_dev[5],\r | |
82 | &mt_dev[6],\r | |
83 | &mt_dev[7],\r | |
84 | &cdr_dev,\r | |
85 | &cdp_dev,\r | |
86 | &lpt_dev,\r | |
87 | &dsk_dev,\r | |
88 | &drm_dev,\r | |
89 | &com_dev,\r | |
90 | &coml_dev,\r | |
91 | NULL\r | |
92 | };\r | |
93 | \r | |
94 | char ch_bkpt_msg[] = "Channel A breakpoint, CLC: xxxxxx";\r | |
95 | \r | |
96 | const char *sim_stop_messages[] = {\r | |
97 | "Unknown error",\r | |
98 | "HALT instruction",\r | |
99 | "Breakpoint",\r | |
100 | "Undefined instruction",\r | |
101 | "Divide check",\r | |
102 | "Nested XEC limit exceeded",\r | |
103 | "Address stop",\r | |
104 | "Non-existent channel",\r | |
105 | "Illegal instruction for 7909 channel",\r | |
106 | "Illegal instruction for non-7909 channel",\r | |
107 | "Non-existent device",\r | |
108 | "Undefined channel instruction",\r | |
109 | "Write to protected device",\r | |
110 | "Illegal instruction for device",\r | |
111 | "Invalid 7631 track format",\r | |
112 | "7750 buffer pool empty on input",\r | |
113 | "7750 buffer pool empty on output",\r | |
114 | "7750 invalid line number",\r | |
115 | "7750 invalid message",\r | |
116 | ch_bkpt_msg\r | |
117 | };\r | |
118 | \r | |
119 | /* Modify channel breakpoint message */\r | |
120 | \r | |
121 | t_stat ch_bkpt (uint32 ch, uint32 clc)\r | |
122 | {\r | |
123 | ch_bkpt_msg[8] = 'A' + ch;\r | |
124 | sprintf (&ch_bkpt_msg[27], "%06o", clc);\r | |
125 | return STOP_CHBKPT;\r | |
126 | }\r | |
127 | \r | |
128 | /* Binary loader, not implemented */\r | |
129 | \r | |
130 | t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)\r | |
131 | {\r | |
132 | extern t_stat binloader (FILE *fd, char *file, int loadpt);\r | |
133 | \r | |
134 | if (flag == 0)\r | |
135 | return binloader (fileref, cptr, 0);\r | |
136 | return SCPE_NOFNC;\r | |
137 | }\r | |
138 | \r | |
139 | /* Symbol tables */\r | |
140 | \r | |
141 | #define I_V_FL 39 /* inst class */\r | |
142 | #define I_M_FL 017 /* class mask */\r | |
143 | #define I_NOP 0000000000000000 /* no operand */\r | |
144 | #define I_MXR 0010000000000000 /* addr(tag) */\r | |
145 | #define I_MXN 0020000000000000 /* *addr(tag) */\r | |
146 | #define I_MXV 0030000000000000 /* var mul/div */\r | |
147 | #define I_MXC 0040000000000000 /* convert */\r | |
148 | #define I_DNP 0050000000000000 /* decr, no oper */\r | |
149 | #define I_DEC 0060000000000000 /* decrement */\r | |
150 | #define I_SNS 0070000000000000 /* sense */\r | |
151 | #define I_IMM 0100000000000000 /* 18b immediate */\r | |
152 | #define I_TAG 0110000000000000 /* tag only */\r | |
153 | #define I_IOX 0120000000000000 /* IO channel */\r | |
154 | #define I_TCH 0130000000000000 /* transfer channel */\r | |
155 | #define I_I9N 0140000000000000 /* 7909 with nostore */\r | |
156 | #define I_I9S 0150000000000000 /* 7909 */\r | |
157 | #define IFAKE_7607 0001000000000000 /* fake op extensions */\r | |
158 | #define IFAKE_7909 0002000000000000\r | |
159 | #define DFAKE (DMASK|IFAKE_7607|IFAKE_7909)\r | |
160 | #define I_N_NOP 000\r | |
161 | #define I_N_MXR 001\r | |
162 | #define I_N_MXN 002\r | |
163 | #define I_N_MXV 003\r | |
164 | #define I_N_MXC 004\r | |
165 | #define I_N_DNP 005\r | |
166 | #define I_N_DEC 006\r | |
167 | #define I_N_SNS 007\r | |
168 | #define I_N_IMM 010\r | |
169 | #define I_N_TAG 011\r | |
170 | #define I_N_IOX 012\r | |
171 | #define I_N_TCH 013\r | |
172 | #define I_N_I9N 014\r | |
173 | #define I_N_I9S 015\r | |
174 | \r | |
175 | #define INST_P_XIT 0 /* exit */\r | |
176 | #define INST_P_SKP 1 /* do not print */\r | |
177 | #define INST_P_PRA 2 /* print always */\r | |
178 | #define INST_P_PNZ 3 /* print if nz */\r | |
179 | #define INST_P_PNT 4 /* print if nz, term */\r | |
180 | \r | |
181 | static const t_uint64 masks[14] = {\r | |
182 | 03777700000000, 03777700000000,\r | |
183 | 03777700000000, 03777700000000,\r | |
184 | 03777400000000, 03700000000000,\r | |
185 | 03700000000000, 03777700077777,\r | |
186 | 03777700000000, 03777700000000,\r | |
187 | 03700000200000, 03700000200000,\r | |
188 | 03760000200000, 03740000200000 }; \r | |
189 | \r | |
190 | static const uint32 fld_max[14][3] = { /* addr,tag,decr limit */\r | |
191 | { INST_M_ADDR, INST_M_TAG, 0 },\r | |
192 | { INST_M_ADDR, INST_M_TAG, 0 },\r | |
193 | { INST_M_ADDR, INST_M_TAG, 0 },\r | |
194 | { INST_M_ADDR, INST_M_TAG, INST_M_VCNT },\r | |
195 | { INST_M_ADDR, INST_M_TAG, INST_M_CCNT },\r | |
196 | { INST_M_ADDR, INST_M_TAG, INST_M_DEC },\r | |
197 | { INST_M_ADDR, INST_M_TAG, INST_M_DEC },\r | |
198 | { 0, INST_M_TAG, 0 },\r | |
199 | { RMASK, 0, 0 },\r | |
200 | { INST_M_ADDR, INST_M_TAG, 0 },\r | |
201 | { INST_M_ADDR, 1, INST_M_DEC },\r | |
202 | { INST_M_ADDR, 1, 0 },\r | |
203 | { INST_M_ADDR, 1, 0 },\r | |
204 | { INST_M_ADDR, 1, 0 }\r | |
205 | };\r | |
206 | \r | |
207 | static const uint32 fld_fmt[14][3] = { /* addr,tag,decr print */\r | |
208 | { INST_P_PNT, INST_P_PNT, INST_P_XIT }, /* nop: all optional */\r | |
209 | { INST_P_PRA, INST_P_PNT, INST_P_XIT }, /* mxr: tag optional */\r | |
210 | { INST_P_PRA, INST_P_PNT, INST_P_XIT }, /* mxn: tag optional */\r | |
211 | { INST_P_PRA, INST_P_PNZ, INST_P_PRA }, /* mxv: tag optional */\r | |
212 | { INST_P_PRA, INST_P_PNZ, INST_P_PRA }, /* cvt: tag optional */\r | |
213 | { INST_P_PNT, INST_P_PNT, INST_P_PNT }, /* dnp: all optional */\r | |
214 | { INST_P_PRA, INST_P_PRA, INST_P_PRA }, /* dec: print all */\r | |
215 | { INST_P_SKP, INST_P_PNT, INST_P_XIT }, /* sns: skip addr, tag opt */\r | |
216 | { INST_P_PRA, INST_P_XIT, INST_P_XIT }, /* immediate: addr only */\r | |
217 | { INST_P_PNZ, INST_P_PRA, INST_P_XIT }, /* tag: addr optional */\r | |
218 | { INST_P_PRA, INST_P_PNZ, INST_P_PRA }, /* iox: tag optional */\r | |
219 | { INST_P_PRA, INST_P_PNT, INST_P_XIT }, /* tch: tag optional */\r | |
220 | { INST_P_PRA, INST_P_PNT, INST_P_XIT }, /* i9n: tag optional */\r | |
221 | { INST_P_PRA, INST_P_PNT, INST_P_XIT } /* i9s: tag optional */\r | |
222 | };\r | |
223 | \r | |
224 | static const t_uint64 ind_test[14] = {\r | |
225 | 0, 0, INST_IND, 0, 0, 0, 0,\r | |
226 | 0, 0, 0, CHI_IND, CHI_IND, CHI_IND, CHI_IND\r | |
227 | };\r | |
228 | \r | |
229 | static const char *opcode[] = {\r | |
230 | "TXI", "TIX", "TXH",\r | |
231 | "STR", "TNX", "TXL",\r | |
232 | "HTR", "TRA", "TTR",\r | |
233 | \r | |
234 | "CLM", "LBT", "CHS",\r | |
235 | "SSP", "ENK", "IOT",\r | |
236 | "COM", "ETM", "RND",\r | |
237 | "FRN", "DCT", "RCT",\r | |
238 | "LMTM", "SLF", "SLN1",\r | |
239 | "SLN2", "SLN3", "SLN4",\r | |
240 | "SWT1", "SWT2", "SWT3",\r | |
241 | "SWT4", "SWT5", "SWT6",\r | |
242 | "BTTA", "BTTB", "BTTC",\r | |
243 | "BTTD", "BTTE", "BTTF",\r | |
244 | "BTTG", "BTTH",\r | |
245 | "RICA", "RICB", "RICC",\r | |
246 | "RICD", "RICE", "RICF",\r | |
247 | "RICG", "RICH",\r | |
248 | "RDCA", "RDCB", "RDCC",\r | |
249 | "RDCD", "RDCE", "RDCF",\r | |
250 | "RDCG", "RDCH",\r | |
251 | \r | |
252 | "TRCA", "TRCC",\r | |
253 | "TRCE", "TRCG",\r | |
254 | "TEFA", "TEFC",\r | |
255 | "TEFE", "TEFG",\r | |
256 | "TLQ", "IIA", "TIO",\r | |
257 | "OAI", "PAI", "TIF",\r | |
258 | "IIR", "RFT", "SIR",\r | |
259 | "RNT", "RIR",\r | |
260 | "TCOA", "TCOB", "TCOC",\r | |
261 | "TCOD", "TCOE", "TCOF",\r | |
262 | "TCOG", "TCOH", "TSX",\r | |
263 | "TZE", "CVR", "TPL",\r | |
264 | "XCA", "TOV",\r | |
265 | "TQO", "TQP",\r | |
266 | "MPY", "VLM", "VLM1",\r | |
267 | "DVH", "DVP",\r | |
268 | "VDH", "VDP",\r | |
269 | "VDH2", "VDP2",\r | |
270 | "FDH", "FDP",\r | |
271 | "FMP", "DFMP",\r | |
272 | "FAD", "DFAD",\r | |
273 | "FSB", "DFSB",\r | |
274 | "FAM", "DFAM",\r | |
275 | "FSM", "DFSM",\r | |
276 | "ANS", "ERA",\r | |
277 | "CAS", "ACL",\r | |
278 | "ADD", "ADM",\r | |
279 | "SUB", "SBM",\r | |
280 | "HPR", "IIS", "LDI",\r | |
281 | "OSI", "DLD", "OFT",\r | |
282 | "RIS", "ONT",\r | |
283 | "CLA", "CLS",\r | |
284 | "ZET", "XEC",\r | |
285 | "LXA", "LAC",\r | |
286 | "RCHA", "RCHC",\r | |
287 | "RCHE", "RCHG",\r | |
288 | "LCHA", "LCHC",\r | |
289 | "LCHE", "LCHG",\r | |
290 | "RSCA", "RSCC",\r | |
291 | "RSCE", "RSCG",\r | |
292 | "STCA", "STCC",\r | |
293 | "STCE", "STCG",\r | |
294 | "LDQ", "ENB",\r | |
295 | "STZ", "STO", "SLW",\r | |
296 | "STI", "STA", "STD",\r | |
297 | "STT", "STP",\r | |
298 | "SXA", "SCA",\r | |
299 | "SCHA", "SCHC",\r | |
300 | "SCHE", "SCHG",\r | |
301 | "SCDA", "SCDC",\r | |
302 | "SCDE", "SCDG",\r | |
303 | "PAX", "PAC",\r | |
304 | "PXA", "PCA",\r | |
305 | "PSE", "NOP", "RDS",\r | |
306 | "LLS", "BSR", "LRS",\r | |
307 | "WRS", "ALS", "WEF",\r | |
308 | "ARS", "REW", "AXT",\r | |
309 | "SDN",\r | |
310 | \r | |
311 | "CLM", "PBT", "EFTM",\r | |
312 | "SSM", "LFTM", "ESTM",\r | |
313 | "ECTM", "LTM", "LSNM",\r | |
314 | "EMTM", "SLT1", "SLT2",\r | |
315 | "SLT3", "SLT4",\r | |
316 | "ETTA", "ETTB", "ETTC",\r | |
317 | "ETTD", "ETTE", "ETTF",\r | |
318 | "ETTG", "ETTH",\r | |
319 | \r | |
320 | "ESNT",\r | |
321 | "TRCB", "TRCD",\r | |
322 | "TRCF", "TRCH",\r | |
323 | "TEFB", "TEFD",\r | |
324 | "TEFF", "TEFH",\r | |
325 | "RIA", "PIA",\r | |
326 | "IIL", "LFT", "SIL",\r | |
327 | "LNT", "RIL",\r | |
328 | "TCNA", "TCNB", "TCNC",\r | |
329 | "TCND", "TCNE", "TCNF",\r | |
330 | "TCNG", "TCNH",\r | |
331 | "TNZ", "CVR", "TMI",\r | |
332 | "XCL", "TNO", "CRQ",\r | |
333 | "MPR", "DFDH", "DFDP",\r | |
334 | "UFM", "DUFM",\r | |
335 | "UFA", "DUFA",\r | |
336 | "UFS", "DUFS",\r | |
337 | "UAM", "DUAM",\r | |
338 | "USM", "DUSM",\r | |
339 | "ANA", "LAS",\r | |
340 | "CAL", "ORA", "NZT",\r | |
341 | "LXD", "LXC",\r | |
342 | "RCHB", "RCHD",\r | |
343 | "RCHF", "RCHH",\r | |
344 | "LCHB", "LCHD",\r | |
345 | "LCHF", "LCHH",\r | |
346 | "RSCB", "RSCD",\r | |
347 | "RSCF", "RSCH",\r | |
348 | "STCB", "STCD",\r | |
349 | "STCF", "STCH",\r | |
350 | "STQ", "ORS", "DST",\r | |
351 | "SLQ", "STL",\r | |
352 | "SXD", "SCD",\r | |
353 | "SCHB", "SCHD",\r | |
354 | "SCHF", "SCHH",\r | |
355 | "SCDB", "SCDD",\r | |
356 | "SCDF", "SCDH",\r | |
357 | "PDX", "PDC",\r | |
358 | "PXD", "PCD",\r | |
359 | "MSE", "LGL", "BSF",\r | |
360 | "LGR", "RQL", "RUN",\r | |
361 | "AXC",\r | |
362 | \r | |
363 | "TIA", "TIB",\r | |
364 | "LRI", "LPI",\r | |
365 | "SEA", "SEB",\r | |
366 | "IFT", "EFT",\r | |
367 | \r | |
368 | "IOCD", "IOCDN", "TCH",\r | |
369 | "IORP", "IORPN",\r | |
370 | "IORT", "IORTN",\r | |
371 | "IOCP", "IOCPN",\r | |
372 | "IOCT", "IOCTN",\r | |
373 | "IOSP", "IOSPN",\r | |
374 | "IOST", "IOSTN",\r | |
375 | \r | |
376 | "WTR", "XMT",\r | |
377 | "TCH", "LIPT",\r | |
378 | "CTL", "CTLN",\r | |
379 | "CTLR", "CTLRN",\r | |
380 | "CTLW", "CTLWN",\r | |
381 | "SNS",\r | |
382 | "LAR", "SAR", "TWT",\r | |
383 | "CPYP",\r | |
384 | "CPYD", "TCM",\r | |
385 | "LIP", "TDC", "LCC",\r | |
386 | "SMS", "ICC",\r | |
387 | \r | |
388 | NULL\r | |
389 | };\r | |
390 | \r | |
391 | static const t_uint64 opc_v[] = {\r | |
392 | 0100000000000+I_DEC, 0200000000000+I_DEC, 0300000000000+I_DEC,\r | |
393 | 0500000000000+I_DNP, 0600000000000+I_DEC, 0700000000000+I_DEC,\r | |
394 | 0000000000000+I_MXN, 0002000000000+I_MXN, 0002100000000+I_MXN,\r | |
395 | \r | |
396 | 0076000000000+I_SNS, 0076000000001+I_SNS, 0076000000002+I_SNS,\r | |
397 | 0076000000003+I_SNS, 0076000000004+I_SNS, 0076000000005+I_SNS,\r | |
398 | 0076000000006+I_SNS, 0076000000007+I_SNS, 0076000000010+I_SNS,\r | |
399 | 0076000000011+I_SNS, 0076000000012+I_SNS, 0076000000014+I_SNS,\r | |
400 | 0076000000016+I_SNS, 0076000000140+I_SNS, 0076000000141+I_SNS,\r | |
401 | 0076000000142+I_SNS, 0076000000143+I_SNS, 0076000000144+I_SNS,\r | |
402 | 0076000000161+I_SNS, 0076000000162+I_SNS, 0076000000163+I_SNS,\r | |
403 | 0076000000164+I_SNS, 0076000000165+I_SNS, 0076000000166+I_SNS,\r | |
404 | 0076000001000+I_SNS, 0076000002000+I_SNS, 0076000003000+I_SNS,\r | |
405 | 0076000004000+I_SNS, 0076000005000+I_SNS, 0076000006000+I_SNS,\r | |
406 | 0076000007000+I_SNS, 0076000010000+I_SNS,\r | |
407 | 0076000001350+I_SNS, 0076000002350+I_SNS, 0076000003350+I_SNS,\r | |
408 | 0076000004350+I_SNS, 0076000005350+I_SNS, 0076000006350+I_SNS,\r | |
409 | 0076000007350+I_SNS, 0076000010350+I_SNS,\r | |
410 | 0076000001352+I_SNS, 0076000002352+I_SNS, 0076000003352+I_SNS,\r | |
411 | 0076000004352+I_SNS, 0076000005352+I_SNS, 0076000006352+I_SNS,\r | |
412 | 0076000007352+I_SNS, 0076000010352+I_SNS,\r | |
413 | \r | |
414 | 0002200000000+I_MXN, 0002400000000+I_MXN,\r | |
415 | 0002600000000+I_MXN, 0002700000000+I_MXN,\r | |
416 | 0003000000000+I_MXN, 0003100000000+I_MXN,\r | |
417 | 0003200000000+I_MXN, 0003300000000+I_MXN,\r | |
418 | 0004000000000+I_MXN, 0004100000000+I_NOP, 0004200000000+I_MXR,\r | |
419 | 0004300000000+I_NOP, 0004400000000+I_NOP, 0004600000000+I_MXR,\r | |
420 | 0005100000000+I_IMM, 0005400000000+I_IMM, 0005500000000+I_IMM,\r | |
421 | 0005600000000+I_IMM, 0005700000000+I_IMM,\r | |
422 | 0006000000000+I_MXN, 0006100000000+I_MXN, 0006200000000+I_MXN,\r | |
423 | 0006300000000+I_MXN, 0006400000000+I_MXN, 0006500000000+I_MXN,\r | |
424 | 0006600000000+I_MXN, 0006700000000+I_MXN, 0007400000000+I_MXR,\r | |
425 | 0010000000000+I_MXN, 0011400000000+I_MXC, 0012000000000+I_MXN,\r | |
426 | 0013100000000+I_NOP, 0014000000000+I_MXN,\r | |
427 | 0016100000000+I_MXN, 0016200000000+I_MXN,\r | |
428 | 0020000000000+I_MXN, 0020400000000+I_MXV, 0020500000000+I_MXV,\r | |
429 | 0022000000000+I_MXN, 0022100000000+I_MXN,\r | |
430 | 0022400000000+I_MXV, 0022500000000+I_MXV,\r | |
431 | 0022600000000+I_MXV, 0022700000000+I_MXV,\r | |
432 | 0024000000000+I_MXN, 0024100000000+I_MXN,\r | |
433 | 0026000000000+I_MXN, 0026100000000+I_MXN,\r | |
434 | 0030000000000+I_MXN, 0030100000000+I_MXN,\r | |
435 | 0030200000000+I_MXN, 0030300000000+I_MXN,\r | |
436 | 0030400000000+I_MXN, 0030500000000+I_MXN,\r | |
437 | 0030600000000+I_MXN, 0030700000000+I_MXN,\r | |
438 | 0032000000000+I_MXN, 0032200000000+I_MXN,\r | |
439 | 0034000000000+I_MXN, 0036100000000+I_MXN,\r | |
440 | 0040000000000+I_MXN, 0040100000000+I_MXN,\r | |
441 | 0040200000000+I_MXN, 0440000000000+I_MXN,\r | |
442 | 0042000000000+I_NOP, 0044000000000+I_MXN, 0044100000000+I_MXN,\r | |
443 | 0044200000000+I_MXN, 0044300000000+I_MXN, 0044400000000+I_MXN,\r | |
444 | 0044500000000+I_MXN, 0044600000000+I_MXN,\r | |
445 | 0050000000000+I_MXN, 0050200000000+I_MXN,\r | |
446 | 0052000000000+I_MXN, 0052200000000+I_MXN,\r | |
447 | 0053400000000+I_MXR, 0053500000000+I_MXR,\r | |
448 | 0054000000000+I_MXN, 0054100000000+I_MXN,\r | |
449 | 0054200000000+I_MXN, 0054300000000+I_MXN,\r | |
450 | 0054400000000+I_MXN, 0054500000000+I_MXN,\r | |
451 | 0054600000000+I_MXN, 0054700000000+I_MXN,\r | |
452 | 0054000000000+I_MXN, 0054100000000+I_MXN,\r | |
453 | 0054200000000+I_MXN, 0054300000000+I_MXN,\r | |
454 | 0054400000000+I_MXN, 0054500000000+I_MXN,\r | |
455 | 0054600000000+I_MXN, 0054700000000+I_MXN,\r | |
456 | 0056000000000+I_MXN, 0056400000000+I_MXN,\r | |
457 | 0060000000000+I_MXN, 0060100000000+I_MXN, 0060200000000+I_MXN,\r | |
458 | 0060400000000+I_MXN, 0062100000000+I_MXN, 0062200000000+I_MXN,\r | |
459 | 0062500000000+I_MXN, 0063000000000+I_MXN,\r | |
460 | 0063400000000+I_MXR, 0063600000000+I_MXR,\r | |
461 | 0064000000000+I_MXN, 0064000000000+I_MXN,\r | |
462 | 0064200000000+I_MXN, 0064300000000+I_MXN,\r | |
463 | 0064400000000+I_MXN, 0064500000000+I_MXN,\r | |
464 | 0064600000000+I_MXN, 0064700000000+I_MXN,\r | |
465 | 0073400000000+I_TAG, 0073700000000+I_TAG,\r | |
466 | 0075400000000+I_TAG, 0075600000000+I_TAG,\r | |
467 | 0076000000000+I_MXR, 0076100000000+I_NOP, 0076200000000+I_MXR,\r | |
468 | 0076300000000+I_MXR, 0076400000000+I_MXR, 0076500000000+I_MXR,\r | |
469 | 0076600000000+I_MXR, 0076700000000+I_MXR, 0077000000000+I_MXR,\r | |
470 | 0077100000000+I_MXR, 0077200000000+I_MXR, 0077400000000+I_MXR,\r | |
471 | 0077600000000+I_MXR,\r | |
472 | \r | |
473 | 0476000000000+I_SNS, 0476000000001+I_SNS, 0476000000002+I_SNS,\r | |
474 | 0476000000003+I_SNS, 0476000000004+I_SNS, 0476000000005+I_SNS,\r | |
475 | 0476000000006+I_SNS, 0476000000007+I_SNS, 0476000000010+I_SNS,\r | |
476 | 0476000000016+I_SNS, 0476000000141+I_SNS, 0476000000142+I_SNS,\r | |
477 | 0476000000143+I_SNS, 0476000000144+I_SNS,\r | |
478 | 0476000001000+I_SNS, 0476000002000+I_SNS, 0476000003000+I_SNS,\r | |
479 | 0476000004000+I_SNS, 0476000005000+I_SNS, 0476000006000+I_SNS,\r | |
480 | 0476000007000+I_SNS, 0476000010000+I_SNS,\r | |
481 | \r | |
482 | 0402100000000+I_MXN,\r | |
483 | 0402200000000+I_MXN, 0402400000000+I_MXN,\r | |
484 | 0402600000000+I_MXN, 0402700000000+I_MXN,\r | |
485 | 0403000000000+I_MXN, 0403100000000+I_MXN,\r | |
486 | 0403200000000+I_MXN, 0403300000000+I_MXN,\r | |
487 | 0404200000000+I_NOP, 0404600000000+I_NOP,\r | |
488 | 0405100000000+I_IMM, 0405400000000+I_IMM, 0405500000000+I_IMM,\r | |
489 | 0405600000000+I_IMM, 0405700000000+I_IMM,\r | |
490 | 0406000000000+I_MXN, 0406100000000+I_MXN, 0406200000000+I_MXN,\r | |
491 | 0406300000000+I_MXN, 0406400000000+I_MXN, 0406500000000+I_MXN,\r | |
492 | 0406600000000+I_MXN, 0406700000000+I_MXN, \r | |
493 | 0410000000000+I_MXN, 0411400000000+I_MXC, 0412000000000+I_MXN,\r | |
494 | 0413000000000+I_NOP, 0414000000000+I_MXN, 0415400000000+I_MXC,\r | |
495 | 0420000000000+I_MXN, 0424000000000+I_MXN, 0424100000000+I_MXN,\r | |
496 | 0426000000000+I_MXN, 0426100000000+I_MXN,\r | |
497 | 0430000000000+I_MXN, 0430100000000+I_MXN,\r | |
498 | 0430200000000+I_MXN, 0430300000000+I_MXN,\r | |
499 | 0430400000000+I_MXN, 0430500000000+I_MXN,\r | |
500 | 0430600000000+I_MXN, 0430700000000+I_MXN,\r | |
501 | 0432000000000+I_MXN, 0434000000000+I_MXN,\r | |
502 | 0450000000000+I_MXN, 0450100000000+I_MXN, 0452000000000+I_MXN,\r | |
503 | 0453400000000+I_MXR, 0453500000000+I_MXR,\r | |
504 | 0454000000000+I_MXN, 0454100000000+I_MXN,\r | |
505 | 0454200000000+I_MXN, 0454300000000+I_MXN,\r | |
506 | 0454400000000+I_MXN, 0454500000000+I_MXN,\r | |
507 | 0454600000000+I_MXN, 0454700000000+I_MXN,\r | |
508 | 0454000000000+I_MXN, 0454100000000+I_MXN,\r | |
509 | 0454200000000+I_MXN, 0454300000000+I_MXN,\r | |
510 | 0454400000000+I_MXN, 0454500000000+I_MXN,\r | |
511 | 0454600000000+I_MXN, 0454700000000+I_MXN,\r | |
512 | 0460000000000+I_MXN, 0460200000000+I_MXN, 0460300000000+I_MXN,\r | |
513 | 0462000000000+I_MXN, 0462500000000+I_MXN,\r | |
514 | 0463400000000+I_MXR, 0463600000000+I_MXR,\r | |
515 | 0464000000000+I_MXN, 0464000000000+I_MXN,\r | |
516 | 0464200000000+I_MXN, 0464300000000+I_MXN,\r | |
517 | 0464400000000+I_MXN, 0464500000000+I_MXN,\r | |
518 | 0464600000000+I_MXN, 0464700000000+I_MXN,\r | |
519 | 0473400000000+I_TAG, 0473700000000+I_TAG,\r | |
520 | 0475400000000+I_TAG, 0475600000000+I_TAG,\r | |
521 | 0476000000000+I_MXR, 0476300000000+I_MXR, 0476400000000+I_MXR,\r | |
522 | 0476500000000+I_MXR, 0477300000000+I_MXR, 0477200000000+I_MXR,\r | |
523 | 0477400000000+I_MXR,\r | |
524 | \r | |
525 | 0010100000000+I_MXN, 0410100000000+I_MXN,\r | |
526 | 0056200000000+I_MXN, 0456400000000+I_MXN,\r | |
527 | 0476100000041+I_SNS, 0476100000042+I_SNS,\r | |
528 | 0476100000043+I_SNS, 0476100000044+I_SNS,\r | |
529 | \r | |
530 | 01000000000000+I_IOX, 01000000200000+I_IOX, 01100000000000+I_TCH,\r | |
531 | 01200000000000+I_IOX, 01200000200000+I_IOX,\r | |
532 | 01300000000000+I_IOX, 01300000200000+I_IOX,\r | |
533 | 01400000000000+I_IOX, 01400000200000+I_IOX,\r | |
534 | 01500000000000+I_IOX, 01500000200000+I_IOX,\r | |
535 | 01600000000000+I_IOX, 01600000200000+I_IOX,\r | |
536 | 01700000000000+I_IOX, 01700000200000+I_IOX,\r | |
537 | \r | |
538 | 02000000000000+I_TCH, 02000000200000+I_IOX,\r | |
539 | 02100000000000+I_TCH, 02100000200000+I_TCH,\r | |
540 | 02200000000000+I_I9N, 02220000000000+I_TCH,\r | |
541 | 02200000200000+I_I9N, 02220000200000+I_TCH,\r | |
542 | 02240000000000+I_I9N, 02260000000000+I_TCH,\r | |
543 | 02240000200000+I_I9N,\r | |
544 | 02300000000000+I_I9S, 02300000200000+I_I9S,\r | |
545 | 02340000000000+I_I9S,\r | |
546 | 02400000000000+I_IOX,\r | |
547 | 02500000000000+I_IOX, 02500000200000+I_IOX,\r | |
548 | 02600000200000+I_I9S, 02640000000000+I_I9S, 02640000200000+I_I9S,\r | |
549 | 02700000000000+I_I9S, 02700000200000+I_IOX,\r | |
550 | \r | |
551 | 0\r | |
552 | };\r | |
553 | \r | |
554 | /* Symbolic decode\r | |
555 | \r | |
556 | Inputs:\r | |
557 | *of = output stream\r | |
558 | addr = current PC\r | |
559 | *val = pointer to values\r | |
560 | *uptr = pointer to unit\r | |
561 | sw = switches\r | |
562 | Outputs:\r | |
563 | return = status code\r | |
564 | */\r | |
565 | \r | |
566 | t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,\r | |
567 | UNIT *uptr, int32 sw)\r | |
568 | {\r | |
569 | uint32 i, j, k, l, fmt, c, fld[3];\r | |
570 | DEVICE *dptr;\r | |
571 | t_uint64 inst;\r | |
572 | \r | |
573 | inst = val[0];\r | |
574 | if (uptr == NULL) uptr = &cpu_unit;\r | |
575 | dptr = find_dev_from_unit (uptr);\r | |
576 | if (dptr == NULL) return SCPE_IERR;\r | |
577 | \r | |
578 | if (sw & SWMASK ('C')) { /* character? */\r | |
579 | c = (uint32) (inst & 077);\r | |
580 | fprintf (of, "%c", cvt_code_to_ascii (c, sw));\r | |
581 | return SCPE_OK;\r | |
582 | }\r | |
583 | if (sw & SWMASK ('S')) { /* string? */\r | |
584 | for (i = 36; i > 0; i = i - 6) {\r | |
585 | c = (uint32) ((inst >> (i - 6)) & 077);\r | |
586 | fprintf (of, "%c", cvt_code_to_ascii (c, sw));\r | |
587 | } \r | |
588 | return SCPE_OK;\r | |
589 | }\r | |
590 | if (!(sw & (SWMASK ('M')|SWMASK ('I')|SWMASK ('N'))) || /* M, N or I? */\r | |
591 | (dptr->dwidth != 36)) return SCPE_ARG;\r | |
592 | \r | |
593 | /* Instruction decode */\r | |
594 | \r | |
595 | fld[0] = ((uint32) inst & 0777777);\r | |
596 | fld[1] = GET_TAG (inst); /* get 3 fields */\r | |
597 | fld[2] = GET_DEC (inst);\r | |
598 | if (sw & SWMASK ('I')) inst |= IFAKE_7607; /* decode as 7607? */\r | |
599 | if (sw & SWMASK ('N')) inst |= IFAKE_7909; /* decode as 7909? */\r | |
600 | \r | |
601 | for (i = 0; opc_v[i] > 0; i++) { /* loop thru ops */\r | |
602 | j = (int32) ((opc_v[i] >> I_V_FL) & I_M_FL); /* get class */\r | |
603 | if ((opc_v[i] & DFAKE) == (inst & masks[j])) { /* match? */\r | |
604 | if (inst & ind_test[j]) /* indirect? */\r | |
605 | fprintf (of, "%s*", opcode[i]);\r | |
606 | else fprintf (of, "%s", opcode[i]); /* opcode */\r | |
607 | for (k = 0; k < 3; k++) fld[k] = fld[k] & fld_max[j][k];\r | |
608 | for (k = 0; k < 3; k++) { /* loop thru fields */\r | |
609 | fmt = fld_fmt[j][k]; /* get format */\r | |
610 | if (fmt == INST_P_XIT) return SCPE_OK;\r | |
611 | switch (fmt) { /* case on format */\r | |
612 | \r | |
613 | case INST_P_PNT: /* print nz, else term */\r | |
614 | for (l = k, c = 0; l < 3; l++) c |= fld[k];\r | |
615 | if (c == 0) return SCPE_OK;\r | |
616 | case INST_P_PNZ: /* print non-zero */\r | |
617 | fputc (k? ',': ' ', of);\r | |
618 | if (fld[k]) fprintf (of, "%-o", fld[k]);\r | |
619 | break;\r | |
620 | case INST_P_PRA: /* print always */\r | |
621 | fputc (k? ',': ' ', of);\r | |
622 | fprintf (of, "%-o", fld[k]);\r | |
623 | break;\r | |
624 | case INST_P_SKP: /* skip */\r | |
625 | break;\r | |
626 | } /* end switch */\r | |
627 | } /* end for k */\r | |
628 | return SCPE_OK; /* done */\r | |
629 | } /* end if */\r | |
630 | } /* end for i */\r | |
631 | return SCPE_ARG;\r | |
632 | }\r | |
633 | \r | |
634 | /* Convert character to code to ASCII\r | |
635 | \r | |
636 | -b BCD\r | |
637 | -a business-chain */\r | |
638 | \r | |
639 | uint32 cvt_code_to_ascii (uint32 c, int32 sw)\r | |
640 | {\r | |
641 | if (sw & SWMASK ('B')) {\r | |
642 | if (sw & SWMASK ('A')) return bcd_to_ascii_a[c];\r | |
643 | else return bcd_to_ascii_h[c];\r | |
644 | }\r | |
645 | else if (sw & SWMASK ('A')) return nine_to_ascii_a[c];\r | |
646 | else return nine_to_ascii_h[c];\r | |
647 | }\r | |
648 | \r | |
649 | /* Symbolic input\r | |
650 | \r | |
651 | Inputs:\r | |
652 | *cptr = pointer to input string\r | |
653 | addr = current PC\r | |
654 | uptr = pointer to unit\r | |
655 | *val = pointer to output values\r | |
656 | sw = switches\r | |
657 | Outputs:\r | |
658 | status = error status\r | |
659 | */\r | |
660 | \r | |
661 | t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)\r | |
662 | {\r | |
663 | uint32 i, j, c;\r | |
664 | t_uint64 fld[3];\r | |
665 | t_bool ind;\r | |
666 | t_stat r;\r | |
667 | char gbuf[CBUFSIZE];\r | |
668 | \r | |
669 | while (isspace (*cptr)) cptr++;\r | |
670 | if ((sw & SWMASK ('C')) || ((*cptr == '\'') && cptr++)) { /* character? */\r | |
671 | if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */\r | |
672 | val[0] = (t_value) cvt_ascii_to_code (cptr[0] & 0177, sw);\r | |
673 | return SCPE_OK;\r | |
674 | }\r | |
675 | if ((sw & SWMASK ('S')) || ((*cptr == '"') && cptr++)) { /* sixbit string? */\r | |
676 | if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */\r | |
677 | for (i = 0; i < 6; i++) {\r | |
678 | c = cptr[0] & 0177;\r | |
679 | if (c) val[0] = (val[0] << 6) | ((t_value) cvt_ascii_to_code (c, sw));\r | |
680 | else {\r | |
681 | val[0] = val[0] << (6 * (6 - i));\r | |
682 | break;\r | |
683 | }\r | |
684 | }\r | |
685 | return SCPE_OK;\r | |
686 | }\r | |
687 | \r | |
688 | cptr = get_glyph (cptr, gbuf, 0); /* get opcode */\r | |
689 | j = strlen (gbuf); /* get length */\r | |
690 | if (gbuf[j - 1] == '*') { /* indirect? */\r | |
691 | ind = TRUE;\r | |
692 | gbuf[j - 1] = 0;\r | |
693 | }\r | |
694 | else ind = FALSE;\r | |
695 | for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;\r | |
696 | if (opcode[i] == NULL) return SCPE_ARG;\r | |
697 | j = (uint32) ((opc_v[i] >> I_V_FL) & I_M_FL); /* get class */\r | |
698 | val[0] = opc_v[i] & DMASK;\r | |
699 | if (ind) {\r | |
700 | if (ind_test[j]) val[0] |= ind_test[j];\r | |
701 | else return SCPE_ARG;\r | |
702 | }\r | |
703 | \r | |
704 | for (i = 0; i < 3; i++) fld[i] = 0; /* clear inputs */\r | |
705 | for (i = 0; (i < 3) && *cptr; i++) { /* parse inputs */\r | |
706 | if (i < 2) cptr = get_glyph (cptr, gbuf, ','); /* get glyph */\r | |
707 | else cptr = get_glyph (cptr, gbuf, 0);\r | |
708 | if (gbuf[0]) { /* anything? */\r | |
709 | fld[i] = get_uint (gbuf, 8, fld_max[j][i], &r);\r | |
710 | if ((r != SCPE_OK) || (fld_max[j][i] == 0)) return SCPE_ARG;\r | |
711 | }\r | |
712 | }\r | |
713 | if (*cptr != 0) return SCPE_ARG; /* junk at end? */\r | |
714 | \r | |
715 | val[0] = val[0] | fld[0] | (fld[1] << INST_V_TAG) | (fld[2] << INST_V_DEC);\r | |
716 | return SCPE_OK;\r | |
717 | }\r | |
718 | \r | |
719 | /* Convert ASCII to character code\r | |
720 | \r | |
721 | -b BCD */\r | |
722 | \r | |
723 | uint32 cvt_ascii_to_code (uint32 c, int32 sw)\r | |
724 | {\r | |
725 | if (sw & SWMASK ('B')) return ascii_to_bcd[c];\r | |
726 | else return ascii_to_nine[c];\r | |
727 | }\r |