Commit | Line | Data |
---|---|---|
196ba1fc PH |
1 | /* id_idc.c: Interdata MSM/IDC disk controller simulator\r |
2 | \r | |
3 | Copyright (c) 2001-2006, Robert M. Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | idc MSM/IDC disk controller\r | |
27 | \r | |
28 | 03-Apr-06 RMS Fixed WD/WH handling (found by Davis Johnson)\r | |
29 | 30-Mar-06 RMS Fixed bug, nop command should be ignored (found by Davis Johnson)\r | |
30 | 25-Apr-03 RMS Revised for extended file support\r | |
31 | 16-Feb-03 RMS Fixed read to test transfer ok before selch operation\r | |
32 | \r | |
33 | Note: define flag ID_IDC to enable the extra functions of the intelligent\r | |
34 | disk controller\r | |
35 | */\r | |
36 | \r | |
37 | #include "id_defs.h"\r | |
38 | \r | |
39 | #define IDC_NUMBY 256 /* bytes/sector */\r | |
40 | #define IDC_NUMSC 64 /* sectors/track */\r | |
41 | \r | |
42 | #define UNIT_V_WLK (UNIT_V_UF + 0) /* write locked */\r | |
43 | #define UNIT_V_DTYPE (UNIT_V_UF + 1) /* disk type */\r | |
44 | #define UNIT_M_DTYPE 0x7\r | |
45 | #define UNIT_V_AUTO (UNIT_V_UF + 4) /* autosize */\r | |
46 | #define UNIT_WLK (1 << UNIT_V_WLK)\r | |
47 | #define UNIT_DTYPE (UNIT_M_DTYPE << UNIT_V_DTYPE)\r | |
48 | #define UNIT_AUTO (1 << UNIT_V_AUTO)\r | |
49 | #define GET_DTYPE(x) (((x) >> UNIT_V_DTYPE) & UNIT_M_DTYPE)\r | |
50 | \r | |
51 | #define CYL u3 /* current cylinder */\r | |
52 | #define HD u4 /* current head */\r | |
53 | #define STD buf /* drive status */\r | |
54 | #define FNC wait /* function */\r | |
55 | #define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protect */\r | |
56 | \r | |
57 | #define IDC_DRVMASK ((1 << ID_NUMDR) - 1) /* drive bit mask */\r | |
58 | #define IDC_DIRMASK (IDC_DRVMASK << (i_IDC + 1)) /* drive irq mask */\r | |
59 | \r | |
60 | /* Controller status */\r | |
61 | \r | |
62 | #define STC_WRP 0x80 /* write protected */\r | |
63 | #define STC_ACF 0x40 /* addr cmp fail */\r | |
64 | #define STC_DEF 0x20 /* def track NI */\r | |
65 | #define STC_CYO 0x10 /* cylinder ovflo */\r | |
66 | #define STC_IDL 0x02 /* ctrl idle */\r | |
67 | #define STC_DTE 0x01 /* xfer error */\r | |
68 | #define SETC_EX (STC_WRP|STC_ACF|STC_DEF|STC_CYO)\r | |
69 | #define STC_MASK (STC_WRP|STC_ACF|STC_DEF|STC_CYO|STA_BSY|STC_IDL|STC_DTE)\r | |
70 | \r | |
71 | /* Controller command */\r | |
72 | \r | |
73 | #define CMC_MASK 0x3F \r | |
74 | #define CMC_CLR 0x08 /* reset */\r | |
75 | #define CMC_RD 0x01 /* read */\r | |
76 | #define CMC_WR 0x02 /* write */\r | |
77 | #define CMC_RCHK 0x03 /* read check */\r | |
78 | #define CMC_FCHK 0x04 /* format check NI */\r | |
79 | #define CMC_RFMT 0x05 /* read fmt NI */\r | |
80 | #define CMC_WFMT 0x06 /* write fmt NI */\r | |
81 | #define CMC_WFTK 0x07 /* write fmt track NI */\r | |
82 | \r | |
83 | /* IDC only functions */\r | |
84 | \r | |
85 | #define CMC_RRAM 0x10 /* read RAM */\r | |
86 | #define CMC_WRAM 0x11 /* write RAM */\r | |
87 | #define CMC_EXP0 0x12 /* read page 0 NI */\r | |
88 | #define CMC_RUNC 0x21 /* read uncorr */\r | |
89 | #define CMC_STST 0x30 /* self test */\r | |
90 | #define CMC_WLNG 0x32 /* write long NI */\r | |
91 | #define CMC_LAMP 0x37 /* lamp test */\r | |
92 | \r | |
93 | #define CMC_DRV 0x100 /* drive func */\r | |
94 | #define CMC_DRV1 0x200 /* drive func, part 2 */\r | |
95 | \r | |
96 | /* Drive status, ^ = dynamic, * = in unit status */\r | |
97 | \r | |
98 | #define STD_WRP 0x80 /* ^write prot */\r | |
99 | /* 0x40 /* unused */\r | |
100 | #define STD_ACH 0x20 /* alt chan busy NI */\r | |
101 | #define STD_UNS 0x10 /* *unsafe */\r | |
102 | #define STD_NRDY 0x08 /* ^not ready */\r | |
103 | #define STD_SKI 0x02 /* *seek incomplete */\r | |
104 | #define STD_OFFL 0x01 /* ^offline */\r | |
105 | #define STD_UST (STD_UNS | STD_SKI) /* set from unit */\r | |
106 | #define SETD_EX (STD_WRP | STD_UNS) /* set examine */\r | |
107 | \r | |
108 | /* Drive command */\r | |
109 | \r | |
110 | #define CMDF_SHD 0x20 /* set head */\r | |
111 | #define CMDF_SCY 0x10 /* set cylinder */\r | |
112 | #define CMD_SK 0x02 /* seek */\r | |
113 | #define CMD_RST 0x01 /* restore */\r | |
114 | \r | |
115 | #define CMDX_MASK 0x30 /* ext cmd bits */\r | |
116 | #define CMDX_RLS 0x80 /* release */\r | |
117 | #define CMDX_CLF 0x40 /* clear fault */\r | |
118 | #define CMDX_SVP 0x08 /* servo + */\r | |
119 | #define CMDX_SVM 0x04 /* servo - */\r | |
120 | #define CMDX_DSP 0x02 /* strobe + */\r | |
121 | #define CMDX_DSM 0x01 /* strobe - */\r | |
122 | \r | |
123 | /* Geometry masks */\r | |
124 | \r | |
125 | #define CY_MASK 0xFFF /* cylinder */\r | |
126 | #define HD_MASK 0x1F /* head mask */\r | |
127 | #define SC_MASK 0x3F /* sector mask */\r | |
128 | #define HCYL_V_HD 10 /* head/cyl word */\r | |
129 | #define HCYL_V_CYL 0\r | |
130 | \r | |
131 | #define GET_SA(cy,sf,sc,t) \\r | |
132 | (((((cy)*drv_tab[t].surf)+(sf))*IDC_NUMSC)+(sc))\r | |
133 | \r | |
134 | /* The MSM (IDC) controller supports (two) six different disk drive types:\r | |
135 | \r | |
136 | type #sectors/ #surfaces/ #cylinders/\r | |
137 | surface cylinder drive\r | |
138 | \r | |
139 | MCCDD16 64 1 823 IDC\r | |
140 | MCCDD48 64 3 823 IDC\r | |
141 | MCCDD80 64 5 823 IDC\r | |
142 | MSM80 64 5 823 MSM\r | |
143 | MSM300 64 19 823 MSM\r | |
144 | MSM330F 64 16 1024 IDC\r | |
145 | \r | |
146 | In theory, each drive can be a different type. The size field in\r | |
147 | each unit selects the drive capacity for each drive and thus the\r | |
148 | drive type. DISKS MUST BE DECLARED IN ASCENDING SIZE AND MUST HAVE\r | |
149 | THE SAME SECTORS/TRACK.\r | |
150 | */\r | |
151 | \r | |
152 | #define TYPE_MCCDD16 0\r | |
153 | #define SURF_MCCDD16 1\r | |
154 | #define CYL_MCCDD16 823\r | |
155 | #define SIZE_MCCDD16 (IDC_NUMSC * SURF_MCCDD16 * CYL_MCCDD16 * IDC_NUMBY)\r | |
156 | \r | |
157 | #define TYPE_MCCDD48 1\r | |
158 | #define SURF_MCCDD48 3\r | |
159 | #define CYL_MCCDD48 823\r | |
160 | #define SIZE_MCCDD48 (IDC_NUMSC * SURF_MCCDD48 * CYL_MCCDD48 * IDC_NUMBY)\r | |
161 | \r | |
162 | #define TYPE_MCCDD80 2\r | |
163 | #define SURF_MCCDD80 5\r | |
164 | #define CYL_MCCDD80 823\r | |
165 | #define SIZE_MCCDD80 (IDC_NUMSC * SURF_MCCDD80 * CYL_MCCDD80 * IDC_NUMBY)\r | |
166 | \r | |
167 | #define TYPE_MSM80 3\r | |
168 | #define SURF_MSM80 5\r | |
169 | #define CYL_MSM80 823\r | |
170 | #define SIZE_MSM80 (IDC_NUMSC * SURF_MSM80 * CYL_MSM80 * IDC_NUMBY)\r | |
171 | \r | |
172 | #define TYPE_MSM300 4\r | |
173 | #define SURF_MSM300 19\r | |
174 | #define CYL_MSM300 823\r | |
175 | #define SIZE_MSM300 (IDC_NUMSC * SURF_MSM300 * CYL_MSM300 * IDC_NUMBY)\r | |
176 | \r | |
177 | #define TYPE_MSM330F 5\r | |
178 | #define SURF_MSM330F 16\r | |
179 | #define CYL_MSM330F 1024\r | |
180 | #define SIZE_MSM330F (IDC_NUMSC * SURF_MSM330F * CYL_MSM330F * IDC_NUMBY)\r | |
181 | \r | |
182 | \r | |
183 | struct drvtyp {\r | |
184 | uint32 surf; /* surfaces */\r | |
185 | uint32 cyl; /* cylinders */\r | |
186 | uint32 size; /* #blocks */\r | |
187 | uint32 msmf; /* MSM drive */\r | |
188 | };\r | |
189 | \r | |
190 | static struct drvtyp drv_tab[] = {\r | |
191 | { SURF_MCCDD16, CYL_MCCDD16, SIZE_MCCDD16, 0 },\r | |
192 | { SURF_MCCDD48, CYL_MCCDD48, SIZE_MCCDD48, 0 },\r | |
193 | { SURF_MCCDD80, CYL_MCCDD80, SIZE_MCCDD80, 0 },\r | |
194 | { SURF_MSM80, CYL_MSM80, SIZE_MSM80, 1 },\r | |
195 | { SURF_MSM300, CYL_MSM300, SIZE_MSM300, 1 },\r | |
196 | { SURF_MSM330F, CYL_MSM330F, SIZE_MSM330F, 0 },\r | |
197 | { 0 }\r | |
198 | };\r | |
199 | \r | |
200 | extern uint32 int_req[INTSZ], int_enb[INTSZ];\r | |
201 | \r | |
202 | uint8 idcxb[IDC_NUMBY * 3]; /* xfer buffer */\r | |
203 | uint32 idc_bptr = 0; /* buffer ptr */\r | |
204 | uint32 idc_wdptr = 0; /* ctrl write data ptr */\r | |
205 | uint32 idc_db = 0; /* ctrl buffer */\r | |
206 | uint32 idc_sta = 0; /* ctrl status */\r | |
207 | uint32 idc_sec = 0; /* sector */\r | |
208 | uint32 idc_hcyl = 0; /* head/cyl */\r | |
209 | uint32 idc_svun = 0; /* most recent unit */\r | |
210 | uint32 idc_1st = 0; /* first byte */\r | |
211 | uint32 idc_arm = 0; /* ctrl armed */\r | |
212 | uint32 idd_db = 0; /* drive buffer */\r | |
213 | uint32 idd_wdptr = 0; /* drive write data ptr */\r | |
214 | uint32 idd_arm[ID_NUMDR] = { 0 }; /* drives armed */\r | |
215 | uint16 idd_dcy[ID_NUMDR] = { 0 }; /* desired cyl */\r | |
216 | uint32 idd_sirq = 0; /* drive saved irq */\r | |
217 | int32 idc_stime = 100; /* seek latency */\r | |
218 | int32 idc_rtime = 100; /* rotate latency */\r | |
219 | int32 idc_ctime = 5; /* command latency */\r | |
220 | uint8 idc_tplte[] = { 0, 1, 2, 3, 4, TPL_END }; /* ctrl + drive */\r | |
221 | \r | |
222 | DEVICE idc_dev;\r | |
223 | uint32 id (uint32 dev, uint32 op, uint32 dat);\r | |
224 | t_stat idc_svc (UNIT *uptr);\r | |
225 | t_stat idc_reset (DEVICE *dptr);\r | |
226 | t_stat idc_attach (UNIT *uptr, char *cptr);\r | |
227 | t_stat idc_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
228 | void idc_wd_byte (uint32 dat);\r | |
229 | t_stat idc_rds (UNIT *uptr);\r | |
230 | t_stat idc_wds (UNIT *uptr);\r | |
231 | t_bool idc_dter (UNIT *uptr, uint32 first);\r | |
232 | void idc_done (uint32 flg);\r | |
233 | \r | |
234 | extern t_stat id_dboot (int32 u, DEVICE *dptr);\r | |
235 | \r | |
236 | /* DP data structures\r | |
237 | \r | |
238 | idc_dev DP device descriptor\r | |
239 | idc_unit DP unit list\r | |
240 | idc_reg DP register list\r | |
241 | idc_mod DP modifier list\r | |
242 | */\r | |
243 | \r | |
244 | DIB idc_dib = { d_IDC, 0, v_IDC, idc_tplte, &id, NULL };\r | |
245 | \r | |
246 | UNIT idc_unit[] = {\r | |
247 | { UDATA (&idc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+\r | |
248 | UNIT_ROABLE+(TYPE_MSM80 << UNIT_V_DTYPE), SIZE_MSM80) },\r | |
249 | { UDATA (&idc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+\r | |
250 | UNIT_ROABLE+(TYPE_MSM80 << UNIT_V_DTYPE), SIZE_MSM80) },\r | |
251 | { UDATA (&idc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+\r | |
252 | UNIT_ROABLE+(TYPE_MSM80 << UNIT_V_DTYPE), SIZE_MSM80) },\r | |
253 | { UDATA (&idc_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+\r | |
254 | UNIT_ROABLE+(TYPE_MSM80 << UNIT_V_DTYPE), SIZE_MSM80) }\r | |
255 | };\r | |
256 | \r | |
257 | REG idc_reg[] = {\r | |
258 | { HRDATA (STA, idc_sta, 8) },\r | |
259 | { HRDATA (BUF, idc_db, 8) },\r | |
260 | { HRDATA (SEC, idc_sec, 8) },\r | |
261 | { HRDATA (HCYL, idc_hcyl, 16) },\r | |
262 | { HRDATA (BUF, idd_db, 8) },\r | |
263 | { HRDATA (SVUN, idc_svun, 2), REG_HIDDEN },\r | |
264 | { BRDATA (DBUF, idcxb, 16, 8, IDC_NUMBY * 3) },\r | |
265 | { HRDATA (DBPTR, idc_bptr, 10), REG_RO },\r | |
266 | { FLDATA (FIRST, idc_1st, 0) },\r | |
267 | { HRDATA (CWDPTR, idc_wdptr, 2) },\r | |
268 | { HRDATA (DWDPTR, idc_wdptr, 1) },\r | |
269 | { GRDATA (IREQ, int_req[l_IDC], 16, ID_NUMDR + 1, i_IDC) },\r | |
270 | { GRDATA (IENB, int_enb[l_IDC], 16, ID_NUMDR + 1, i_IDC) },\r | |
271 | { GRDATA (SIREQ, idd_sirq, 16, ID_NUMDR, i_IDC + 1), REG_RO },\r | |
272 | { FLDATA (ICARM, idc_arm, 0) },\r | |
273 | { BRDATA (IDARM, idd_arm, 16, 1, ID_NUMDR) },\r | |
274 | { DRDATA (RTIME, idc_rtime, 24), PV_LEFT | REG_NZ },\r | |
275 | { DRDATA (STIME, idc_stime, 24), PV_LEFT | REG_NZ },\r | |
276 | { DRDATA (CTIME, idc_ctime, 24), PV_LEFT | REG_NZ },\r | |
277 | { BRDATA (CYL, idd_dcy, 16, 16, ID_NUMDR) },\r | |
278 | { URDATA (UCYL, idc_unit[0].CYL, 16, 12, 0,\r | |
279 | ID_NUMDR, REG_RO) },\r | |
280 | { URDATA (UHD, idc_unit[0].HD, 16, 5, 0,\r | |
281 | ID_NUMDR, REG_RO) },\r | |
282 | { URDATA (UFNC, idc_unit[0].FNC, 16, 10, 0,\r | |
283 | ID_NUMDR, REG_HRO) },\r | |
284 | { URDATA (UST, idc_unit[0].STD, 16, 8, 0,\r | |
285 | ID_NUMDR, REG_RO) },\r | |
286 | { URDATA (CAPAC, idc_unit[0].capac, 10, T_ADDR_W, 0,\r | |
287 | ID_NUMDR, PV_LEFT | REG_HRO) },\r | |
288 | { HRDATA (DEVNO, idc_dib.dno, 8), REG_HRO },\r | |
289 | { HRDATA (SELCH, idc_dib.sch, 2), REG_HRO },\r | |
290 | { BRDATA (TPLTE, idc_tplte, 16, 8, ID_NUMDR + 1), REG_HRO },\r | |
291 | { NULL }\r | |
292 | };\r | |
293 | \r | |
294 | MTAB idc_mod[] = {\r | |
295 | { UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },\r | |
296 | { UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },\r | |
297 | { (UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD16 << UNIT_V_DTYPE) + UNIT_ATT,\r | |
298 | "MCCDD16", NULL, NULL },\r | |
299 | { (UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD48 << UNIT_V_DTYPE) + UNIT_ATT,\r | |
300 | "MCCDD48", NULL, NULL },\r | |
301 | { (UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD80 << UNIT_V_DTYPE) + UNIT_ATT,\r | |
302 | "MCCDD80", NULL, NULL },\r | |
303 | { (UNIT_DTYPE+UNIT_ATT), (TYPE_MSM330F << UNIT_V_DTYPE) + UNIT_ATT,\r | |
304 | "MSM330F", NULL, NULL },\r | |
305 | { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD16 << UNIT_V_DTYPE),\r | |
306 | "MCCDD16", NULL, NULL },\r | |
307 | { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD48 << UNIT_V_DTYPE),\r | |
308 | "MCCDD48", NULL, NULL },\r | |
309 | { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MCCDD80 << UNIT_V_DTYPE),\r | |
310 | "MCCDD80", NULL, NULL },\r | |
311 | { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MSM330F << UNIT_V_DTYPE),\r | |
312 | "MSM330F", NULL, NULL },\r | |
313 | { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MCCDD16 << UNIT_V_DTYPE),\r | |
314 | NULL, "MCCDD16", &idc_set_size }, \r | |
315 | { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MCCDD48 << UNIT_V_DTYPE),\r | |
316 | NULL, "MCCDD48", &idc_set_size }, \r | |
317 | { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MCCDD80 << UNIT_V_DTYPE),\r | |
318 | NULL, "MCCDD80", &idc_set_size }, \r | |
319 | { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MSM330F << UNIT_V_DTYPE),\r | |
320 | NULL, "MSM330F", &idc_set_size },\r | |
321 | { (UNIT_DTYPE+UNIT_ATT), (TYPE_MSM80 << UNIT_V_DTYPE) + UNIT_ATT,\r | |
322 | "MSM80", NULL, NULL },\r | |
323 | { (UNIT_DTYPE+UNIT_ATT), (TYPE_MSM300 << UNIT_V_DTYPE) + UNIT_ATT,\r | |
324 | "MSM300", NULL, NULL },\r | |
325 | { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MSM80 << UNIT_V_DTYPE),\r | |
326 | "MSM80", NULL, NULL },\r | |
327 | { (UNIT_AUTO+UNIT_DTYPE+UNIT_ATT), (TYPE_MSM300 << UNIT_V_DTYPE),\r | |
328 | "MSM300", NULL, NULL },\r | |
329 | { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MSM80 << UNIT_V_DTYPE),\r | |
330 | NULL, "MSM80", &idc_set_size },\r | |
331 | { (UNIT_AUTO+UNIT_DTYPE), (TYPE_MSM300 << UNIT_V_DTYPE),\r | |
332 | NULL, "MSM300", &idc_set_size },\r | |
333 | { (UNIT_AUTO+UNIT_ATT), UNIT_AUTO, "autosize", NULL, NULL },\r | |
334 | { UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE", NULL },\r | |
335 | { MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO",\r | |
336 | &set_dev, &show_dev, NULL },\r | |
337 | { MTAB_XTD|MTAB_VDV, 0, "SELCH", "SELCH",\r | |
338 | &set_sch, &show_sch, NULL },\r | |
339 | { 0 }\r | |
340 | };\r | |
341 | \r | |
342 | DEVICE idc_dev = {\r | |
343 | "DM", idc_unit, idc_reg, idc_mod,\r | |
344 | ID_NUMDR, 16, 29, 1, 16, 8,\r | |
345 | NULL, NULL, &idc_reset,\r | |
346 | &id_dboot, &idc_attach, NULL,\r | |
347 | &idc_dib, DEV_DISABLE\r | |
348 | };\r | |
349 | \r | |
350 | /* Controller: IO routine */\r | |
351 | \r | |
352 | uint32 idc (uint32 dev, uint32 op, uint32 dat)\r | |
353 | {\r | |
354 | uint32 f, t;\r | |
355 | UNIT *uptr;\r | |
356 | \r | |
357 | switch (op) { /* case IO op */\r | |
358 | \r | |
359 | case IO_ADR: /* select */\r | |
360 | sch_adr (idc_dib.sch, dev); /* inform sel ch */\r | |
361 | return HW; /* halfwords */\r | |
362 | \r | |
363 | case IO_RD: /* read data */\r | |
364 | case IO_RH: /* read halfword */\r | |
365 | return 0; /* return data */\r | |
366 | \r | |
367 | case IO_WD: /* write data */\r | |
368 | idc_wd_byte (dat); /* one byte only */\r | |
369 | break;\r | |
370 | \r | |
371 | case IO_WH: /* write halfword */\r | |
372 | idc_wd_byte (dat >> 8); /* high byte */\r | |
373 | idc_wd_byte (dat); /* low byte */\r | |
374 | break;\r | |
375 | \r | |
376 | case IO_SS: /* status */\r | |
377 | t = idc_sta & STC_MASK; /* get status */\r | |
378 | if (t & SETC_EX) t = t | STA_EX; /* test for EX */\r | |
379 | return t;\r | |
380 | \r | |
381 | case IO_OC: /* command */\r | |
382 | idc_arm = int_chg (v_IDC, dat, idc_arm); /* upd int ctrl */\r | |
383 | idc_wdptr = 0; /* init ptr */\r | |
384 | f = dat & CMC_MASK; /* get cmd */\r | |
385 | uptr = idc_dev.units + idc_svun; /* get unit */\r | |
386 | if (f & CMC_CLR) { /* clear? */\r | |
387 | idc_reset (&idc_dev); /* reset world */\r | |
388 | break;\r | |
389 | }\r | |
390 | if ((f == 0) || /* if nop, */\r | |
391 | (f == CMC_EXP0) || /* expg, */\r | |
392 | !(idc_sta & STC_IDL) || /* !idle, */\r | |
393 | sim_is_active (uptr)) break; /* unit busy, ignore */\r | |
394 | idc_sta = STA_BSY; /* bsy=1,idl,err=0 */\r | |
395 | idc_1st = 1; /* xfr not started */\r | |
396 | idc_bptr = 0; /* buffer empty */\r | |
397 | uptr->FNC = f; /* save cmd */\r | |
398 | sim_activate (uptr, idc_rtime); /* schedule */\r | |
399 | idd_sirq = int_req[l_IDC] & IDC_DIRMASK; /* save drv ints */\r | |
400 | int_req[l_IDC] = int_req[l_IDC] & ~IDC_DIRMASK; /* clr drv ints */\r | |
401 | break;\r | |
402 | }\r | |
403 | \r | |
404 | return 0;\r | |
405 | }\r | |
406 | \r | |
407 | /* Process WD/WH data */\r | |
408 | \r | |
409 | void idc_wd_byte (uint32 dat)\r | |
410 | {\r | |
411 | dat = dat & 0xFF;\r | |
412 | switch (idc_wdptr) {\r | |
413 | \r | |
414 | case 0: /* byte 0 = sector */\r | |
415 | idc_sec = dat;\r | |
416 | idc_wdptr++;\r | |
417 | break;\r | |
418 | \r | |
419 | case 1: /* byte 1 = high hd/cyl */\r | |
420 | idc_hcyl = (idc_hcyl & 0xFF) | (dat << 8);\r | |
421 | idc_wdptr++;\r | |
422 | break;\r | |
423 | \r | |
424 | case 2: /* byte 2 = low hd/cyl */\r | |
425 | idc_hcyl = (idc_hcyl & 0xFF00) | dat;\r | |
426 | idc_wdptr = 0;\r | |
427 | break;\r | |
428 | }\r | |
429 | \r | |
430 | return;\r | |
431 | }\r | |
432 | \r | |
433 | /* Drives: IO routine */\r | |
434 | \r | |
435 | uint32 id (uint32 dev, uint32 op, uint32 dat)\r | |
436 | {\r | |
437 | uint32 t, u, f;\r | |
438 | UNIT *uptr;\r | |
439 | \r | |
440 | if (dev == idc_dib.dno) return idc (dev, op, dat); /* controller? */\r | |
441 | u = (dev - idc_dib.dno - o_ID0) / o_ID0; /* get unit num */\r | |
442 | uptr = idc_dev.units + u; /* get unit ptr */\r | |
443 | switch (op) { /* case IO op */\r | |
444 | \r | |
445 | case IO_ADR: /* select */\r | |
446 | if (idc_sta & STC_IDL) idc_svun = u; /* idle? save unit */\r | |
447 | return BY; /* byte only */\r | |
448 | \r | |
449 | case IO_RD: /* read data */\r | |
450 | case IO_RH:\r | |
451 | return 0;\r | |
452 | \r | |
453 | case IO_WD: /* write data */\r | |
454 | if (idd_wdptr & 1) /* low byte? */\r | |
455 | idd_db = (idd_db & 0xFF00) | dat;\r | |
456 | else idd_db = (idd_db & 0xFF) | (dat << 8); /* no, high */\r | |
457 | idd_wdptr = idd_wdptr ^ 1; /* other byte */\r | |
458 | break;\r | |
459 | \r | |
460 | case IO_SS: /* status */\r | |
461 | if (uptr->flags & UNIT_ATT) t =\r | |
462 | ((uptr->flags & UNIT_WPRT)? STD_WRP: 0) |\r | |
463 | (sim_is_active (uptr)? STD_NRDY: 0) |\r | |
464 | (uptr->STD & STD_UST);\r | |
465 | else t = STD_NRDY | STD_OFFL; /* off = X'09' */\r | |
466 | if (t & SETD_EX) t = t | STA_EX; /* test for ex */\r | |
467 | return t;\r | |
468 | \r | |
469 | case IO_OC: /* command */\r | |
470 | idd_arm[u] = int_chg (v_IDC + u + 1, dat, idd_arm[u]);\r | |
471 | idd_wdptr = 0; /* init ptr */\r | |
472 | if (idd_arm[u] == 0) /* disarmed? */\r | |
473 | idd_sirq &= ~(1 << (v_IDC + u + 1)); /* clr saved req */\r | |
474 | f = dat & CMC_MASK; /* get cmd */\r | |
475 | if ((f == 0) || /* if nop, */\r | |
476 | (f == CMDX_MASK) || /* 0x30, */\r | |
477 | !(idc_sta & STC_IDL) || /* !idle, */\r | |
478 | sim_is_active (uptr)) break; /* unit busy, ignore */\r | |
479 | uptr->FNC = f | CMC_DRV; /* save cmd */\r | |
480 | idc_sta = idc_sta & ~STC_IDL; /* clr idle */\r | |
481 | sim_activate (uptr, idc_ctime); /* schedule */\r | |
482 | break;\r | |
483 | }\r | |
484 | \r | |
485 | return 0;\r | |
486 | }\r | |
487 | \r | |
488 | /* Unit service\r | |
489 | \r | |
490 | If drive command, process; if an interrupt is needed (positioning\r | |
491 | command), schedule second part\r | |
492 | \r | |
493 | If data transfer command, process; must use selector channel\r | |
494 | */\r | |
495 | \r | |
496 | t_stat idc_svc (UNIT *uptr)\r | |
497 | {\r | |
498 | int32 diff;\r | |
499 | uint32 f, u = uptr - idc_dev.units; /* get unit number */\r | |
500 | uint32 dtype = GET_DTYPE (uptr->flags); /* get drive type */\r | |
501 | uint32 t;\r | |
502 | t_stat r;\r | |
503 | \r | |
504 | if (uptr->FNC & CMC_DRV) { /* drive cmd? */\r | |
505 | f = uptr->FNC & CMC_MASK; /* get cmd */\r | |
506 | if (uptr->FNC & CMC_DRV1) { /* part 2? */\r | |
507 | if (idd_arm[u]) { /* drv int armed? */\r | |
508 | if (idc_sta & STC_IDL) /* ctrl idle? */\r | |
509 | SET_INT (v_IDC + u + 1); /* req intr */\r | |
510 | else idd_sirq |= (1 << (v_IDC + u + 1)); /* def intr */\r | |
511 | }\r | |
512 | if ((uptr->flags & UNIT_ATT) == 0) return SCPE_OK;\r | |
513 | if (((f & CMDX_MASK) == 0) && /* seek? */\r | |
514 | (f & (CMD_SK | CMD_RST))) {\r | |
515 | if (idd_dcy[u] >= drv_tab[dtype].cyl) /* bad cylinder? */\r | |
516 | uptr->STD = uptr->STD | STD_SKI; /* error */\r | |
517 | uptr->CYL = idd_dcy[u]; /* put on cyl */\r | |
518 | }\r | |
519 | } /* end if p2 */\r | |
520 | else { /* part 1 */\r | |
521 | idc_sta = idc_sta | STC_IDL; /* set idle */\r | |
522 | uptr->FNC = uptr->FNC | CMC_DRV1; /* set part 2 */\r | |
523 | if (f >= CMDX_MASK) { /* extended? */\r | |
524 | if (f & CMDX_CLF) /* clr fault? */\r | |
525 | uptr->STD = uptr->STD & ~STD_UNS; /* clr unsafe */\r | |
526 | if (f & (CMDX_RLS | CMDX_SVP | CMDX_SVM)) /* intr expected? */\r | |
527 | sim_activate (uptr, idc_ctime);\r | |
528 | }\r | |
529 | else if (f >= CMDF_SCY) { /* tag? */\r | |
530 | if (f & CMDF_SHD) uptr->HD = idd_db & HD_MASK;\r | |
531 | else if (f & CMDF_SCY) {\r | |
532 | if (idd_db >= drv_tab[dtype].cyl) /* bad cylinder? */\r | |
533 | uptr->STD = uptr->STD | STD_SKI; /* set seek inc */\r | |
534 | idd_dcy[u] = idd_db & CY_MASK;\r | |
535 | }\r | |
536 | }\r | |
537 | else if (f & (CMD_SK | CMD_RST)) { /* seek? */\r | |
538 | if (f == CMD_RST) idd_dcy[u] = 0; /* restore? */\r | |
539 | if (idd_dcy[u] >= drv_tab[dtype].cyl) { /* bad cylinder? */\r | |
540 | uptr->STD = uptr->STD | STD_SKI; /* set seek inc */\r | |
541 | idd_dcy[u] = uptr->CYL; /* no motion */\r | |
542 | sim_activate (uptr, 0); /* finish asap */\r | |
543 | }\r | |
544 | else { /* cylinder ok */\r | |
545 | uptr->STD = uptr->STD & ~STD_SKI; /* clr seek inc */\r | |
546 | diff = idd_dcy[u] - uptr->CYL;\r | |
547 | if (diff < 0) diff = -diff; /* ABS cyl diff */\r | |
548 | else if (diff == 0) diff = 1; /* must be nz */\r | |
549 | sim_activate (uptr, diff * idc_stime);\r | |
550 | }\r | |
551 | }\r | |
552 | } /* end else p1 */\r | |
553 | return SCPE_OK; /* end if drv */\r | |
554 | }\r | |
555 | \r | |
556 | switch (uptr->FNC & CMC_MASK) { /* case on func */\r | |
557 | \r | |
558 | case CMC_RCHK: /* read check */\r | |
559 | idc_dter (uptr, 1); /* check xfr err */\r | |
560 | break;\r | |
561 | \r | |
562 | #if defined (ID_IDC)\r | |
563 | case CMC_RUNC: /* read uncorr */\r | |
564 | #endif\r | |
565 | case CMC_RD: /* read */\r | |
566 | if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* sch transfer? */\r | |
567 | if (idc_dter (uptr, idc_1st)) return SCPE_OK; /* dte? done */\r | |
568 | if (r = idc_rds (uptr)) return r; /* read sec, err? */\r | |
569 | idc_1st = 0;\r | |
570 | t = sch_wrmem (idc_dib.sch, idcxb, IDC_NUMBY); /* write mem */\r | |
571 | if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* more to do? */ \r | |
572 | sim_activate (uptr, idc_rtime); /* reschedule */\r | |
573 | return SCPE_OK;\r | |
574 | }\r | |
575 | break; /* no, set done */\r | |
576 | }\r | |
577 | idc_sta = idc_sta | STC_DTE; /* cant work */\r | |
578 | break;\r | |
579 | \r | |
580 | case CMC_WR: /* write */\r | |
581 | if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* sch transfer? */\r | |
582 | if (idc_dter (uptr, idc_1st)) return SCPE_OK; /* dte? done */\r | |
583 | idc_bptr = sch_rdmem (idc_dib.sch, idcxb, IDC_NUMBY); /* read mem */\r | |
584 | idc_db = idcxb[idc_bptr - 1]; /* last byte */\r | |
585 | if (r = idc_wds (uptr)) return r; /* write sec, err? */\r | |
586 | idc_1st = 0;\r | |
587 | if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* more to do? */ \r | |
588 | sim_activate (uptr, idc_rtime); /* reschedule */\r | |
589 | return SCPE_OK;\r | |
590 | }\r | |
591 | break; /* no, set done */\r | |
592 | }\r | |
593 | idc_sta = idc_sta | STC_DTE; /* cant work */\r | |
594 | break;\r | |
595 | \r | |
596 | case CMC_FCHK: case CMC_RFMT: case CMC_WFMT: case CMC_WFTK:\r | |
597 | idc_dter (uptr, 1);\r | |
598 | idc_sta = idc_sta | STC_WRP;\r | |
599 | break;\r | |
600 | \r | |
601 | #if defined (ID_IDC)\r | |
602 | case CMC_RRAM: /* read RAM */\r | |
603 | if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* sch transfer? */\r | |
604 | sch_wrmem (idc_dib.sch, idcxb, IDC_NUMBY * 3);\r | |
605 | if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* more to do? */ \r | |
606 | sim_activate (uptr, idc_rtime); /* reschedule */\r | |
607 | return SCPE_OK;\r | |
608 | }\r | |
609 | break; /* no, set done */\r | |
610 | }\r | |
611 | idc_sta = idc_sta | STC_DTE; /* cant work */\r | |
612 | break;\r | |
613 | \r | |
614 | case CMC_WRAM: /* write RAM */\r | |
615 | if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* sch transfer? */\r | |
616 | sch_rdmem (idc_dib.sch, idcxb, IDC_NUMBY * 3); /* read from mem */\r | |
617 | if (sch_actv (idc_dib.sch, idc_dib.dno)) { /* more to do? */ \r | |
618 | sim_activate (uptr, idc_rtime); /* reschedule */\r | |
619 | return SCPE_OK;\r | |
620 | }\r | |
621 | break; /* no, set done */\r | |
622 | }\r | |
623 | idc_sta = idc_sta | STC_DTE; /* cant work */\r | |
624 | break;\r | |
625 | \r | |
626 | case CMC_STST: case CMC_LAMP: /* tests */\r | |
627 | break;\r | |
628 | #endif\r | |
629 | \r | |
630 | default:\r | |
631 | idc_sta = idc_sta | STC_DTE;\r | |
632 | break;\r | |
633 | }\r | |
634 | \r | |
635 | idc_done (0); /* done */\r | |
636 | return SCPE_OK;\r | |
637 | }\r | |
638 | \r | |
639 | /* Read data sector */\r | |
640 | \r | |
641 | t_stat idc_rds (UNIT *uptr)\r | |
642 | {\r | |
643 | uint32 i;\r | |
644 | \r | |
645 | i = fxread (idcxb, sizeof (uint8), IDC_NUMBY, uptr->fileref);\r | |
646 | if (ferror (uptr->fileref)) { /* error? */\r | |
647 | perror ("IDC I/O error");\r | |
648 | clearerr (uptr->fileref);\r | |
649 | idc_done (STC_DTE);\r | |
650 | return SCPE_IOERR;\r | |
651 | }\r | |
652 | for ( ; i < IDC_NUMBY; i++) idcxb[i] = 0; /* fill with 0's */\r | |
653 | return SCPE_OK;\r | |
654 | }\r | |
655 | \r | |
656 | /* Write data sector */\r | |
657 | \r | |
658 | t_bool idc_wds (UNIT *uptr)\r | |
659 | {\r | |
660 | for ( ; idc_bptr < IDC_NUMBY; idc_bptr++)\r | |
661 | idcxb[idc_bptr] = idc_db; /* fill with last */\r | |
662 | fxwrite (idcxb, sizeof (uint8), IDC_NUMBY, uptr->fileref);\r | |
663 | if (ferror (uptr->fileref)) { /* error? */\r | |
664 | perror ("IDC I/O error");\r | |
665 | clearerr (uptr->fileref);\r | |
666 | idc_done (STC_DTE);\r | |
667 | return SCPE_IOERR;\r | |
668 | }\r | |
669 | return FALSE;\r | |
670 | }\r | |
671 | \r | |
672 | /* Data transfer error test routine */\r | |
673 | \r | |
674 | t_bool idc_dter (UNIT *uptr, uint32 first)\r | |
675 | {\r | |
676 | uint32 cy;\r | |
677 | uint32 hd, sc, sa;\r | |
678 | uint32 dtype = GET_DTYPE (uptr->flags); /* get drive type */\r | |
679 | \r | |
680 | if ((uptr->flags & UNIT_ATT) == 0) { /* not attached? */\r | |
681 | idc_done (STC_DTE); /* error, done */\r | |
682 | return TRUE;\r | |
683 | }\r | |
684 | if ((uptr->flags & UNIT_WPRT) && (uptr->FNC == CMC_WR)) {\r | |
685 | idc_done (STC_WRP); /* error, done */\r | |
686 | return TRUE;\r | |
687 | }\r | |
688 | cy = uptr->CYL; /* get cylinder */\r | |
689 | hd = uptr->HD; /* get head */\r | |
690 | sc = idc_sec & SC_MASK; /* get sector */\r | |
691 | if (cy >= drv_tab[dtype].cyl) { /* bad cylinder? */\r | |
692 | uptr->STD = uptr->STD | STD_SKI; /* error */\r | |
693 | idc_done (STC_DTE); /* error, done */\r | |
694 | return TRUE;\r | |
695 | }\r | |
696 | if (hd >= drv_tab[dtype].surf) { /* bad head? */\r | |
697 | if (first) { /* 1st xfer? */\r | |
698 | uptr->STD = uptr->STD | STD_UNS; /* drive unsafe */\r | |
699 | idc_done (STC_ACF);\r | |
700 | }\r | |
701 | else idc_done (STC_CYO); /* no, cyl ovf */\r | |
702 | return TRUE;\r | |
703 | }\r | |
704 | sa = GET_SA (cy, hd, sc, dtype); /* curr disk addr */\r | |
705 | fseek (uptr->fileref, sa * IDC_NUMBY, SEEK_SET); /* seek to pos */\r | |
706 | idc_sec = (idc_sec + 1) & SC_MASK; /* incr disk addr */\r | |
707 | if (idc_sec == 0) uptr->HD = uptr->HD + 1;\r | |
708 | return FALSE;\r | |
709 | }\r | |
710 | \r | |
711 | /* Data transfer done routine */\r | |
712 | \r | |
713 | void idc_done (uint32 flg)\r | |
714 | {\r | |
715 | idc_sta = (idc_sta | STC_IDL | flg) & ~STA_BSY; /* set flag, idle */\r | |
716 | if (idc_arm) SET_INT (v_IDC); /* if armed, intr */\r | |
717 | int_req[l_IDC] = int_req[l_IDC] | idd_sirq; /* restore drv ints */\r | |
718 | idd_sirq = 0; /* clear saved */\r | |
719 | if (flg) sch_stop (idc_dib.sch); /* if err, stop sch */\r | |
720 | return;\r | |
721 | }\r | |
722 | \r | |
723 | /* Reset routine */\r | |
724 | \r | |
725 | t_stat idc_reset (DEVICE *dptr)\r | |
726 | {\r | |
727 | uint32 u;\r | |
728 | UNIT *uptr;\r | |
729 | \r | |
730 | idc_sta = STC_IDL | STA_BSY; /* idle, busy */\r | |
731 | idc_wdptr = 0;\r | |
732 | idd_wdptr = 0;\r | |
733 | idc_1st = 0; /* clear flag */\r | |
734 | idc_svun = idc_db = 0; /* clear unit, buf */\r | |
735 | idc_sec = 0; /* clear addr */\r | |
736 | idc_hcyl = 0;\r | |
737 | CLR_INT (v_IDC); /* clear ctrl int */\r | |
738 | CLR_ENB (v_IDC); /* clear ctrl enb */\r | |
739 | idc_arm = 0; /* clear ctrl arm */\r | |
740 | idd_sirq = 0;\r | |
741 | for (u = 0; u < ID_NUMDR; u++) { /* loop thru units */\r | |
742 | uptr = idc_dev.units + u;\r | |
743 | uptr->CYL = uptr->STD = 0;\r | |
744 | uptr->HD = uptr->FNC = 0;\r | |
745 | idd_dcy[u] = 0;\r | |
746 | CLR_INT (v_IDC + u + 1); /* clear intr */\r | |
747 | CLR_ENB (v_IDC + u + 1); /* clear enable */\r | |
748 | idd_arm[u] = 0; /* clear arm */\r | |
749 | sim_cancel (uptr); /* cancel activity */\r | |
750 | }\r | |
751 | return SCPE_OK;\r | |
752 | }\r | |
753 | \r | |
754 | /* Attach routine (with optional autosizing) */\r | |
755 | \r | |
756 | t_stat idc_attach (UNIT *uptr, char *cptr)\r | |
757 | {\r | |
758 | uint32 i, p;\r | |
759 | t_stat r;\r | |
760 | \r | |
761 | uptr->capac = drv_tab[GET_DTYPE (uptr->flags)].size;\r | |
762 | r = attach_unit (uptr, cptr); /* attach unit */\r | |
763 | if (r != SCPE_OK) return r; /* error? */\r | |
764 | uptr->CYL = 0;\r | |
765 | if ((uptr->flags & UNIT_AUTO) == 0) return SCPE_OK; /* autosize? */\r | |
766 | if ((p = ftell (uptr->fileref)) == 0) return SCPE_OK;\r | |
767 | for (i = 0; drv_tab[i].surf != 0; i++) {\r | |
768 | if (p <= drv_tab[i].size) {\r | |
769 | uptr->flags = (uptr->flags & ~UNIT_DTYPE) | (i << UNIT_V_DTYPE);\r | |
770 | uptr->capac = drv_tab[i].size;\r | |
771 | return SCPE_OK;\r | |
772 | }\r | |
773 | }\r | |
774 | return SCPE_OK;\r | |
775 | }\r | |
776 | \r | |
777 | /* Set size command validation routine */\r | |
778 | \r | |
779 | t_stat idc_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)\r | |
780 | {\r | |
781 | if (uptr->flags & UNIT_ATT) return SCPE_ALATT;\r | |
782 | uptr->capac = drv_tab[GET_DTYPE (val)].size;\r | |
783 | return SCPE_OK;\r | |
784 | }\r |