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1 | /* pdp11_xq.h: DEQNA/DELQA ethernet controller information\r |
2 | ------------------------------------------------------------------------------\r | |
3 | \r | |
4 | Copyright (c) 2002-2005, David T. Hittner\r | |
5 | \r | |
6 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
7 | copy of this software and associated documentation files (the "Software"),\r | |
8 | to deal in the Software without restriction, including without limitation\r | |
9 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
10 | and/or sell copies of the Software, and to permit persons to whom the\r | |
11 | Software is furnished to do so, subject to the following conditions:\r | |
12 | \r | |
13 | The above copyright notice and this permission notice shall be included in\r | |
14 | all copies or substantial portions of the Software.\r | |
15 | \r | |
16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
19 | THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
20 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
21 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
22 | \r | |
23 | Except as contained in this notice, the name of the author shall not be\r | |
24 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
25 | in this Software without prior written authorization from the author.\r | |
26 | \r | |
27 | ------------------------------------------------------------------------------\r | |
28 | \r | |
29 | Modification history:\r | |
30 | \r | |
31 | 07-Jul-05 RMS Removed extraneous externs\r | |
32 | 20-Jan-04 DTH Added new sanity timer and system id timer\r | |
33 | 19-Jan-04 DTH Added XQ_SERVICE_INTERVAL, poll\r | |
34 | 09-Jan-04 DTH Added Boot PDP diagnostic definition, XI/RI combination\r | |
35 | 26-Dec-03 DTH Moved ethernet queue definitions to sim_ether\r | |
36 | 25-Nov-03 DTH Added interrupt request flag\r | |
37 | 02-Jun-03 DTH Added struct xq_stats\r | |
38 | 28-May-03 DTH Made xq_msg_que.item dynamic\r | |
39 | 28-May-03 MP Optimized structures, removed rtime variable\r | |
40 | 06-May-03 DTH Changed 32-bit t_addr to uint32 for v3.0\r | |
41 | 28-Apr-03 DTH Added callbacks for multicontroller identification\r | |
42 | 25-Mar-03 DTH Removed bootrom field - no longer needed; Updated copyright\r | |
43 | 15-Jan-03 DTH Merged Mark Pizzolato's changes into main source\r | |
44 | 13-Jan-03 MP Added countdown for System Id multicast packets\r | |
45 | 10-Jan-03 DTH Added bootrom field\r | |
46 | 30-Dec-02 DTH Added setup valid field\r | |
47 | 21-Oct-02 DTH Corrected copyright again\r | |
48 | 15-Oct-02 DTH Fixed copyright, added sanity timer support\r | |
49 | 10-Oct-02 DTH Added more setup fields and bitmasks\r | |
50 | 08-Oct-02 DTH Integrated with 2.10-0p4, added variable vector and copyrights\r | |
51 | 03-Oct-02 DTH Beta version of xq/sim_ether released for SIMH 2.09-11\r | |
52 | 15-Aug-02 DTH Started XQ simulation\r | |
53 | \r | |
54 | ------------------------------------------------------------------------------\r | |
55 | */\r | |
56 | \r | |
57 | #ifndef _PDP11_XQ_H\r | |
58 | #define _PDP11_XQ_H\r | |
59 | \r | |
60 | #if defined (VM_PDP10) /* PDP10 version */\r | |
61 | #error "DEQNA/DELQA not supported on PDP10!"\r | |
62 | \r | |
63 | #elif defined (VM_VAX) /* VAX version */\r | |
64 | #include "vax_defs.h"\r | |
65 | #define XQ_RDX 16\r | |
66 | #define XQ_WID 32\r | |
67 | extern int32 PSL; /* PSL */\r | |
68 | extern int32 fault_PC; /* fault PC */\r | |
69 | extern int32 int_req[IPL_HLVL];\r | |
70 | \r | |
71 | #else /* PDP-11 version */\r | |
72 | #include "pdp11_defs.h"\r | |
73 | #define XQ_RDX 8\r | |
74 | #define XQ_WID 16\r | |
75 | extern int32 int_req[IPL_HLVL];\r | |
76 | #endif\r | |
77 | \r | |
78 | #include "sim_ether.h"\r | |
79 | \r | |
80 | #define XQ_QUE_MAX 500 /* read queue size in packets */\r | |
81 | #define XQ_FILTER_MAX 14 /* number of filters allowed */\r | |
82 | #define XQ_SERVICE_INTERVAL 100 /* polling interval - X per second */\r | |
83 | #define XQ_SYSTEM_ID_SECS 540 /* seconds before system ID timer expires */\r | |
84 | #define XQ_HW_SANITY_SECS 240 /* seconds before HW sanity timer expires */\r | |
85 | #define XQ_MAX_CONTROLLERS 2 /* maximum controllers allowed */\r | |
86 | \r | |
87 | enum xq_type {XQ_T_DEQNA, XQ_T_DELQA};\r | |
88 | \r | |
89 | struct xq_sanity {\r | |
90 | int enabled; /* sanity timer enabled? 2=HW, 1=SW, 0=off */\r | |
91 | int quarter_secs; /* sanity timer value in 1/4 seconds */\r | |
92 | int max; /* maximum timeout (based on poll) */\r | |
93 | int timer; /* countdown timer */\r | |
94 | };\r | |
95 | \r | |
96 | struct xq_setup {\r | |
97 | int valid; /* is the setup block valid? */\r | |
98 | int promiscuous; /* promiscuous mode enabled */\r | |
99 | int multicast; /* enable all multicast addresses */\r | |
100 | int l1; /* first diagnostic led state */\r | |
101 | int l2; /* second diagnostic led state */\r | |
102 | int l3; /* third diagnostic led state */\r | |
103 | int sanity_timer; /* sanity timer value (encoded) */\r | |
104 | ETH_MAC macs[XQ_FILTER_MAX]; /* MAC addresses to respond to */\r | |
105 | };\r | |
106 | \r | |
107 | struct xq_stats {\r | |
108 | int recv; /* received packets */\r | |
109 | int filter; /* filtered packets */\r | |
110 | int xmit; /* transmitted packets */\r | |
111 | int fail; /* transmit failed */\r | |
112 | int runt; /* runts */\r | |
113 | int giant; /* oversize packets */\r | |
114 | int setup; /* setup packets */\r | |
115 | int loop; /* loopback packets */\r | |
116 | };\r | |
117 | \r | |
118 | struct xq_meb { /* MEB block */\r | |
119 | uint8 type;\r | |
120 | uint8 add_lo;\r | |
121 | uint8 add_mi;\r | |
122 | uint8 add_hi;\r | |
123 | uint8 siz_lo;\r | |
124 | uint8 siz_hi;\r | |
125 | };\r | |
126 | \r | |
127 | struct xq_device {\r | |
128 | /*+ initialized values - DO NOT MOVE */\r | |
129 | ETH_PCALLBACK rcallback; /* read callback routine */\r | |
130 | ETH_PCALLBACK wcallback; /* write callback routine */\r | |
131 | ETH_MAC mac; /* MAC address */\r | |
132 | enum xq_type type; /* controller type */\r | |
133 | int poll; /* poll ethernet times/sec */\r | |
134 | struct xq_sanity sanity; /* sanity timer information */\r | |
135 | /*- initialized values - DO NOT MOVE */\r | |
136 | \r | |
137 | /* I/O register storage */\r | |
138 | uint16 addr[6];\r | |
139 | uint16 rbdl[2];\r | |
140 | uint16 xbdl[2];\r | |
141 | uint16 var;\r | |
142 | uint16 csr;\r | |
143 | uint32 irq; /* interrupt request flag */\r | |
144 | \r | |
145 | /* buffers, etc. */\r | |
146 | struct xq_setup setup;\r | |
147 | struct xq_stats stats;\r | |
148 | uint8 mac_checksum[2];\r | |
149 | uint16 rbdl_buf[6];\r | |
150 | uint16 xbdl_buf[6];\r | |
151 | uint32 rbdl_ba;\r | |
152 | uint32 xbdl_ba;\r | |
153 | ETH_DEV* etherface;\r | |
154 | int receiving;\r | |
155 | ETH_PACK read_buffer;\r | |
156 | ETH_PACK write_buffer;\r | |
157 | ETH_QUE ReadQ;\r | |
158 | int idtmr; /* countdown for ID Timer */\r | |
159 | };\r | |
160 | \r | |
161 | struct xq_controller {\r | |
162 | DEVICE* dev; /* device block */\r | |
163 | UNIT* unit; /* unit block */\r | |
164 | DIB* dib; /* device interface block */\r | |
165 | struct xq_device* var; /* controller-specific variables */\r | |
166 | };\r | |
167 | \r | |
168 | typedef struct xq_controller CTLR;\r | |
169 | \r | |
170 | \r | |
171 | #define XQ_CSR_RI 0x8000 /* Receive Interrupt Request (RI) [RO/W1] */\r | |
172 | #define XQ_CSR_PE 0x4000 /* Parity Error in Host Memory (PE) [RO] */\r | |
173 | #define XQ_CSR_CA 0x2000 /* Carrier from Receiver Enabled (CA) [RO] */\r | |
174 | #define XQ_CSR_OK 0x1000 /* Ethernet Transceiver Power (OK) [RO] */\r | |
175 | #define XQ_CSR_RR 0x0800 /* Reserved : Set to Zero (RR) [RO] */\r | |
176 | #define XQ_CSR_SE 0x0400 /* Sanity Timer Enable (SE) [RW] */\r | |
177 | #define XQ_CSR_EL 0x0200 /* External Loopback (EL) [RW] */\r | |
178 | #define XQ_CSR_IL 0x0100 /* Internal Loopback (IL) [RW] */\r | |
179 | #define XQ_CSR_XI 0x0080 /* Transmit Interrupt Request (XI) [RO/W1] */\r | |
180 | #define XQ_CSR_IE 0x0040 /* Interrupt Enable (IE) [RW] */\r | |
181 | #define XQ_CSR_RL 0x0020 /* Receive List Invalid/Empty (RL) [RO] */\r | |
182 | #define XQ_CSR_XL 0x0010 /* Transmit List Invalid/Empty (XL) [RO] */\r | |
183 | #define XQ_CSR_BD 0x0008 /* Boot/Diagnostic ROM Load (BD) [RW] */\r | |
184 | #define XQ_CSR_NI 0x0004 /* NonExistant Memory Timeout (NXM) [RO] */\r | |
185 | #define XQ_CSR_SR 0x0002 /* Software Reset (SR) [RW] */\r | |
186 | #define XQ_CSR_RE 0x0001 /* Receiver Enable (RE) [RW] */\r | |
187 | \r | |
188 | /* special access bitmaps */\r | |
189 | #define XQ_CSR_RO 0xF8B4 /* Read-Only bits */\r | |
190 | #define XQ_CSR_RW 0x074B /* Read/Write bits */\r | |
191 | #define XQ_CSR_W1 0x8080 /* Write-one-to-clear bits */\r | |
192 | #define XQ_CSR_BP 0x0208 /* Boot PDP diagnostic ROM */\r | |
193 | #define XQ_CSR_XIRI 0X8080 /* Transmit & Receive Interrupts */\r | |
194 | \r | |
195 | #define XQ_VEC_MS 0x8000 /* Mode Select (MO) [RW] */\r | |
196 | #define XQ_VEC_OS 0x4000 /* Option Switch Setting (OS) [RO] */\r | |
197 | #define XQ_VEC_RS 0x2000 /* Request Self-Test (RS) [RW] */\r | |
198 | #define XQ_VEC_S3 0x1000 /* Self-Test Status (S3) [RO] */\r | |
199 | #define XQ_VEC_S2 0x0800 /* Self-Test Status (S2) [RO] */\r | |
200 | #define XQ_VEC_S1 0x0400 /* Self-Test Status (S1) [RO] */\r | |
201 | #define XQ_VEC_ST 0x1C00 /* Self-Test (S1 + S2 + S3) [RO] */\r | |
202 | #define XQ_VEC_IV 0x03FC /* Interrupt Vector (IV) [RW] */\r | |
203 | #define XQ_VEC_RR 0x0002 /* Reserved (RR) [RO] */\r | |
204 | #define XQ_VEC_ID 0x0001 /* Identity Test Bit (ID) [RW] */\r | |
205 | \r | |
206 | /* special access bitmaps */\r | |
207 | #define XQ_VEC_RO 0x5C02 /* Read-Only bits */\r | |
208 | #define XQ_VEC_RW 0xA3FD /* Read/Write bits */\r | |
209 | \r | |
210 | #define XQ_DSC_V 0x8000 /* Valid bit */\r | |
211 | #define XQ_DSC_C 0x4000 /* Chain bit */\r | |
212 | #define XQ_DSC_E 0x2000 /* End of Message bit [Transmit only] */\r | |
213 | #define XQ_DSC_S 0x1000 /* Setup bit [Transmit only] */\r | |
214 | #define XQ_DSC_L 0x0080 /* Low Byte Termination bit [Transmit only] */\r | |
215 | #define XQ_DSC_H 0x0040 /* High Byte Start bit [Transmit only] */\r | |
216 | \r | |
217 | #define XQ_SETUP_MC 0x0001 /* multicast bit */\r | |
218 | #define XQ_SETUP_PM 0x0002 /* promiscuous bit */\r | |
219 | #define XQ_SETUP_LD 0x000C /* led bits */\r | |
220 | #define XQ_SETUP_ST 0x0070 /* sanity timer bits */\r | |
221 | \r | |
222 | /* debugging bitmaps */\r | |
223 | #define DBG_TRC 0x0001 /* trace routine calls */\r | |
224 | #define DBG_REG 0x0002 /* trace read/write registers */\r | |
225 | #define DBG_CSR 0x0004 /* watch CSR */\r | |
226 | #define DBG_VAR 0x0008 /* watch VAR */\r | |
227 | #define DBG_WRN 0x0010 /* display warnings */\r | |
228 | #define DBG_SAN 0x0020 /* display sanity timer info */\r | |
229 | #define DBG_SET 0x0040 /* display setup info */\r | |
230 | #define DBG_PCK 0x0080 /* display packets */\r | |
231 | #define DBG_ETH 0x8000 /* debug ethernet device */\r | |
232 | \r | |
233 | #endif /* _PDP11_XQ_H */\r |