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1 | /* pdp18b_defs.h: 18b PDP simulator definitions\r |
2 | \r | |
3 | Copyright (c) 1993-2006, Robert M Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | 30-Oct-06 RMS Added infinite loop stop\r | |
27 | 14-Jan-04 RMS Revised IO device call interface\r | |
28 | 18-Oct-03 RMS Added DECtape off reel message\r | |
29 | 18-Jul-03 RMS Added FP15 support\r | |
30 | Added XVM support\r | |
31 | Added EAE option for PDP-4\r | |
32 | 25-Apr-03 RMS Revised for extended file support\r | |
33 | 04-Feb-03 RMS Added RB09, LP09 support\r | |
34 | 22-Nov-02 RMS Added PDP-4 drum support\r | |
35 | 05-Oct-02 RMS Added DIB structure\r | |
36 | 25-Jul-02 RMS Added PDP-4 DECtape support\r | |
37 | 10-Feb-02 RMS Added PDP-7 DECtape support\r | |
38 | 25-Nov-01 RMS Revised interrupt structure\r | |
39 | 27-May-01 RMS Added second Teletype support\r | |
40 | 21-Jan-01 RMS Added DECtape support\r | |
41 | 14-Apr-99 RMS Changed t_addr to unsigned\r | |
42 | 02-Jan-96 RMS Added fixed head and moving head disks\r | |
43 | 31-Dec-95 RMS Added memory management\r | |
44 | 19-Mar-95 RMS Added dynamic memory size\r | |
45 | \r | |
46 | The author gratefully acknowledges the help of Craig St. Clair and\r | |
47 | Deb Tevonian in locating archival material about the 18b PDP's, and of\r | |
48 | Al Kossow and Max Burnet in making documentation and software available.\r | |
49 | */\r | |
50 | \r | |
51 | #ifndef _PDP18B_DEFS_H_\r | |
52 | #define _PDP18B_DEFS_H_ 0\r | |
53 | \r | |
54 | #include "sim_defs.h" /* simulator defns */\r | |
55 | \r | |
56 | /* Models: only one should be defined\r | |
57 | \r | |
58 | model memory CPU options I/O options\r | |
59 | \r | |
60 | PDP4 8K Type 18 EAE Type 65 KSR-28 Teletype (Baudot)\r | |
61 | ??Type 16 mem extension integral paper tape reader\r | |
62 | Type 75 paper tape punch\r | |
63 | integral real time clock\r | |
64 | Type 62 line printer (Hollerith)\r | |
65 | Type 550/555 DECtape\r | |
66 | Type 24 serial drum\r | |
67 | \r | |
68 | PDP7 32K Type 177 EAE Type 649 KSR-33 Teletype\r | |
69 | Type 148 mem extension Type 444 paper tape reader\r | |
70 | Type 75 paper tape punch\r | |
71 | integral real time clock\r | |
72 | Type 647B line printer (sixbit)\r | |
73 | Type 550/555 DECtape\r | |
74 | Type 24 serial drum\r | |
75 | \r | |
76 | PDP9 32K KE09A EAE KSR-33 Teletype\r | |
77 | KF09A auto pri intr PC09A paper tape reader and punch\r | |
78 | KG09B mem extension integral real time clock\r | |
79 | KP09A power detection Type 647D/E line printer (sixbit)\r | |
80 | KX09A mem protection LP09 line printer (ASCII)\r | |
81 | RF09/RS09 fixed head disk\r | |
82 | RB09 fixed head disk\r | |
83 | TC59 magnetic tape\r | |
84 | TC02/TU55 DECtape\r | |
85 | LT09A additional Teletypes\r | |
86 | \r | |
87 | PDP15 128K KE15 EAE KSR-35 Teletype\r | |
88 | KA15 auto pri intr PC15 paper tape reader and punch\r | |
89 | KF15 power detection KW15 real time clock\r | |
90 | KM15 mem protection LP09 line printer\r | |
91 | KT15 mem relocation LP15 line printer\r | |
92 | FP15 floating point RP15 disk pack\r | |
93 | XVM option RF15/RF09 fixed head disk\r | |
94 | TC59D magnetic tape\r | |
95 | TC15/TU56 DECtape\r | |
96 | LT15/LT19 additional Teletypes\r | |
97 | \r | |
98 | ??Indicates not implemented. The PDP-4 manual refers to a memory\r | |
99 | ??extension control; there is no documentation on it.\r | |
100 | */\r | |
101 | \r | |
102 | #if !defined (PDP4) && !defined (PDP7) && !defined (PDP9) && !defined (PDP15)\r | |
103 | #define PDP15 0 /* default to PDP-15 */\r | |
104 | #endif\r | |
105 | \r | |
106 | /* Simulator stop codes */\r | |
107 | \r | |
108 | #define STOP_RSRV 1 /* must be 1 */\r | |
109 | #define STOP_HALT 2 /* HALT */\r | |
110 | #define STOP_IBKPT 3 /* breakpoint */\r | |
111 | #define STOP_XCT 4 /* nested XCT's */\r | |
112 | #define STOP_API 5 /* invalid API int */\r | |
113 | #define STOP_NONSTD 6 /* non-std dev num */\r | |
114 | #define STOP_MME 7 /* mem mgt error */\r | |
115 | #define STOP_FPDIS 8 /* fp inst, fpp disabled */\r | |
116 | #define STOP_DTOFF 9 /* DECtape off reel */\r | |
117 | #define STOP_LOOP 10 /* infinite loop */\r | |
118 | \r | |
119 | /* Peripheral configuration */\r | |
120 | \r | |
121 | #if defined (PDP4)\r | |
122 | #define ADDRSIZE 13\r | |
123 | #define KSR28 0 /* Baudot terminal */\r | |
124 | #define TYPE62 0 /* Hollerith printer */\r | |
125 | #define TYPE550 0 /* DECtape */\r | |
126 | #define DRM 0 /* drum */\r | |
127 | #elif defined (PDP7)\r | |
128 | #define ADDRSIZE 15\r | |
129 | #define TYPE647 0 /* sixbit printer */\r | |
130 | #define TYPE550 0 /* DECtape */\r | |
131 | #define DRM 0 /* drum */\r | |
132 | #elif defined (PDP9)\r | |
133 | #define ADDRSIZE 15\r | |
134 | #define TYPE647 0 /* sixbit printer */\r | |
135 | #define LP09 0 /* ASCII printer */\r | |
136 | #define RB 0 /* fixed head disk */\r | |
137 | #define RF 0 /* fixed head disk */\r | |
138 | #define MTA 0 /* magtape */\r | |
139 | #define TC02 0 /* DECtape */\r | |
140 | #define TTY1 4 /* second Teletype(s) */\r | |
141 | #define BRMASK 0076000 /* bounds mask */\r | |
142 | #elif defined (PDP15)\r | |
143 | #define ADDRSIZE 17\r | |
144 | #define LP09 0 /* ASCII printer */\r | |
145 | #define LP15 0 /* DMA printer */\r | |
146 | #define RF 0 /* fixed head disk */\r | |
147 | #define RP 0 /* disk pack */\r | |
148 | #define MTA 0 /* magtape */\r | |
149 | #define TC02 0 /* DECtape */\r | |
150 | #define TTY1 16 /* second Teletype(s) */\r | |
151 | #define BRMASK 0377400 /* bounds mask */\r | |
152 | #define BRMASK_XVM 0777400 /* bounds mask, XVM */\r | |
153 | #endif\r | |
154 | \r | |
155 | /* Memory */\r | |
156 | \r | |
157 | #define AMASK ((1 << ADDRSIZE) - 1) /* address mask */\r | |
158 | #define IAMASK 077777 /* ind address mask */\r | |
159 | #define BLKMASK (AMASK & (~IAMASK)) /* block mask */\r | |
160 | #define MAXMEMSIZE (1 << ADDRSIZE) /* max memory size */\r | |
161 | #define MEMSIZE (cpu_unit.capac) /* actual memory size */\r | |
162 | #define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)\r | |
163 | \r | |
164 | /* Instructions */\r | |
165 | \r | |
166 | #define I_V_OP 14 /* opcode */\r | |
167 | #define I_M_OP 017\r | |
168 | #define I_V_IND 13 /* indirect */\r | |
169 | #define I_V_IDX 12 /* index */\r | |
170 | #define I_IND (1 << I_V_IND)\r | |
171 | #define I_IDX (1 << I_V_IDX)\r | |
172 | #define B_DAMASK 017777 /* bank mode address */\r | |
173 | #define B_EPCMASK (AMASK & ~B_DAMASK)\r | |
174 | #define P_DAMASK 007777 /* page mode address */\r | |
175 | #define P_EPCMASK (AMASK & ~P_DAMASK)\r | |
176 | \r | |
177 | /* Memory cycles */\r | |
178 | \r | |
179 | #define FE 0\r | |
180 | #define DF 1\r | |
181 | #define RD 2\r | |
182 | #define WR 3\r | |
183 | \r | |
184 | /* Memory status codes */\r | |
185 | \r | |
186 | #define MM_OK 0\r | |
187 | #define MM_ERR 1\r | |
188 | \r | |
189 | /* Memory management relocation checks (PDP-15 KT15 and XVM only) */\r | |
190 | \r | |
191 | #define REL_C -1 /* console */\r | |
192 | #define REL_R 0 /* read */\r | |
193 | #define REL_W 1 /* write */\r | |
194 | \r | |
195 | /* Architectural constants */\r | |
196 | \r | |
197 | #define DMASK 0777777 /* data mask */\r | |
198 | #define LINK (DMASK + 1) /* link */\r | |
199 | #define LACMASK (LINK | DMASK) /* link + data */\r | |
200 | #define SIGN 0400000 /* sign bit */\r | |
201 | #define OP_JMS 0100000 /* JMS */\r | |
202 | #define OP_JMP 0600000 /* JMP */\r | |
203 | #define OP_HLT 0740040 /* HLT */\r | |
204 | \r | |
205 | /* IOT subroutine return codes */\r | |
206 | \r | |
207 | #define IOT_V_SKP 18 /* skip */\r | |
208 | #define IOT_V_REASON 19 /* reason */\r | |
209 | #define IOT_SKP (1 << IOT_V_SKP)\r | |
210 | #define IOT_REASON (1 << IOT_V_REASON)\r | |
211 | \r | |
212 | #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */\r | |
213 | \r | |
214 | /* PC change queue */\r | |
215 | \r | |
216 | #define PCQ_SIZE 64 /* must be 2**n */\r | |
217 | #define PCQ_MASK (PCQ_SIZE - 1)\r | |
218 | #define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = PC\r | |
219 | \r | |
220 | /* XVM memory management registers */\r | |
221 | \r | |
222 | #define MM_RDIS 0400000 /* reloc disabled */\r | |
223 | #define MM_V_GM 15 /* G mode */\r | |
224 | #define MM_M_GM 03\r | |
225 | #define MM_GM (MM_M_GM << MM_V_GM)\r | |
226 | #define MM_G_W0 0077777 /* virt addr width */\r | |
227 | #define MM_G_W1 0177777\r | |
228 | #define MM_G_W2 0777777\r | |
229 | #define MM_G_W3 0377777\r | |
230 | #define MM_G_B0 0060000 /* SAS base */\r | |
231 | #define MM_G_B1 0160000\r | |
232 | #define MM_G_B2 0760000\r | |
233 | #define MM_G_B3 0360000\r | |
234 | #define MM_UIOT 0040000 /* user mode IOT's */\r | |
235 | #define MM_WP 0020000 /* share write prot */\r | |
236 | #define MM_SH 0010000 /* share enabled */\r | |
237 | #define MM_V_SLR 10 /* segment length reg */\r | |
238 | #define MM_M_SLR 03\r | |
239 | #define MM_SLR_L0 001000 /* SAS length */\r | |
240 | #define MM_SLR_L1 002000\r | |
241 | #define MM_SLR_L2 010000\r | |
242 | #define MM_SLR_L3 020000\r | |
243 | #define MM_SBR_MASK 01777 /* share base reg */\r | |
244 | #define MM_GETGM(x) (((x) >> MM_V_GM) & MM_M_GM)\r | |
245 | #define MM_GETSLR(x) (((x) >> MM_V_SLR) & MM_M_SLR)\r | |
246 | \r | |
247 | /* Device information block */\r | |
248 | \r | |
249 | #define DEV_MAXBLK 8 /* max dev block */\r | |
250 | #define DEV_MAX 64 /* total devices */\r | |
251 | \r | |
252 | typedef struct {\r | |
253 | uint32 dev; /* base dev number */\r | |
254 | uint32 num; /* number of slots */\r | |
255 | int32 (*iors)(void); /* IORS responder */\r | |
256 | int32 (*dsp[DEV_MAXBLK])(int32 dev, int32 pulse, int32 dat);\r | |
257 | } DIB;\r | |
258 | \r | |
259 | /* Standard device numbers */\r | |
260 | \r | |
261 | #define DEV_PTR 001 /* paper tape reader */\r | |
262 | #define DEV_PTP 002 /* paper tape punch */\r | |
263 | #define DEV_TTI 003 /* console input */\r | |
264 | #define DEV_TTO 004 /* console output */\r | |
265 | #define DEV_TTI1 041 /* extra terminals */\r | |
266 | #define DEV_TTO1 040\r | |
267 | #define DEV_DRM 060 /* drum */\r | |
268 | #define DEV_RP 063 /* RP15 */\r | |
269 | #define DEV_LPT 065 /* line printer */\r | |
270 | #define DEV_RF 070 /* RF09 */\r | |
271 | #define DEV_RB 071 /* RB09 */\r | |
272 | #define DEV_MT 073 /* magtape */\r | |
273 | #define DEV_DTA 075 /* dectape */\r | |
274 | \r | |
275 | /* Interrupt system\r | |
276 | \r | |
277 | The interrupt system can be modelled on either the flag driven system\r | |
278 | of the PDP-4 and PDP-7 or the API driven system of the PDP-9 and PDP-15.\r | |
279 | If flag based, API is hard to implement; if API based, IORS requires\r | |
280 | extra code for implementation. I've chosen an API based model.\r | |
281 | \r | |
282 | API channel Device API priority Notes\r | |
283 | \r | |
284 | 00 software 4 4\r | |
285 | 01 software 5 5\r | |
286 | 02 software 6 6\r | |
287 | 03 software 7 7\r | |
288 | 04 TC02/TC15 1\r | |
289 | 05 TC59D 1\r | |
290 | 06 drum 1 PDP-9 only\r | |
291 | 07 RB09 1 PDP-9 only\r | |
292 | 10 paper tape reader 2\r | |
293 | 11 real time clock 3\r | |
294 | 12 power fail 0\r | |
295 | 13 memory parity 0\r | |
296 | 14 display 2\r | |
297 | 15 card reader 2\r | |
298 | 16 line printer 2\r | |
299 | 17 A/D converter 0\r | |
300 | 20 interprocessor buffer 3\r | |
301 | 21 360 link 3 PDP-9 only\r | |
302 | 22 data phone 2 PDP-15 only\r | |
303 | 23 RF09/RF15 1\r | |
304 | 24 RP15 1 PDP-15 only\r | |
305 | 25 plotter 1 PDP-15 only\r | |
306 | 26 -\r | |
307 | 27 -\r | |
308 | 30 -\r | |
309 | 31 -\r | |
310 | 32 -\r | |
311 | 33 -\r | |
312 | 34 LT15 TTO 3 PDP-15 only\r | |
313 | 35 LT15 TTI 3 PDP-15 only\r | |
314 | 36 -\r | |
315 | 37 -\r | |
316 | \r | |
317 | On the PDP-9, any API level active masks PI, and PI does not mask API.\r | |
318 | On the PDP-15, only the hardware API levels active mask PI, and PI masks\r | |
319 | the API software levels. */\r | |
320 | \r | |
321 | #define API_ML0 0200 /* API masks: level 0 */\r | |
322 | #define API_ML1 0100\r | |
323 | #define API_ML2 0040\r | |
324 | #define API_ML3 0020\r | |
325 | #define API_ML4 0010\r | |
326 | #define API_ML5 0004\r | |
327 | #define API_ML6 0002\r | |
328 | #define API_ML7 0001 /* level 7 */\r | |
329 | \r | |
330 | #if defined (PDP9) /* levels which mask PI */\r | |
331 | #define API_MASKPI (API_ML0|API_ML1|API_ML2|API_ML3|API_ML4|API_ML5|API_ML6|API_ML7)\r | |
332 | #else\r | |
333 | #define API_MASKPI (API_ML0|API_ML1|API_ML2|API_ML3)\r | |
334 | #endif\r | |
335 | \r | |
336 | #define API_HLVL 4 /* hwre levels */\r | |
337 | #define ACH_SWRE 040 /* swre int vec */\r | |
338 | \r | |
339 | /* API level 0 */\r | |
340 | \r | |
341 | #define INT_V_PWRFL 0 /* powerfail */\r | |
342 | \r | |
343 | #define INT_PWRFL (1 << INT_V_PWRFL)\r | |
344 | \r | |
345 | #define API_PWRFL 0\r | |
346 | \r | |
347 | #define ACH_PWRFL 052\r | |
348 | \r | |
349 | /* API level 1 */\r | |
350 | \r | |
351 | #define INT_V_DTA 0 /* DECtape */\r | |
352 | #define INT_V_MTA 1 /* magtape */\r | |
353 | #define INT_V_DRM 2 /* drum */\r | |
354 | #define INT_V_RF 3 /* fixed head disk */\r | |
355 | #define INT_V_RP 4 /* disk pack */\r | |
356 | #define INT_V_RB 5 /* RB disk */\r | |
357 | \r | |
358 | #define INT_DTA (1 << INT_V_DTA)\r | |
359 | #define INT_MTA (1 << INT_V_MTA)\r | |
360 | #define INT_DRM (1 << INT_V_DRM)\r | |
361 | #define INT_RF (1 << INT_V_RF)\r | |
362 | #define INT_RP (1 << INT_V_RP)\r | |
363 | #define INT_RB (1 << INT_V_RB)\r | |
364 | \r | |
365 | #define API_DTA 1\r | |
366 | #define API_MTA 1\r | |
367 | #define API_DRM 1\r | |
368 | #define API_RF 1\r | |
369 | #define API_RP 1\r | |
370 | #define API_RB 1\r | |
371 | \r | |
372 | #define ACH_DTA 044\r | |
373 | #define ACH_MTA 045\r | |
374 | #define ACH_DRM 046\r | |
375 | #define ACH_RB 047\r | |
376 | #define ACH_RF 063\r | |
377 | #define ACH_RP 064\r | |
378 | \r | |
379 | /* API level 2 */\r | |
380 | \r | |
381 | #define INT_V_PTR 0 /* paper tape reader */\r | |
382 | #define INT_V_LPT 1 /* line printer */\r | |
383 | #define INT_V_LPTSPC 2 /* line printer spc */\r | |
384 | \r | |
385 | #define INT_PTR (1 << INT_V_PTR)\r | |
386 | #define INT_LPT (1 << INT_V_LPT)\r | |
387 | #define INT_LPTSPC (1 << INT_V_LPTSPC)\r | |
388 | \r | |
389 | #define API_PTR 2\r | |
390 | #define API_LPT 2\r | |
391 | #define API_LPTSPC 2\r | |
392 | \r | |
393 | #define ACH_PTR 050\r | |
394 | #define ACH_LPT 056\r | |
395 | \r | |
396 | /* API level 3 */\r | |
397 | \r | |
398 | #define INT_V_CLK 0 /* clock */\r | |
399 | #define INT_V_TTI1 1 /* LT15 keyboard */\r | |
400 | #define INT_V_TTO1 2 /* LT15 output */\r | |
401 | \r | |
402 | #define INT_CLK (1 << INT_V_CLK)\r | |
403 | #define INT_TTI1 (1 << INT_V_TTI1)\r | |
404 | #define INT_TTO1 (1 << INT_V_TTO1)\r | |
405 | \r | |
406 | #define API_CLK 3\r | |
407 | #define API_TTI1 3\r | |
408 | #define API_TTO1 3\r | |
409 | \r | |
410 | #define ACH_CLK 051\r | |
411 | #define ACH_TTI1 075\r | |
412 | #define ACH_TTO1 074\r | |
413 | \r | |
414 | /* PI level */\r | |
415 | \r | |
416 | #define INT_V_TTI 0 /* console keyboard */\r | |
417 | #define INT_V_TTO 1 /* console output */\r | |
418 | #define INT_V_PTP 2 /* paper tape punch */\r | |
419 | \r | |
420 | #define INT_TTI (1 << INT_V_TTI)\r | |
421 | #define INT_TTO (1 << INT_V_TTO)\r | |
422 | #define INT_PTP (1 << INT_V_PTP)\r | |
423 | \r | |
424 | #define API_TTI 4 /* PI level */\r | |
425 | #define API_TTO 4\r | |
426 | #define API_PTP 4\r | |
427 | \r | |
428 | /* Interrupt macros */\r | |
429 | \r | |
430 | #define SET_INT(dv) int_hwre[API_##dv] = int_hwre[API_##dv] | INT_##dv\r | |
431 | #define CLR_INT(dv) int_hwre[API_##dv] = int_hwre[API_##dv] & ~INT_##dv\r | |
432 | #define TST_INT(dv) (int_hwre[API_##dv] & INT_##dv)\r | |
433 | \r | |
434 | /* I/O status flags for the IORS instruction\r | |
435 | \r | |
436 | bit PDP-4 PDP-7 PDP-9 PDP-15\r | |
437 | \r | |
438 | 0 intr on intr on intr on intr on\r | |
439 | 1 tape rdr flag* tape rdr flag* tape rdr flag* tape rdr flag*\r | |
440 | 2 tape pun flag* tape pun flag* tape pun flag* tape pun flag*\r | |
441 | 3 keyboard flag* keyboard flag* keyboard flag* keyboard flag*\r | |
442 | 4 type out flag* type out flag* type out flag* type out flag*\r | |
443 | 5 display flag* display flag* light pen flag* light pen flag*\r | |
444 | 6 clk ovflo flag* clk ovflo flag* clk ovflo flag* clk ovflo flag*\r | |
445 | 7 clk enable flag clk enable flag clk enable flag clk enable flag\r | |
446 | 8 mag tape flag* mag tape flag* tape rdr empty* tape rdr empty*\r | |
447 | 9 card rdr col* * tape pun empty tape pun empty\r | |
448 | 10 card rdr ~busy DECtape flag* DECtape flag*\r | |
449 | 11 card rdr error magtape flag* magtape flag*\r | |
450 | 12 card rdr EOF disk pack flag*\r | |
451 | 13 card pun row* DECdisk flag* DECdisk flag*\r | |
452 | 14 card pun error lpt flag*\r | |
453 | 15 lpt flag* lpt flag* lpt flag*\r | |
454 | 16 lpt space flag* lpt error flag lpt error flag\r | |
455 | 17 drum flag* drum flag*\r | |
456 | */\r | |
457 | \r | |
458 | #define IOS_ION 0400000 /* interrupts on */\r | |
459 | #define IOS_PTR 0200000 /* tape reader */\r | |
460 | #define IOS_PTP 0100000 /* tape punch */\r | |
461 | #define IOS_TTI 0040000 /* keyboard */\r | |
462 | #define IOS_TTO 0020000 /* terminal */\r | |
463 | #define IOS_LPEN 0010000 /* light pen */\r | |
464 | #define IOS_CLK 0004000 /* clock */\r | |
465 | #define IOS_CLKON 0002000 /* clock enable */\r | |
466 | #define IOS_DTA 0000200 /* DECtape */\r | |
467 | #define IOS_RP 0000040 /* disk pack */\r | |
468 | #define IOS_RF 0000020 /* fixed head disk */\r | |
469 | #define IOS_DRM 0000001 /* drum */\r | |
470 | #if defined (PDP4) || defined (PDP7)\r | |
471 | #define IOS_MTA 0001000 /* magtape */\r | |
472 | #define IOS_LPT 0000004 /* line printer */\r | |
473 | #define IOS_LPT1 0000002 /* line printer stat */\r | |
474 | #elif defined (PDP9)\r | |
475 | #define IOS_PTRERR 0001000 /* reader empty */\r | |
476 | #define IOS_PTPERR 0000400 /* punch empty */\r | |
477 | #define IOS_MTA 0000100 /* magtape */\r | |
478 | #define IOS_LPT 0000004 /* line printer */\r | |
479 | #define IOS_LPT1 0000002 /* line printer stat */\r | |
480 | #elif defined (PDP15)\r | |
481 | #define IOS_PTRERR 0001000 /* reader empty */\r | |
482 | #define IOS_PTPERR 0000400 /* punch empty */\r | |
483 | #define IOS_MTA 0000100 /* magtape */\r | |
484 | #define IOS_LPT 0000010 /* line printer */\r | |
485 | #define IOS_LPT1 0000000 /* not used */\r | |
486 | #endif\r | |
487 | \r | |
488 | /* Function prototypes */\r | |
489 | \r | |
490 | t_stat set_devno (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
491 | t_stat show_devno (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
492 | \r | |
493 | #endif\r |