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1 | /* sds_defs.h: SDS 940 simulator definitions \r |
2 | \r | |
3 | Copyright (c) 2001-2005, Robert M. Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | 25-Apr-03 RMS Revised for extended file support\r | |
27 | */\r | |
28 | \r | |
29 | #ifndef _SDS_DEFS_H_\r | |
30 | #define _SDS_DEFS_H_ 0\r | |
31 | \r | |
32 | #include "sim_defs.h" /* simulator defns */\r | |
33 | \r | |
34 | /* Simulator stop codes */\r | |
35 | \r | |
36 | #define STOP_IONRDY 1 /* I/O dev not ready */\r | |
37 | #define STOP_HALT 2 /* HALT */\r | |
38 | #define STOP_IBKPT 3 /* breakpoint */\r | |
39 | #define STOP_INVDEV 4 /* invalid dev */\r | |
40 | #define STOP_INVINS 5 /* invalid instr */\r | |
41 | #define STOP_INVIOP 6 /* invalid I/O op */\r | |
42 | #define STOP_INDLIM 7 /* indirect limit */\r | |
43 | #define STOP_EXULIM 8 /* EXU limit */\r | |
44 | #define STOP_MMINT 9 /* mm in intr */\r | |
45 | #define STOP_MMTRP 10 /* mm in trap */\r | |
46 | #define STOP_TRPINS 11 /* trap inst not BRM */\r | |
47 | #define STOP_RTCINS 12 /* rtc inst not MIN/SKR */\r | |
48 | #define STOP_ILLVEC 13 /* zero vector */\r | |
49 | #define STOP_CCT 14 /* runaway CCT */\r | |
50 | \r | |
51 | /* Trap codes */\r | |
52 | \r | |
53 | #define MM_PRVINS -040 /* privileged */\r | |
54 | #define MM_NOACC -041 /* no access */\r | |
55 | #define MM_WRITE -043 /* write protect */\r | |
56 | #define MM_MONUSR -044 /* mon to user */\r | |
57 | \r | |
58 | /* Conditional error returns */\r | |
59 | \r | |
60 | #define CRETINS return ((stop_invins)? STOP_INVINS: SCPE_OK)\r | |
61 | #define CRETDEV return ((stop_invdev)? STOP_INVDEV: SCPE_OK)\r | |
62 | #define CRETIOP return ((stop_inviop)? STOP_INVIOP: SCPE_OK)\r | |
63 | #define CRETIOE(f,c) return ((f)? c: SCPE_OK)\r | |
64 | \r | |
65 | /* Architectural constants */\r | |
66 | \r | |
67 | #define SIGN 040000000 /* sign */\r | |
68 | #define DMASK 077777777 /* data mask */\r | |
69 | #define EXPS 0400 /* exp sign */\r | |
70 | #define EXPMASK 0777 /* exp mask */\r | |
71 | #define SXT(x) ((int32) (((x) & SIGN)? ((x) | ~DMASK): \\r | |
72 | ((x) & DMASK)))\r | |
73 | #define SXT_EXP(x) ((int32) (((x) & EXPS)? ((x) | ~EXPMASK): \\r | |
74 | ((x) & EXPMASK)))\r | |
75 | \r | |
76 | /* Memory */\r | |
77 | \r | |
78 | #define MAXMEMSIZE (1 << 16) /* max memory size */\r | |
79 | #define PAMASK (MAXMEMSIZE - 1) /* physical addr mask */\r | |
80 | #define MEMSIZE (cpu_unit.capac) /* actual memory size */\r | |
81 | #define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)\r | |
82 | #define ReadP(x) M[x]\r | |
83 | #define WriteP(x,y) if (MEM_ADDR_OK (x)) M[x] = y\r | |
84 | \r | |
85 | /* Virtual addressing */\r | |
86 | \r | |
87 | #define VA_SIZE (1 << 14) /* virtual addr size */\r | |
88 | #define VA_MASK (VA_SIZE - 1) /* virtual addr mask */\r | |
89 | #define VA_V_PN 11 /* page number */\r | |
90 | #define VA_M_PN 07\r | |
91 | #define VA_GETPN(x) (((x) >> VA_V_PN) & VA_M_PN)\r | |
92 | #define VA_POFF ((1 << VA_V_PN) - 1) /* offset */\r | |
93 | #define VA_USR (I_USR) /* user flag in addr */\r | |
94 | #define XVA_MASK (VA_USR | VA_MASK)\r | |
95 | \r | |
96 | /* Arithmetic */\r | |
97 | \r | |
98 | #define TSTS(x) ((x) & SIGN)\r | |
99 | #define NEG(x) (-((int32) (x)) & DMASK)\r | |
100 | #define ABS(x) (TSTS (x)? NEG(x): (x))\r | |
101 | \r | |
102 | /* Memory map */\r | |
103 | \r | |
104 | #define MAP_PROT (040 << VA_V_PN) /* protected */\r | |
105 | #define MAP_PAGE (037 << VA_V_PN) /* phys page number */\r | |
106 | \r | |
107 | /* Instruction format */\r | |
108 | \r | |
109 | #define I_USR (1 << 23) /* user */\r | |
110 | #define I_IDX (1 << 22) /* indexed */\r | |
111 | #define I_POP (1 << 21) /* programmed op */\r | |
112 | #define I_V_TAG 21 /* tag */\r | |
113 | #define I_V_OP 15 /* opcode */\r | |
114 | #define I_M_OP 077\r | |
115 | #define I_GETOP(x) (((x) >> I_V_OP) & I_M_OP)\r | |
116 | #define I_IND (1 << 14) /* indirect */\r | |
117 | #define I_V_SHFOP 11 /* shift op */\r | |
118 | #define I_M_SHFOP 07\r | |
119 | #define I_GETSHFOP(x) (((x) >> I_V_SHFOP) & I_M_SHFOP)\r | |
120 | #define I_SHFMSK 0777 /* shift count */\r | |
121 | #define I_V_IOMD 12 /* IO inst mode */\r | |
122 | #define I_M_IOMD 03\r | |
123 | #define I_GETIOMD(x) (((x) >> I_V_IOMD) & I_M_IOMD)\r | |
124 | #define I_V_SKCND 7 /* SKS skip cond */\r | |
125 | #define I_M_SKCND 037\r | |
126 | #define I_GETSKCND(x) (((x) >> I_V_SKCND) & I_M_SKCND)\r | |
127 | #define I_EOB2 000400000 /* chan# bit 2 */\r | |
128 | #define I_SKB2 000040000 /* skschan# bit 2 */\r | |
129 | #define I_EOB1 020000000 /* chan# bit 1 */\r | |
130 | #define I_EOB0 000000100 /* chan# bit 0 */\r | |
131 | #define I_GETEOCH(x) ((((x) & I_EOB2)? 4: 0) | \\r | |
132 | (((x) & I_EOB1)? 2: 0) | \\r | |
133 | (((x) & I_EOB0)? 1: 0))\r | |
134 | #define I_SETEOCH(x) ((((x) & 4)? I_EOB2: 0) | \\r | |
135 | (((x) & 2)? I_EOB1: 0) | \\r | |
136 | (((x) & 1)? I_EOB0: 0))\r | |
137 | #define I_GETSKCH(x) ((((x) & I_SKB2)? 4: 0) | \\r | |
138 | (((x) & I_EOB1)? 2: 0) | \\r | |
139 | (((x) & I_EOB0)? 1: 0))\r | |
140 | #define I_SETSKCH(x) ((((x) & 4)? I_SKB2: 0) | \\r | |
141 | (((x) & 2)? I_EOB1: 0) | \\r | |
142 | (((x) & 1)? I_EOB0: 0))\r | |
143 | \r | |
144 | /* Globally visible flags */\r | |
145 | \r | |
146 | #define UNIT_V_GENIE (UNIT_V_UF + 0)\r | |
147 | #define UNIT_GENIE (1 << UNIT_V_GENIE)\r | |
148 | \r | |
149 | /* Timers */\r | |
150 | \r | |
151 | #define TMR_RTC 0 /* clock */\r | |
152 | #define TMR_MUX 1 /* mux */\r | |
153 | \r | |
154 | /* I/O routine functions */\r | |
155 | \r | |
156 | #define IO_CONN 0 /* connect */\r | |
157 | #define IO_EOM1 1 /* EOM mode 1 */\r | |
158 | #define IO_DISC 2 /* disconnect */\r | |
159 | #define IO_READ 3 /* read */\r | |
160 | #define IO_WRITE 4 /* write */\r | |
161 | #define IO_WREOR 5 /* write eor */\r | |
162 | #define IO_SKS 6 /* skip signal */\r | |
163 | \r | |
164 | /* Dispatch template */\r | |
165 | \r | |
166 | struct sdsdspt {\r | |
167 | uint32 num; /* # entries */\r | |
168 | uint32 off; /* offset from base */\r | |
169 | };\r | |
170 | \r | |
171 | typedef struct sdsdspt DSPT;\r | |
172 | \r | |
173 | /* Device information block */\r | |
174 | \r | |
175 | struct sdsdib {\r | |
176 | int32 chan; /* channel */\r | |
177 | int32 dev; /* base dev no */\r | |
178 | int32 xfr; /* xfer flag */\r | |
179 | DSPT *tplt; /* dispatch templates */\r | |
180 | t_stat (*iop) (uint32 fnc, uint32 dev, uint32 *dat);\r | |
181 | };\r | |
182 | \r | |
183 | typedef struct sdsdib DIB;\r | |
184 | \r | |
185 | /* Channels */\r | |
186 | \r | |
187 | #define NUM_CHAN 8 /* max num chan */\r | |
188 | #define CHAN_W 0 /* TMCC */\r | |
189 | #define CHAN_Y 1\r | |
190 | #define CHAN_C 2\r | |
191 | #define CHAN_D 3\r | |
192 | #define CHAN_E 4 /* DACC */\r | |
193 | #define CHAN_F 5\r | |
194 | #define CHAN_G 6\r | |
195 | #define CHAN_H 7\r | |
196 | \r | |
197 | /* I/O control EOM */\r | |
198 | \r | |
199 | #define CHC_REV 04000 /* reverse */\r | |
200 | #define CHC_NLDR 02000 /* no leader */\r | |
201 | #define CHC_BIN 01000 /* binary */\r | |
202 | #define CHC_V_CPW 7 /* char/word */\r | |
203 | #define CHC_M_CPW 03\r | |
204 | #define CHC_GETCPW(x) (((x) >> CHC_V_CPW) & CHC_M_CPW)\r | |
205 | \r | |
206 | /* Buffer control (extended) EOM */\r | |
207 | \r | |
208 | #define CHM_CE 04000 /* compat/ext */\r | |
209 | #define CHM_ER 02000 /* end rec int */\r | |
210 | #define CHM_ZC 01000 /* zero wc int */\r | |
211 | #define CHM_V_FNC 7 /* term func */\r | |
212 | #define CHM_M_FNC 03\r | |
213 | #define CHM_GETFNC(x) (((x) & CHM_CE)? (((x) >> CHM_V_FNC) & CHM_M_FNC): CHM_COMP)\r | |
214 | #define CHM_IORD 0 /* record, disc */\r | |
215 | #define CHM_IOSD 1 /* signal, disc */\r | |
216 | #define CHM_IORP 2 /* record, proc */\r | |
217 | #define CHM_IOSP 3 /* signal, proc */\r | |
218 | #define CHM_COMP 5 /* compatible */\r | |
219 | #define CHM_SGNL 1 /* signal bit */\r | |
220 | #define CHM_PROC 2 /* proceed bit */\r | |
221 | #define CHM_V_HMA 5 /* hi mem addr */\r | |
222 | #define CHM_M_HMA 03\r | |
223 | #define CHM_GETHMA(x) (((x) >> CHM_V_HMA) & CHM_M_HMA)\r | |
224 | #define CHM_V_HWC 0 /* hi word count */\r | |
225 | #define CHM_M_HWC 037\r | |
226 | #define CHM_GETHWC(x) (((x) >> CHM_V_HWC) & CHM_M_HWC)\r | |
227 | \r | |
228 | /* Channel flags word */\r | |
229 | \r | |
230 | #define CHF_ERR 00001 /* error */\r | |
231 | #define CHF_IREC 00002 /* interrecord */\r | |
232 | #define CHF_ILCE 00004 /* interlace */\r | |
233 | #define CHF_DCHN 00010 /* data chain */\r | |
234 | #define CHF_EOR 00020 /* end of record */\r | |
235 | #define CHF_12B 00040 /* 12 bit mode */\r | |
236 | #define CHF_24B 00100 /* 24 bit mode */\r | |
237 | #define CHF_OWAK 00200 /* output wake */\r | |
238 | #define CHF_SCAN 00400 /* scan */\r | |
239 | #define CHF_TOP 01000 /* TOP pending */\r | |
240 | #define CHF_N_FLG 9 /* <= 16 */\r | |
241 | \r | |
242 | /* Interrupts and vectors (0 is reserved), highest bit is highest priority */\r | |
243 | \r | |
244 | #define INT_V_PWRO 31 /* power on */\r | |
245 | #define INT_V_PWRF 30 /* power off */\r | |
246 | #define INT_V_CPAR 29 /* CPU parity err */\r | |
247 | #define INT_V_IPAR 28 /* IO parity err */\r | |
248 | #define INT_V_RTCS 27 /* clock sync */\r | |
249 | #define INT_V_RTCP 26 /* clock pulse */\r | |
250 | #define INT_V_YZWC 25 /* chan Y zero wc */\r | |
251 | #define INT_V_WZWC 24 /* chan W zero wc */\r | |
252 | #define INT_V_YEOR 23 /* chan Y end rec */\r | |
253 | #define INT_V_WEOR 22 /* chan W end rec */\r | |
254 | #define INT_V_CZWC 21 /* chan C */\r | |
255 | #define INT_V_CEOR 20\r | |
256 | #define INT_V_DZWC 19 /* chan D */\r | |
257 | #define INT_V_DEOR 18\r | |
258 | #define INT_V_EZWC 17 /* chan E */\r | |
259 | #define INT_V_EEOR 16\r | |
260 | #define INT_V_FZWC 15 /* chan F */\r | |
261 | #define INT_V_FEOR 14\r | |
262 | #define INT_V_GZWC 13 /* chan G */\r | |
263 | #define INT_V_GEOR 12\r | |
264 | #define INT_V_HZWC 11 /* chan H */\r | |
265 | #define INT_V_HEOR 10\r | |
266 | #define INT_V_MUXR 9 /* mux receive */\r | |
267 | #define INT_V_MUXT 8 /* mux transmit */\r | |
268 | #define INT_V_MUXCO 7 /* SDS carrier on */\r | |
269 | #define INT_V_MUXCF 6 /* SDS carrier off */\r | |
270 | #define INT_V_DRM 5 /* Genie drum */\r | |
271 | #define INT_V_FORK 4 /* fork */\r | |
272 | \r | |
273 | #define INT_PWRO (1 << INT_V_PWRO)\r | |
274 | #define INT_PWRF (1 << INT_V_PWRF)\r | |
275 | #define INT_CPAR (1 << INT_V_CPAR)\r | |
276 | #define INT_IPAR (1 << INT_V_IPAR)\r | |
277 | #define INT_RTCS (1 << INT_V_RTCS)\r | |
278 | #define INT_RTCP (1 << INT_V_RTCP)\r | |
279 | #define INT_YZWC (1 << INT_V_YZWC)\r | |
280 | #define INT_WZWC (1 << INT_V_WZWC)\r | |
281 | #define INT_YEOR (1 << INT_V_YEOR)\r | |
282 | #define INT_WEOR (1 << INT_V_WEOR)\r | |
283 | #define INT_CZWC (1 << INT_V_CZWC)\r | |
284 | #define INT_CEOR (1 << INT_V_CEOR)\r | |
285 | #define INT_DZWC (1 << INT_V_DZWC)\r | |
286 | #define INT_DEOR (1 << INT_V_DEOR)\r | |
287 | #define INT_EZWC (1 << INT_V_EZWC)\r | |
288 | #define INT_EEOR (1 << INT_V_EEOR)\r | |
289 | #define INT_FZWC (1 << INT_V_FZWC)\r | |
290 | #define INT_FEOR (1 << INT_V_FEOR)\r | |
291 | #define INT_GZWC (1 << INT_V_GZWC)\r | |
292 | #define INT_GEOR (1 << INT_V_GEOR)\r | |
293 | #define INT_HZWC (1 << INT_V_HZWC)\r | |
294 | #define INT_HEOR (1 << INT_V_HEOR)\r | |
295 | #define INT_MUXR (1 << INT_V_MUXR)\r | |
296 | #define INT_MUXT (1 << INT_V_MUXT)\r | |
297 | #define INT_MUXCO (1 << INT_V_MUXCO)\r | |
298 | #define INT_MUXCF (1 << INT_V_MUXCF)\r | |
299 | #define INT_DRM (1 << INT_V_DRM)\r | |
300 | #define INT_FORK (1 << INT_V_FORK)\r | |
301 | \r | |
302 | #define VEC_PWRO 0036\r | |
303 | #define VEC_PWRF 0037\r | |
304 | #define VEC_CPAR 0056\r | |
305 | #define VEC_IPAR 0057\r | |
306 | #define VEC_RTCS 0074\r | |
307 | #define VEC_RTCP 0075\r | |
308 | #define VEC_YZWC 0030\r | |
309 | #define VEC_WZWC 0031\r | |
310 | #define VEC_YEOR 0032\r | |
311 | #define VEC_WEOR 0033\r | |
312 | #define VEC_CZWC 0060\r | |
313 | #define VEC_CEOR 0061\r | |
314 | #define VEC_DZWC 0062\r | |
315 | #define VEC_DEOR 0063\r | |
316 | #define VEC_EZWC 0064\r | |
317 | #define VEC_EEOR 0065\r | |
318 | #define VEC_FZWC 0066\r | |
319 | #define VEC_FEOR 0067\r | |
320 | #define VEC_GZWC 0070\r | |
321 | #define VEC_GEOR 0071\r | |
322 | #define VEC_HZWC 0072\r | |
323 | #define VEC_HEOR 0073\r | |
324 | #define VEC_MUXR 0200 /* term mux rcv */\r | |
325 | #define VEC_MUXT 0201 /* term mux xmt */\r | |
326 | #define VEC_MUXCO 0202 /* SDS: mux carrier on */\r | |
327 | #define VEC_MUXCF 0203 /* SDS: mux carrier off */\r | |
328 | #define VEC_DRM 0202 /* Genie: drum */\r | |
329 | #define VEC_FORK 0216 /* "fork" */\r | |
330 | \r | |
331 | /* Device constants */\r | |
332 | \r | |
333 | #define DEV_MASK 077 /* device mask */\r | |
334 | #define DEV_TTI 001 /* teletype */\r | |
335 | #define DEV_PTR 004 /* paper tape rdr */\r | |
336 | #define DEV_MT 010 /* magtape */\r | |
337 | #define DEV_RAD 026 /* fixed head disk */\r | |
338 | #define DEV_DSK 026 /* moving head disk */\r | |
339 | #define DEV_TTO 041 /* teletype */\r | |
340 | #define DEV_PTP 044 /* paper tape punch */\r | |
341 | #define DEV_LPT 060 /* line printer */\r | |
342 | #define DEV_MTS 020 /* MT scan/erase */\r | |
343 | #define DEV_OUT 040 /* output flag */\r | |
344 | #define DEV3_GDRM 004 /* Genie drum */\r | |
345 | #define DEV3_GMUX 001 /* Genie mux */\r | |
346 | #define DEV3_SMUX (DEV_MASK) /* standard mux */\r | |
347 | \r | |
348 | #define LPT_WIDTH 132 /* line print width */\r | |
349 | #define CCT_LNT 132 /* car ctrl length */\r | |
350 | \r | |
351 | /* Transfer request flags for devices (0 is reserved) */\r | |
352 | \r | |
353 | #define XFR_V_TTI 1 /* console */\r | |
354 | #define XFR_V_TTO 2\r | |
355 | #define XFR_V_PTR 3 /* paper tape */\r | |
356 | #define XFR_V_PTP 4\r | |
357 | #define XFR_V_LPT 5 /* line printer */\r | |
358 | #define XFR_V_RAD 6 /* fixed hd disk */\r | |
359 | #define XFR_V_DSK 7 /* mving hd disk */\r | |
360 | #define XFR_V_MT0 8 /* magtape */\r | |
361 | \r | |
362 | #define XFR_TTI (1 << XFR_V_TTI)\r | |
363 | #define XFR_TTO (1 << XFR_V_TTO)\r | |
364 | #define XFR_PTR (1 << XFR_V_PTR)\r | |
365 | #define XFR_PTP (1 << XFR_V_PTP)\r | |
366 | #define XFR_LPT (1 << XFR_V_LPT)\r | |
367 | #define XFR_RAD (1 << XFR_V_RAD)\r | |
368 | #define XFR_DSK (1 << XFR_V_DSK)\r | |
369 | #define XFR_MT0 (1 << XFR_V_MT0)\r | |
370 | \r | |
371 | /* PIN/POT ordinals (0 is reserved) */\r | |
372 | \r | |
373 | #define POT_ILCY 1 /* interlace */\r | |
374 | #define POT_DCRY (POT_ILCY + NUM_CHAN) /* data chain */\r | |
375 | #define POT_ADRY (POT_DCRY + NUM_CHAN) /* address reg */\r | |
376 | #define POT_RL1 (POT_ADRY + NUM_CHAN) /* RL1 */\r | |
377 | #define POT_RL2 (POT_RL1 + 1) /* RL2 */\r | |
378 | #define POT_RL4 (POT_RL2 + 1) /* RL4 */\r | |
379 | #define POT_RADS (POT_RL4 + 1) /* fhd sector */\r | |
380 | #define POT_RADA (POT_RADS + 1) /* fhd addr */\r | |
381 | #define POT_DSK (POT_RADA + 1) /* mhd sec/addr */\r | |
382 | #define POT_SYSI (POT_DSK + 1) /* sys intr */\r | |
383 | #define POT_MUX (POT_SYSI + 1) /* multiplexor */\r | |
384 | \r | |
385 | /* Opcodes */\r | |
386 | \r | |
387 | enum opcodes {\r | |
388 | HLT, BRU, EOM, EOD = 006,\r | |
389 | MIY = 010, BRI, MIW, POT, ETR, MRG = 016, EOR,\r | |
390 | NOP, OVF = 022, EXU,\r | |
391 | YIM = 030, WIM = 032, PIN, STA = 035, STB, STX,\r | |
392 | SKS, BRX, BRM = 043, RCH = 046,\r | |
393 | SKE = 050, BRR, SKB, SKN, SUB, ADD, SUC, ADC,\r | |
394 | SKR, MIN, XMA, ADM, MUL, DIV, RSH, LSH,\r | |
395 | SKM, LDX, SKA, SKG, SKD, LDB, LDA, EAX\r | |
396 | };\r | |
397 | \r | |
398 | /* Channel function prototypes */\r | |
399 | \r | |
400 | void chan_set_flag (int32 ch, uint32 fl);\r | |
401 | void chan_set_ordy (int32 ch);\r | |
402 | void chan_disc (int32 ch);\r | |
403 | void chan_set_uar (int32 ch, uint32 dev);\r | |
404 | t_stat set_chan (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
405 | t_stat show_chan (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
406 | t_stat chan_process (void);\r | |
407 | t_bool chan_testact (void);\r | |
408 | \r | |
409 | #endif\r |