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1 | \r |
2 | /* vax780_defs.h: VAX 780 model-specific definitions file\r | |
3 | \r | |
4 | Copyright (c) 2004-2007, Robert M Supnik\r | |
5 | \r | |
6 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
7 | copy of this software and associated documentation files (the "Software"),\r | |
8 | to deal in the Software without restriction, including without limitation\r | |
9 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
10 | and/or sell copies of the Software, and to permit persons to whom the\r | |
11 | Software is furnished to do so, subject to the following conditions:\r | |
12 | \r | |
13 | The above copyright notice and this permission notice shall be included in\r | |
14 | all copies or substantial portions of the Software.\r | |
15 | \r | |
16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
19 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
20 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
21 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
22 | \r | |
23 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
24 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
25 | in this Software without prior written authorization from Robert M Supnik.\r | |
26 | \r | |
27 | 29-Apr-07 RMS Modified model-specific reserved operand check macros\r | |
28 | to reflect 780 microcode patches (found by Naoki Hamada)\r | |
29 | 29-Oct-06 RMS Added clock coscheduler function\r | |
30 | 17-May-06 RMS Added CR11/CD11 support (from John Dundas)\r | |
31 | 10-May-06 RMS Added model-specific reserved operand check macros\r | |
32 | \r | |
33 | This file covers the VAX 11/780, the first VAX.\r | |
34 | \r | |
35 | System memory map\r | |
36 | \r | |
37 | 0000 0000 - 1FFF FFFF main memory\r | |
38 | \r | |
39 | 2000 0000 - 2001 FFFF nexus register space\r | |
40 | 2002 0000 - 200F FFFF reserved\r | |
41 | 2010 0000 - 2013 FFFF Unibus address space, Unibus 0\r | |
42 | 2014 0000 - 2017 FFFF Unibus address space, Unibus 1\r | |
43 | 2018 0000 - 201B FFFF Unibus address space, Unibus 2\r | |
44 | 201C 0000 - 201F FFFF Unibus address space, Unibus 3\r | |
45 | 2020 0000 - 3FFF FFFF reserved\r | |
46 | */\r | |
47 | \r | |
48 | #ifndef FULL_VAX\r | |
49 | #define FULL_VAX 1\r | |
50 | #endif\r | |
51 | \r | |
52 | #ifndef _VAX_780_DEFS_H_\r | |
53 | #define _VAX_780_DEFS_H_ 1\r | |
54 | \r | |
55 | /* Microcode constructs */\r | |
56 | \r | |
57 | #define VAX780_SID (1 << 24) /* system ID */\r | |
58 | #define VAX780_ECO (7 << 19) /* ucode revision */\r | |
59 | #define VAX780_PLANT (0 << 12) /* plant (Salem NH) */\r | |
60 | #define VAX780_SN (1234)\r | |
61 | #define CON_HLTPIN 0x0200 /* external CPU halt */\r | |
62 | #define CON_HLTINS 0x0600 /* HALT instruction */\r | |
63 | #define MCHK_RD_F 0x00 /* read fault */\r | |
64 | #define MCHK_RD_A 0xF4 /* read abort */\r | |
65 | #define MCHK_IBUF 0x0D /* read istream */\r | |
66 | #define VER_FPLA 0x0C /* FPLA version */\r | |
67 | #define VER_WCSP (VER_FPLA) /* WCS primary version */\r | |
68 | #define VER_WCSS 0x12 /* WCS secondary version */\r | |
69 | #define VER_PCS ((VER_WCSS >> 4) & 0x3) /* PCS version */\r | |
70 | \r | |
71 | /* Interrupts */\r | |
72 | \r | |
73 | #define IPL_HMAX 0x17 /* highest hwre level */\r | |
74 | #define IPL_HMIN 0x14 /* lowest hwre level */\r | |
75 | #define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */\r | |
76 | #define IPL_SMAX 0xF /* highest swre level */\r | |
77 | \r | |
78 | /* Nexus constants */\r | |
79 | \r | |
80 | #define NEXUS_NUM 16 /* number of nexus */\r | |
81 | #define MCTL_NUM 2 /* number of mem ctrl */\r | |
82 | #define MBA_NUM 2 /* number of MBA's */\r | |
83 | #define TR_MCTL0 1 /* nexus assignments */\r | |
84 | #define TR_MCTL1 2\r | |
85 | #define TR_UBA 3\r | |
86 | #define TR_MBA0 8\r | |
87 | #define TR_MBA1 9\r | |
88 | #define NEXUS_HLVL (IPL_HMAX - IPL_HMIN + 1)\r | |
89 | #define SCB_NEXUS 0x100 /* nexus intr base */\r | |
90 | #define SBI_FAULTS 0xFC000000 /* SBI fault flags */\r | |
91 | \r | |
92 | /* Internal I/O interrupts - relative except for clock and console */\r | |
93 | \r | |
94 | #define IPL_CLKINT 0x18 /* clock IPL */\r | |
95 | #define IPL_TTINT 0x14 /* console IPL */\r | |
96 | \r | |
97 | #define IPL_MCTL0 (0x15 - IPL_HMIN)\r | |
98 | #define IPL_MCTL1 (0x15 - IPL_HMIN)\r | |
99 | #define IPL_UBA (0x15 - IPL_HMIN)\r | |
100 | #define IPL_MBA0 (0x15 - IPL_HMIN)\r | |
101 | #define IPL_MBA1 (0x15 - IPL_HMIN)\r | |
102 | \r | |
103 | /* Nexus interrupt macros */\r | |
104 | \r | |
105 | #define SET_NEXUS_INT(dv) nexus_req[IPL_##dv] |= (1 << TR_##dv)\r | |
106 | #define CLR_NEXUS_INT(dv) nexus_req[IPL_##dv] &= ~(1 << TR_##dv)\r | |
107 | \r | |
108 | /* Machine specific IPRs */\r | |
109 | \r | |
110 | #define MT_ACCS 40 /* FPA control */\r | |
111 | #define MT_ACCR 41 /* FPA maint */\r | |
112 | #define MT_WCSA 44 /* WCS address */\r | |
113 | #define MT_WCSD 45 /* WCS data */\r | |
114 | #define MT_SBIFS 48 /* SBI fault status */\r | |
115 | #define MT_SBIS 49 /* SBI silo */\r | |
116 | #define MT_SBISC 50 /* SBI silo comparator */\r | |
117 | #define MT_SBIMT 51 /* SBI maint */\r | |
118 | #define MT_SBIER 52 /* SBI error */\r | |
119 | #define MT_SBITA 53 /* SBI timeout addr */\r | |
120 | #define MT_SBIQC 54 /* SBI timeout clear */\r | |
121 | #define MT_MBRK 60 /* microbreak */\r | |
122 | \r | |
123 | /* Machine specific reserved operand tests */\r | |
124 | \r | |
125 | /* 780 microcode patch 37 - only test LR<23:0> for appropriate length */\r | |
126 | \r | |
127 | #define ML_LR_TEST(r) if ((uint32)((r) & 0xFFFFFF) > 0x200000) RSVD_OPND_FAULT\r | |
128 | \r | |
129 | /* 780 microcode patch 38 - only test PxBR<31>=1 and xBR<1:0> = 0 */\r | |
130 | \r | |
131 | #define ML_PXBR_TEST(r) if ((((r) & 0x80000000) == 0) || \\r | |
132 | ((r) & 0x00000003)) RSVD_OPND_FAULT\r | |
133 | #define ML_SBR_TEST(r) if ((r) & 0x00000003) RSVD_OPND_FAULT\r | |
134 | \r | |
135 | /* 780 microcode patch 78 - only test xCBB<1:0> = 0 */\r | |
136 | \r | |
137 | #define ML_PA_TEST(r) if ((r) & 0x00000003) RSVD_OPND_FAULT\r | |
138 | \r | |
139 | #define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT\r | |
140 | #define LP_MBZ84_TEST(r) if ((r) & 0xF8C00000) RSVD_OPND_FAULT\r | |
141 | #define LP_MBZ92_TEST(r) if ((r) & 0x7FC00000) RSVD_OPND_FAULT\r | |
142 | \r | |
143 | /* Memory */\r | |
144 | \r | |
145 | #define MAXMEMWIDTH 23 /* max mem, MS780C */\r | |
146 | #define MAXMEMSIZE (1 << MAXMEMWIDTH)\r | |
147 | #define MAXMEMWIDTH_X 27 /* max mem, MS780E */\r | |
148 | #define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X)\r | |
149 | #define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */\r | |
150 | #define MEMSIZE (cpu_unit.capac)\r | |
151 | #define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)\r | |
152 | \r | |
153 | /* Unibus I/O registers */\r | |
154 | \r | |
155 | #define UBADDRWIDTH 18 /* Unibus addr width */\r | |
156 | #define UBADDRSIZE (1u << UBADDRWIDTH) /* Unibus addr length */\r | |
157 | #define UBADDRMASK (UBADDRSIZE - 1) /* Unibus addr mask */\r | |
158 | #define IOPAGEAWIDTH 13 /* IO addr width */\r | |
159 | #define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */\r | |
160 | #define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */\r | |
161 | #define UBADDRBASE 0x20100000 /* Unibus addr base */\r | |
162 | #define IOPAGEBASE 0x2013E000 /* IO page base */\r | |
163 | #define ADDR_IS_IO(x) ((((uint32) (x)) >= UBADDRBASE) && \\r | |
164 | (((uint32) (x)) < (UBADDRBASE + UBADDRSIZE)))\r | |
165 | #define ADDR_IS_IOP(x) (((uint32) (x)) >= IOPAGEBASE)\r | |
166 | \r | |
167 | /* Nexus register space */\r | |
168 | \r | |
169 | #define REGAWIDTH 17 /* REG addr width */\r | |
170 | #define REG_V_NEXUS 13 /* nexus number */\r | |
171 | #define REG_M_NEXUS 0xF\r | |
172 | #define REG_V_OFS 2 /* register number */\r | |
173 | #define REG_M_OFS 0x7FF \r | |
174 | #define REGSIZE (1u << REGAWIDTH) /* REG length */\r | |
175 | #define REGBASE 0x20000000 /* REG addr base */\r | |
176 | #define ADDR_IS_REG(x) ((((uint32) (x)) >= REGBASE) && \\r | |
177 | (((uint32) (x)) < (REGBASE + REGSIZE)))\r | |
178 | #define NEXUS_GETNEX(x) (((x) >> REG_V_NEXUS) & REG_M_NEXUS)\r | |
179 | #define NEXUS_GETOFS(x) (((x) >> REG_V_OFS) & REG_M_OFS)\r | |
180 | \r | |
181 | /* ROM address space in memory controllers */\r | |
182 | \r | |
183 | #define ROMAWIDTH 12 /* ROM addr width */\r | |
184 | #define ROMSIZE (1u << ROMAWIDTH) /* ROM size */\r | |
185 | #define ROM0BASE (REGBASE + (TR_MCTL0 << REG_V_NEXUS) + 0x1000)\r | |
186 | #define ROM1BASE (REGBASE + (TR_MCTL1 << REG_V_NEXUS) + 0x1000)\r | |
187 | #define ADDR_IS_ROM0(x) ((((uint32) (x)) >= ROM0BASE) && \\r | |
188 | (((uint32) (x)) < (ROM0BASE + ROMSIZE)))\r | |
189 | #define ADDR_IS_ROM1(x) ((((uint32) (x)) >= ROM1BASE) && \\r | |
190 | (((uint32) (x)) < (ROM1BASE + ROMSIZE)))\r | |
191 | #define ADDR_IS_ROM(x) (ADDR_IS_ROM0 (x) || ADDR_IS_ROM1 (x))\r | |
192 | \r | |
193 | /* Other address spaces */\r | |
194 | \r | |
195 | #define ADDR_IS_CDG(x) (0)\r | |
196 | #define ADDR_IS_NVR(x) (0)\r | |
197 | \r | |
198 | /* Unibus I/O modes */\r | |
199 | \r | |
200 | #define READ 0 /* PDP-11 compatibility */\r | |
201 | #define WRITE (L_WORD)\r | |
202 | #define WRITEB (L_BYTE)\r | |
203 | \r | |
204 | /* Common CSI flags */\r | |
205 | \r | |
206 | #define CSR_V_GO 0 /* go */\r | |
207 | #define CSR_V_IE 6 /* interrupt enable */\r | |
208 | #define CSR_V_DONE 7 /* done */\r | |
209 | #define CSR_V_BUSY 11 /* busy */\r | |
210 | #define CSR_V_ERR 15 /* error */\r | |
211 | #define CSR_GO (1u << CSR_V_GO)\r | |
212 | #define CSR_IE (1u << CSR_V_IE)\r | |
213 | #define CSR_DONE (1u << CSR_V_DONE)\r | |
214 | #define CSR_BUSY (1u << CSR_V_BUSY)\r | |
215 | #define CSR_ERR (1u << CSR_V_ERR)\r | |
216 | \r | |
217 | /* Timers */\r | |
218 | \r | |
219 | #define TMR_CLK 0 /* 100Hz clock */\r | |
220 | \r | |
221 | /* I/O system definitions */\r | |
222 | \r | |
223 | #define DZ_MUXES 4 /* max # of DZV muxes */\r | |
224 | #define DZ_LINES 8 /* lines per DZV mux */\r | |
225 | #define VH_MUXES 4 /* max # of DHQ muxes */\r | |
226 | #define MT_MAXFR (1 << 16) /* magtape max rec */\r | |
227 | \r | |
228 | #define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */\r | |
229 | #define DEV_V_MBUS (DEV_V_UF + 1) /* Massbus */\r | |
230 | #define DEV_V_NEXUS (DEV_V_UF + 2) /* Nexus */\r | |
231 | #define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */\r | |
232 | #define DEV_V_FFUF (DEV_V_UF + 4) /* first free flag */\r | |
233 | #define DEV_UBUS (1u << DEV_V_UBUS)\r | |
234 | #define DEV_MBUS (1u << DEV_V_MBUS)\r | |
235 | #define DEV_NEXUS (1u << DEV_V_NEXUS)\r | |
236 | #define DEV_FLTA (1u << DEV_V_FLTA)\r | |
237 | #define DEV_QBUS (0)\r | |
238 | #define DEV_Q18 (0)\r | |
239 | \r | |
240 | #define UNIBUS TRUE /* Unibus only */\r | |
241 | \r | |
242 | #define DEV_RDX 16 /* default device radix */\r | |
243 | \r | |
244 | /* Device information block \r | |
245 | \r | |
246 | For Massbus devices,\r | |
247 | ba = Massbus number\r | |
248 | lnt = Massbus ctrl type\r | |
249 | ack[0] = abort routine\r | |
250 | \r | |
251 | For Nexus devices,\r | |
252 | ba = Nexus number\r | |
253 | lnt = number of consecutive nexi */\r | |
254 | \r | |
255 | #define VEC_DEVMAX 4 /* max device vec */\r | |
256 | \r | |
257 | typedef struct {\r | |
258 | uint32 ba; /* base addr */\r | |
259 | uint32 lnt; /* length */\r | |
260 | t_stat (*rd)(int32 *dat, int32 ad, int32 md);\r | |
261 | t_stat (*wr)(int32 dat, int32 ad, int32 md);\r | |
262 | int32 vnum; /* vectors: number */\r | |
263 | int32 vloc; /* locator */\r | |
264 | int32 vec; /* value */\r | |
265 | int32 (*ack[VEC_DEVMAX])(void); /* ack routine */\r | |
266 | } DIB;\r | |
267 | \r | |
268 | /* Unibus I/O page layout - XUB,RQB,RQC,RQD float based on number of DZ's\r | |
269 | Massbus devices (RP, TU) do not appear in the Unibus IO page */\r | |
270 | \r | |
271 | #define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */\r | |
272 | #define IOLN_DZ 010\r | |
273 | #define IOBA_XUB (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2)))\r | |
274 | #define IOLN_XUB 010\r | |
275 | #define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2)))\r | |
276 | #define IOLN_RQB 004\r | |
277 | #define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB)\r | |
278 | #define IOLN_RQC 004\r | |
279 | #define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC)\r | |
280 | #define IOLN_RQD 004\r | |
281 | #define IOBA_RQ (IOPAGEBASE + 012150) /* UDA50 */\r | |
282 | #define IOLN_RQ 004\r | |
283 | #define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */\r | |
284 | #define IOLN_TS 004\r | |
285 | #define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */\r | |
286 | #define IOLN_RL 012\r | |
287 | #define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */\r | |
288 | #define IOLN_XQ 020\r | |
289 | #define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */\r | |
290 | #define IOLN_XQB 020\r | |
291 | #define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */\r | |
292 | #define IOLN_TQ 004\r | |
293 | #define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */\r | |
294 | #define IOLN_XU 010\r | |
295 | #define IOBA_CR (IOPAGEBASE + 017160) /* CD/CR/CM */\r | |
296 | #define IOLN_CR 010\r | |
297 | #define IOBA_RX (IOPAGEBASE + 017170) /* RX11 */\r | |
298 | #define IOLN_RX 004\r | |
299 | #define IOBA_RY (IOPAGEBASE + 017170) /* RXV21 */\r | |
300 | #define IOLN_RY 004\r | |
301 | #define IOBA_QDSS (IOPAGEBASE + 017400) /* QDSS */\r | |
302 | #define IOLN_QDSS 002\r | |
303 | #define IOBA_HK (IOPAGEBASE + 017440) /* RK611 */\r | |
304 | #define IOLN_HK 040\r | |
305 | #define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */\r | |
306 | #define IOLN_LPT 004\r | |
307 | #define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */\r | |
308 | #define IOLN_PTR 004\r | |
309 | #define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */\r | |
310 | #define IOLN_PTP 004\r | |
311 | \r | |
312 | /* Interrupt assignments; within each level, priority is right to left */\r | |
313 | \r | |
314 | #define INT_V_DZRX 0 /* BR5 */\r | |
315 | #define INT_V_DZTX 1\r | |
316 | #define INT_V_HK 2\r | |
317 | #define INT_V_RL 3\r | |
318 | #define INT_V_RQ 4\r | |
319 | #define INT_V_TQ 5\r | |
320 | #define INT_V_TS 6\r | |
321 | #define INT_V_RY 7\r | |
322 | #define INT_V_XU 8\r | |
323 | \r | |
324 | #define INT_V_LPT 0 /* BR4 */\r | |
325 | #define INT_V_PTR 1\r | |
326 | #define INT_V_PTP 2\r | |
327 | #define INT_V_CR 3\r | |
328 | \r | |
329 | #define INT_DZRX (1u << INT_V_DZRX)\r | |
330 | #define INT_DZTX (1u << INT_V_DZTX)\r | |
331 | #define INT_HK (1u << INT_V_HK)\r | |
332 | #define INT_RL (1u << INT_V_RL)\r | |
333 | #define INT_RQ (1u << INT_V_RQ)\r | |
334 | #define INT_TQ (1u << INT_V_TQ)\r | |
335 | #define INT_TS (1u << INT_V_TS)\r | |
336 | #define INT_RY (1u << INT_V_RY)\r | |
337 | #define INT_XU (1u << INT_V_XU)\r | |
338 | #define INT_LPT (1u << INT_V_LPT)\r | |
339 | #define INT_PTR (1u << INT_V_PTR)\r | |
340 | #define INT_PTP (1u << INT_V_PTP)\r | |
341 | #define INT_CR (1u << INT_V_CR)\r | |
342 | \r | |
343 | #define IPL_DZRX (0x15 - IPL_HMIN)\r | |
344 | #define IPL_DZTX (0x15 - IPL_HMIN)\r | |
345 | #define IPL_HK (0x15 - IPL_HMIN)\r | |
346 | #define IPL_RL (0x15 - IPL_HMIN)\r | |
347 | #define IPL_RQ (0x15 - IPL_HMIN)\r | |
348 | #define IPL_TQ (0x15 - IPL_HMIN)\r | |
349 | #define IPL_TS (0x15 - IPL_HMIN)\r | |
350 | #define IPL_RY (0x15 - IPL_HMIN)\r | |
351 | #define IPL_XU (0x15 - IPL_HMIN)\r | |
352 | #define IPL_LPT (0x14 - IPL_HMIN)\r | |
353 | #define IPL_PTR (0x14 - IPL_HMIN)\r | |
354 | #define IPL_PTP (0x14 - IPL_HMIN)\r | |
355 | #define IPL_CR (0x14 - IPL_HMIN)\r | |
356 | \r | |
357 | /* Device vectors */\r | |
358 | \r | |
359 | #define VEC_Q 0000\r | |
360 | #define VEC_PTR 0070\r | |
361 | #define VEC_PTP 0074\r | |
362 | #define VEC_XQ 0120\r | |
363 | #define VEC_XU 0120\r | |
364 | #define VEC_RQ 0154\r | |
365 | #define VEC_RL 0160\r | |
366 | #define VEC_LPT 0200\r | |
367 | #define VEC_HK 0210\r | |
368 | #define VEC_TS 0224\r | |
369 | #define VEC_CR 0230\r | |
370 | #define VEC_TQ 0260\r | |
371 | #define VEC_RX 0264\r | |
372 | #define VEC_RY 0264\r | |
373 | #define VEC_DZRX 0300\r | |
374 | #define VEC_DZTX 0304\r | |
375 | \r | |
376 | /* Interrupt macros */\r | |
377 | \r | |
378 | #define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv)\r | |
379 | #define NVCL(dv) ((IPL_##dv * 32) + TR_##dv)\r | |
380 | #define IREQ(dv) int_req[IPL_##dv]\r | |
381 | #define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)\r | |
382 | #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)\r | |
383 | #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */\r | |
384 | \r | |
385 | /* Logging */\r | |
386 | \r | |
387 | #define LOG_CPU_I 0x1 /* intexc */\r | |
388 | #define LOG_CPU_R 0x2 /* REI */\r | |
389 | #define LOG_CPU_P 0x4 /* context */\r | |
390 | \r | |
391 | /* Massbus definitions */\r | |
392 | \r | |
393 | #define MBA_RP (TR_MBA0 - TR_MBA0) /* MBA for RP */\r | |
394 | #define MBA_TU (TR_MBA1 - TR_MBA0) /* MBA for TU */\r | |
395 | #define MBA_RMASK 0x1F /* max 32 reg */\r | |
396 | #define MBE_NXD 1 /* nx drive */\r | |
397 | #define MBE_NXR 2 /* nx reg */\r | |
398 | #define MBE_GOE 3 /* err on GO */\r | |
399 | \r | |
400 | /* Boot definitions */\r | |
401 | \r | |
402 | #define BOOT_MB 0 /* device codes */\r | |
403 | #define BOOT_HK 1 /* for VMB */\r | |
404 | #define BOOT_RL 2\r | |
405 | #define BOOT_UDA 17\r | |
406 | #define BOOT_TK 18\r | |
407 | \r | |
408 | /* Function prototypes for virtual memory interface */\r | |
409 | \r | |
410 | int32 Read (uint32 va, int32 lnt, int32 acc);\r | |
411 | void Write (uint32 va, int32 val, int32 lnt, int32 acc);\r | |
412 | \r | |
413 | /* Function prototypes for physical memory interface (inlined) */\r | |
414 | \r | |
415 | SIM_INLINE_GCC int32 ReadB (uint32 pa);\r | |
416 | SIM_INLINE_GCC int32 ReadW (uint32 pa);\r | |
417 | SIM_INLINE_GCC int32 ReadL (uint32 pa);\r | |
418 | SIM_INLINE_GCC int32 ReadLP (uint32 pa);\r | |
419 | SIM_INLINE_GCC void WriteB (uint32 pa, int32 val);\r | |
420 | SIM_INLINE_GCC void WriteW (uint32 pa, int32 val);\r | |
421 | SIM_INLINE_GCC void WriteL (uint32 pa, int32 val);\r | |
422 | void WriteLP (uint32 pa, int32 val);\r | |
423 | \r | |
424 | /* Function prototypes for I/O */\r | |
425 | \r | |
426 | int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);\r | |
427 | int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);\r | |
428 | int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf);\r | |
429 | int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf);\r | |
430 | \r | |
431 | t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
432 | t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
433 | t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
434 | t_stat set_vec (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
435 | t_stat show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
436 | t_stat auto_config (char *name, int32 num);\r | |
437 | \r | |
438 | int32 mba_rdbufW (uint32 mbus, int32 bc, uint16 *buf);\r | |
439 | int32 mba_wrbufW (uint32 mbus, int32 bc, uint16 *buf);\r | |
440 | int32 mba_chbufW (uint32 mbus, int32 bc, uint16 *buf);\r | |
441 | int32 mba_get_bc (uint32 mbus);\r | |
442 | void mba_upd_ata (uint32 mbus, uint32 val);\r | |
443 | void mba_set_exc (uint32 mbus);\r | |
444 | void mba_set_don (uint32 mbus);\r | |
445 | void mba_set_enbdis (uint32 mbus, t_bool dis);\r | |
446 | t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
447 | \r | |
448 | t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
449 | \r | |
450 | void sbi_set_errcnf (void);\r | |
451 | int32 clk_cosched (int32 wait);\r | |
452 | \r | |
453 | #endif\r |