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1 | /* vax_cmode.c: VAX compatibility mode\r |
2 | \r | |
3 | Copyright (c) 2004-2008, Robert M Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | On a full VAX, this module implements PDP-11 compatibility mode.\r | |
27 | On a subset VAX, this module forces a fault if REI attempts to set PSL<cm>.\r | |
28 | \r | |
29 | 28-May-08 RMS Inlined physical memory routines\r | |
30 | 25-Jan-08 RMS Fixed declaration (from Mark Pizzolato)\r | |
31 | 03-May-06 RMS Fixed omission of SXT\r | |
32 | Fixed order of operand fetching in XOR\r | |
33 | 24-Aug-04 RMS Cloned from PDP-11 CPU\r | |
34 | \r | |
35 | In compatibility mode, the Istream prefetch mechanism is not used. The\r | |
36 | prefetcher will be explicitly resynchronized through intexc on any exit\r | |
37 | from compatibility mode.\r | |
38 | */\r | |
39 | \r | |
40 | #include "vax_defs.h"\r | |
41 | \r | |
42 | #if defined (FULL_VAX)\r | |
43 | \r | |
44 | #define RdMemB(a) Read (a, L_BYTE, RA)\r | |
45 | #define RdMemMB(a) Read (a, L_BYTE, WA)\r | |
46 | #define WrMemB(d,a) Write (a, d, L_BYTE, WA)\r | |
47 | #define BRANCH_F(x) CMODE_JUMP ((PC + (((x) + (x)) & BMASK)) & WMASK)\r | |
48 | #define BRANCH_B(x) CMODE_JUMP ((PC + (((x) + (x)) | 0177400)) & WMASK)\r | |
49 | #define CC_XOR_NV(x) ((((x) & CC_N) != 0) ^ (((x) & CC_V) != 0))\r | |
50 | #define CC_XOR_NC(x) ((((x) & CC_N) != 0) ^ (((x) & CC_C) != 0))\r | |
51 | \r | |
52 | extern int32 R[16];\r | |
53 | extern int32 PSL;\r | |
54 | extern int32 trpirq;\r | |
55 | extern int32 p1;\r | |
56 | extern int32 fault_PC;\r | |
57 | extern int32 recq[]; /* recovery queue */\r | |
58 | extern int32 recqptr; /* recq pointer */\r | |
59 | extern int32 pcq[];\r | |
60 | extern int32 pcq_p;\r | |
61 | extern int32 ibcnt, ppc;\r | |
62 | extern int32 sim_interval;\r | |
63 | extern uint32 sim_brk_summ;\r | |
64 | extern jmp_buf save_env;\r | |
65 | \r | |
66 | int32 GeteaB (int32 spec);\r | |
67 | int32 GeteaW (int32 spec);\r | |
68 | int32 RdMemW (int32 a);\r | |
69 | int32 RdMemMW (int32 a);\r | |
70 | void WrMemW (int32 d, int32 a);\r | |
71 | int32 RdRegB (int32 rn);\r | |
72 | int32 RdRegW (int32 rn);\r | |
73 | void WrRegB (int32 val, int32 rn);\r | |
74 | void WrRegW (int32 val, int32 rn);\r | |
75 | \r | |
76 | /* Validate PSL for compatibility mode */\r | |
77 | \r | |
78 | t_bool BadCmPSL (int32 newpsl)\r | |
79 | {\r | |
80 | if ((newpsl & (PSL_FPD|PSL_IS|PSL_CUR|PSL_PRV|PSL_IPL)) !=\r | |
81 | ((USER << PSL_V_CUR) | (USER << PSL_V_PRV)))\r | |
82 | return TRUE;\r | |
83 | else return FALSE;\r | |
84 | }\r | |
85 | \r | |
86 | /* Compatibility mode execution */\r | |
87 | \r | |
88 | int32 op_cmode (int32 cc)\r | |
89 | {\r | |
90 | int32 IR, srcspec, dstspec, srcreg, dstreg, ea;\r | |
91 | int32 i, t, src, src2, dst, sign, oc;\r | |
92 | int32 acc = ACC_MASK (USER);\r | |
93 | \r | |
94 | PC = PC & WMASK; /* PC must be 16b */\r | |
95 | if (sim_brk_summ && sim_brk_test (PC, SWMASK ('E'))) { /* breakpoint? */\r | |
96 | ABORT (STOP_IBKPT); /* stop simulation */\r | |
97 | }\r | |
98 | sim_interval = sim_interval - 1; /* count instr */\r | |
99 | \r | |
100 | IR = RdMemW (PC); /* fetch instruction */\r | |
101 | PC = (PC + 2) & WMASK; /* incr PC, mod 65k */\r | |
102 | srcspec = (IR >> 6) & 077; /* src, dst specs */\r | |
103 | dstspec = IR & 077;\r | |
104 | srcreg = (srcspec <= 07); /* src, dst = rmode? */\r | |
105 | dstreg = (dstspec <= 07);\r | |
106 | switch ((IR >> 12) & 017) { /* decode IR<15:12> */\r | |
107 | \r | |
108 | /* Opcode 0: no operands, specials, branches, JSR, SOPs */\r | |
109 | \r | |
110 | case 000: /* 00xxxx */\r | |
111 | switch ((IR >> 6) & 077) { /* decode IR<11:6> */\r | |
112 | case 000: /* 0000xx */\r | |
113 | switch (IR) { /* decode IR<5:0> */\r | |
114 | case 3: /* BPT */\r | |
115 | CMODE_FAULT (CMODE_BPT);\r | |
116 | break;\r | |
117 | \r | |
118 | case 4: /* IOT */\r | |
119 | CMODE_FAULT (CMODE_IOT);\r | |
120 | break;\r | |
121 | \r | |
122 | case 2: /* RTI */\r | |
123 | case 6: /* RTT */\r | |
124 | src = RdMemW (R[6] & WMASK); /* new PC */\r | |
125 | src2 = RdMemW ((R[6] + 2) & WMASK); /* new PSW */\r | |
126 | R[6] = (R[6] + 4) & WMASK;\r | |
127 | cc = src2 & CC_MASK; /* update cc, T */\r | |
128 | if (src2 & PSW_T) PSL = PSL | PSW_T;\r | |
129 | else PSL = PSL & ~PSW_T;\r | |
130 | CMODE_JUMP (src); /* update PC */\r | |
131 | break;\r | |
132 | \r | |
133 | default: /* undefined */\r | |
134 | CMODE_FAULT (CMODE_RSVI);\r | |
135 | break;\r | |
136 | } /* end switch IR */\r | |
137 | break; /* end case 0000xx */\r | |
138 | \r | |
139 | case 001: /* JMP */\r | |
140 | if (dstreg) CMODE_FAULT (CMODE_ILLI); /* mode 0 illegal */\r | |
141 | else { CMODE_JUMP (GeteaW (dstspec)); }\r | |
142 | break;\r | |
143 | \r | |
144 | case 002: /* 0002xx */\r | |
145 | if (IR < 000210) { /* RTS */\r | |
146 | dstspec = dstspec & 07;\r | |
147 | if (dstspec != 7) { /* PC <- r */\r | |
148 | CMODE_JUMP (RdRegW (dstspec));\r | |
149 | }\r | |
150 | dst = RdMemW (R[6]); /* t <- (sp)+ */\r | |
151 | R[6] = (R[6] + 2) & WMASK;\r | |
152 | WrRegW (dst, dstspec); /* r <- t */\r | |
153 | break; /* end if RTS */\r | |
154 | }\r | |
155 | if (IR < 000240) { /* [210:237] */\r | |
156 | CMODE_FAULT (CMODE_RSVI);\r | |
157 | break;\r | |
158 | }\r | |
159 | if (IR < 000260) cc = cc & ~(IR & CC_MASK); /* clear CC */\r | |
160 | else cc = cc | (IR & CC_MASK); /* set CC */\r | |
161 | break;\r | |
162 | \r | |
163 | case 003: /* SWAB */\r | |
164 | if (dstreg) src = RdRegW (dstspec);\r | |
165 | else src = RdMemMW (ea = GeteaW (dstspec));\r | |
166 | dst = ((src & BMASK) << 8) | ((src >> 8) & BMASK);\r | |
167 | if (dstreg) WrRegW (dst, dstspec);\r | |
168 | else WrMemW (dst, ea);\r | |
169 | CC_IIZZ_B ((dst & BMASK));\r | |
170 | break;\r | |
171 | \r | |
172 | case 004: case 005: /* BR */\r | |
173 | BRANCH_F (IR);\r | |
174 | break;\r | |
175 | \r | |
176 | case 006: case 007: /* BR */\r | |
177 | BRANCH_B (IR);\r | |
178 | break;\r | |
179 | \r | |
180 | case 010: case 011: /* BNE */\r | |
181 | if ((cc & CC_Z) == 0) { BRANCH_F (IR); } \r | |
182 | break;\r | |
183 | \r | |
184 | case 012: case 013: /* BNE */\r | |
185 | if ((cc & CC_Z) == 0) { BRANCH_B (IR); }\r | |
186 | break;\r | |
187 | \r | |
188 | case 014: case 015: /* BEQ */\r | |
189 | if (cc & CC_Z) { BRANCH_F (IR); } \r | |
190 | break;\r | |
191 | \r | |
192 | case 016: case 017: /* BEQ */\r | |
193 | if (cc & CC_Z) { BRANCH_B (IR); }\r | |
194 | break;\r | |
195 | \r | |
196 | case 020: case 021: /* BGE */\r | |
197 | if (CC_XOR_NV (cc) == 0) { BRANCH_F (IR); } \r | |
198 | break;\r | |
199 | \r | |
200 | case 022: case 023: /* BGE */\r | |
201 | if (CC_XOR_NV (cc) == 0) { BRANCH_B (IR); }\r | |
202 | break;\r | |
203 | \r | |
204 | case 024: case 025: /* BLT */\r | |
205 | if (CC_XOR_NV (cc)) { BRANCH_F (IR); }\r | |
206 | break;\r | |
207 | \r | |
208 | case 026: case 027: /* BLT */\r | |
209 | if (CC_XOR_NV (cc)) { BRANCH_B (IR); }\r | |
210 | break;\r | |
211 | \r | |
212 | case 030: case 031: /* BGT */\r | |
213 | if (((cc & CC_Z) || CC_XOR_NV (cc)) == 0) { BRANCH_F (IR); } \r | |
214 | break;\r | |
215 | \r | |
216 | case 032: case 033: /* BGT */\r | |
217 | if (((cc & CC_Z) || CC_XOR_NV (cc)) == 0) { BRANCH_B (IR); }\r | |
218 | break;\r | |
219 | \r | |
220 | case 034: case 035: /* BLE */\r | |
221 | if ((cc & CC_Z) || CC_XOR_NV (cc)) { BRANCH_F (IR); } \r | |
222 | break;\r | |
223 | \r | |
224 | case 036: case 037: /* BLE */\r | |
225 | if ((cc & CC_Z) || CC_XOR_NV (cc)) { BRANCH_B (IR); }\r | |
226 | break;\r | |
227 | \r | |
228 | case 040: case 041: case 042: case 043: /* JSR */\r | |
229 | case 044: case 045: case 046: case 047:\r | |
230 | if (dstreg) CMODE_FAULT (CMODE_ILLI); /* mode 0 illegal */\r | |
231 | else {\r | |
232 | srcspec = srcspec & 07; /* get reg num */\r | |
233 | dst = GeteaW (dstspec); /* get dst addr */\r | |
234 | src = RdRegW (srcspec); /* get src reg */\r | |
235 | WrMemW (src, (R[6] - 2) & WMASK); /* -(sp) <- r */\r | |
236 | R[6] = (R[6] - 2) & WMASK;\r | |
237 | if (srcspec != 7) WrRegW (PC, srcspec); /* r <- PC */\r | |
238 | CMODE_JUMP (dst); /* PC <- dst */\r | |
239 | }\r | |
240 | break; /* end JSR */\r | |
241 | \r | |
242 | case 050: /* CLR */\r | |
243 | if (dstreg) WrRegW (0, dstspec);\r | |
244 | else WrMemW (0, GeteaW (dstspec));\r | |
245 | cc = CC_Z;\r | |
246 | break;\r | |
247 | \r | |
248 | case 051: /* COM */\r | |
249 | if (dstreg) src = RdRegW (dstspec);\r | |
250 | else src = RdMemMW (ea = GeteaW (dstspec));\r | |
251 | dst = src ^ WMASK;\r | |
252 | if (dstreg) WrRegW (dst, dstspec);\r | |
253 | else WrMemW (dst, ea);\r | |
254 | CC_IIZZ_W (dst);\r | |
255 | cc = cc | CC_C;\r | |
256 | break;\r | |
257 | \r | |
258 | case 052: /* INC */\r | |
259 | if (dstreg) src = RdRegW (dstspec);\r | |
260 | else src = RdMemMW (ea = GeteaW (dstspec));\r | |
261 | dst = (src + 1) & WMASK;\r | |
262 | if (dstreg) WrRegW (dst, dstspec);\r | |
263 | else WrMemW (dst, ea);\r | |
264 | CC_IIZP_W (dst);\r | |
265 | if (dst == 0100000) cc = cc | CC_V;\r | |
266 | break;\r | |
267 | \r | |
268 | case 053: /* DEC */\r | |
269 | if (dstreg) src = RdRegW (dstspec);\r | |
270 | else src = RdMemMW (ea = GeteaW (dstspec));\r | |
271 | dst = (src - 1) & WMASK;\r | |
272 | if (dstreg) WrRegW (dst, dstspec);\r | |
273 | else WrMemW (dst, ea);\r | |
274 | CC_IIZP_W (dst);\r | |
275 | if (dst == 077777) cc = cc | CC_V;\r | |
276 | break;\r | |
277 | \r | |
278 | case 054: /* NEG */\r | |
279 | if (dstreg) src = RdRegW (dstspec);\r | |
280 | else src = RdMemMW (ea = GeteaW (dstspec));\r | |
281 | dst = (-src) & WMASK;\r | |
282 | if (dstreg) WrRegW (dst, dstspec);\r | |
283 | else WrMemW (dst, ea);\r | |
284 | CC_IIZZ_W (dst);\r | |
285 | if (dst == 0100000) cc = cc | CC_V;\r | |
286 | if (dst) cc = cc | CC_C;\r | |
287 | break;\r | |
288 | \r | |
289 | case 055: /* ADC */\r | |
290 | if (dstreg) src = RdRegW (dstspec);\r | |
291 | else src = RdMemMW (ea = GeteaW (dstspec));\r | |
292 | dst = (src + (cc & CC_C)) & WMASK;\r | |
293 | if (dstreg) WrRegW (dst, dstspec);\r | |
294 | else WrMemW (dst, ea);\r | |
295 | CC_IIZZ_W (dst);\r | |
296 | if ((src == 077777) && (dst == 0100000)) cc = cc | CC_V;\r | |
297 | if ((src == 0177777) && (dst == 0)) cc = cc | CC_C;\r | |
298 | break;\r | |
299 | \r | |
300 | case 056: /* SBC */\r | |
301 | if (dstreg) src = RdRegW (dstspec);\r | |
302 | else src = RdMemMW (ea = GeteaW (dstspec));\r | |
303 | dst = (src - (cc & CC_C)) & WMASK;\r | |
304 | if (dstreg) WrRegW (dst, dstspec);\r | |
305 | else WrMemW (dst, ea);\r | |
306 | CC_IIZZ_W (dst);\r | |
307 | if ((src == 0100000) && (dst == 077777)) cc = cc | CC_V;\r | |
308 | if ((src == 0) && (dst == 0177777)) cc = cc | CC_C;\r | |
309 | break;\r | |
310 | \r | |
311 | case 057: /* TST */\r | |
312 | if (dstreg) src = RdRegW (dstspec);\r | |
313 | else src = RdMemW (GeteaW (dstspec));\r | |
314 | CC_IIZZ_W (src);\r | |
315 | break;\r | |
316 | \r | |
317 | case 060: /* ROR */\r | |
318 | if (dstreg) src = RdRegW (dstspec);\r | |
319 | else src = RdMemMW (ea = GeteaW (dstspec));\r | |
320 | dst = (src >> 1) | ((cc & CC_C)? WSIGN: 0);\r | |
321 | if (dstreg) WrRegW (dst, dstspec);\r | |
322 | else WrMemW (dst, ea);\r | |
323 | CC_IIZZ_W (dst);\r | |
324 | if (src & 1) cc = cc | CC_C;\r | |
325 | if (CC_XOR_NC (cc)) cc = cc | CC_V;\r | |
326 | break;\r | |
327 | \r | |
328 | case 061: /* ROL */\r | |
329 | if (dstreg) src = RdRegW (dstspec);\r | |
330 | else src = RdMemMW (ea = GeteaW (dstspec));\r | |
331 | dst = ((src << 1) | ((cc & CC_C)? 1: 0)) & WMASK;\r | |
332 | if (dstreg) WrRegW (dst, dstspec);\r | |
333 | else WrMemW (dst, ea);\r | |
334 | CC_IIZZ_W (dst);\r | |
335 | if (src & WSIGN) cc = cc | CC_C;\r | |
336 | if (CC_XOR_NC (cc)) cc = cc | CC_V;\r | |
337 | break;\r | |
338 | \r | |
339 | case 062: /* ASR */\r | |
340 | if (dstreg) src = RdRegW (dstspec);\r | |
341 | else src = RdMemMW (ea = GeteaW (dstspec));\r | |
342 | dst = (src & WSIGN) | (src >> 1);\r | |
343 | if (dstreg) WrRegW (dst, dstspec);\r | |
344 | else WrMemW (dst, ea);\r | |
345 | CC_IIZZ_W (dst);\r | |
346 | if (src & 1) cc = cc | CC_C;\r | |
347 | if (CC_XOR_NC (cc)) cc = cc | CC_V;\r | |
348 | break;\r | |
349 | \r | |
350 | case 063: /* ASL */\r | |
351 | if (dstreg) src = RdRegW (dstspec);\r | |
352 | else src = RdMemMW (ea = GeteaW (dstspec));\r | |
353 | dst = (src << 1) & WMASK;\r | |
354 | if (dstreg) WrRegW (dst, dstspec);\r | |
355 | else WrMemW (dst, ea);\r | |
356 | CC_IIZZ_W (dst);\r | |
357 | if (src & WSIGN) cc = cc | CC_C;\r | |
358 | if (CC_XOR_NC (cc)) cc = cc | CC_V;\r | |
359 | break;\r | |
360 | \r | |
361 | case 065: /* MFPI */\r | |
362 | if (dstreg) dst = RdRegW (dstspec); /* "mov dst,-(sp)" */\r | |
363 | else dst = RdMemW (GeteaW (dstspec));\r | |
364 | WrMemW (dst, (R[6] - 2) & WMASK);\r | |
365 | R[6] = (R[6] - 2) & WMASK;\r | |
366 | CC_IIZP_W (dst);\r | |
367 | break;\r | |
368 | \r | |
369 | case 066: /* MTPI */\r | |
370 | dst = RdMemW (R[6] & WMASK); /* "mov (sp)+,dst" */\r | |
371 | R[6] = (R[6] + 2) & WMASK;\r | |
372 | recq[recqptr++] = RQ_REC (AIN|RW, 6);\r | |
373 | if (dstreg) WrRegW (dst, dstspec);\r | |
374 | else WrMemW (dst, (GeteaW (dstspec) & WMASK));\r | |
375 | CC_IIZP_W (dst);\r | |
376 | break;\r | |
377 | \r | |
378 | case 067: /* SXT */\r | |
379 | dst = (cc & CC_N)? 0177777: 0;\r | |
380 | if (dstreg) WrRegW (dst, dstspec);\r | |
381 | else WrMemW (dst, GeteaW (dstspec));\r | |
382 | CC_IIZP_W (dst);\r | |
383 | break;\r | |
384 | \r | |
385 | default: /* undefined */\r | |
386 | CMODE_FAULT (CMODE_RSVI);\r | |
387 | break;\r | |
388 | } /* end switch SOPs */\r | |
389 | break; /* end case 000 */\r | |
390 | \r | |
391 | /* Opcodes 01 - 06: double operand word instructions\r | |
392 | \r | |
393 | Compatibility mode requires source address decode, source fetch,\r | |
394 | dest address decode, dest fetch/store.\r | |
395 | \r | |
396 | Add: v = [sign (src) = sign (src2)] and [sign (src) != sign (result)]\r | |
397 | Cmp: v = [sign (src) != sign (src2)] and [sign (src2) = sign (result)]\r | |
398 | */\r | |
399 | \r | |
400 | case 001: /* MOV */\r | |
401 | if (srcreg) src = RdRegW (srcspec);\r | |
402 | else src = RdMemW (GeteaW (srcspec));\r | |
403 | if (dstreg) WrRegW (src, dstspec);\r | |
404 | else WrMemW (src, GeteaW (dstspec));\r | |
405 | CC_IIZP_W (src);\r | |
406 | break;\r | |
407 | \r | |
408 | case 002: /* CMP */\r | |
409 | if (srcreg) src = RdRegW (srcspec);\r | |
410 | else src = RdMemW (GeteaW (srcspec));\r | |
411 | if (dstreg) src2 = RdRegW (dstspec);\r | |
412 | else src2 = RdMemW (GeteaW (dstspec));\r | |
413 | dst = (src - src2) & WMASK;\r | |
414 | CC_IIZZ_W (dst);\r | |
415 | if (((src ^ src2) & (~src2 ^ dst)) & WSIGN) cc = cc | CC_V;\r | |
416 | if (src < src2) cc = cc | CC_C;\r | |
417 | break;\r | |
418 | \r | |
419 | case 003: /* BIT */\r | |
420 | if (srcreg) src = RdRegW (srcspec);\r | |
421 | else src = RdMemW (GeteaW (srcspec));\r | |
422 | if (dstreg) src2 = RdRegW (dstspec);\r | |
423 | else src2 = RdMemW (GeteaW (dstspec));\r | |
424 | dst = src2 & src;\r | |
425 | CC_IIZP_W (dst);\r | |
426 | break;\r | |
427 | \r | |
428 | case 004: /* BIC */\r | |
429 | if (srcreg) src = RdRegW (srcspec);\r | |
430 | else src = RdMemW (GeteaW (srcspec));\r | |
431 | if (dstreg) src2 = RdRegW (dstspec);\r | |
432 | else src2 = RdMemMW (ea = GeteaW (dstspec));\r | |
433 | dst = src2 & ~src;\r | |
434 | if (dstreg) WrRegW (dst, dstspec);\r | |
435 | else WrMemW (dst, ea);\r | |
436 | CC_IIZP_W (dst);\r | |
437 | break;\r | |
438 | \r | |
439 | case 005: /* BIS */\r | |
440 | if (srcreg) src = RdRegW (srcspec);\r | |
441 | else src = RdMemW (GeteaW (srcspec));\r | |
442 | if (dstreg) src2 = RdRegW (dstspec);\r | |
443 | else src2 = RdMemMW (ea = GeteaW (dstspec));\r | |
444 | dst = src2 | src;\r | |
445 | if (dstreg) WrRegW (dst, dstspec);\r | |
446 | else WrMemW (dst, ea);\r | |
447 | CC_IIZP_W (dst);\r | |
448 | break;\r | |
449 | \r | |
450 | case 006: /* ADD */\r | |
451 | if (srcreg) src = RdRegW (srcspec);\r | |
452 | else src = RdMemW (GeteaW (srcspec));\r | |
453 | if (dstreg) src2 = RdRegW (dstspec);\r | |
454 | else src2 = RdMemMW (ea = GeteaW (dstspec));\r | |
455 | dst = (src2 + src) & WMASK;\r | |
456 | if (dstreg) WrRegW (dst, dstspec);\r | |
457 | else WrMemW (dst, ea);\r | |
458 | CC_ADD_W (dst, src, src2);\r | |
459 | break;\r | |
460 | \r | |
461 | /* Opcode 07: EIS, FIS (not implemented), CIS\r | |
462 | \r | |
463 | Notes:\r | |
464 | - MUL carry: C is set if the (signed) result doesn't fit in 16 bits.\r | |
465 | - Divide has three error cases:\r | |
466 | 1. Divide by zero.\r | |
467 | 2. Divide largest negative number by -1.\r | |
468 | 3. (Signed) quotient doesn't fit in 16 bits.\r | |
469 | Cases 1 and 2 must be tested in advance, to avoid C runtime errors.\r | |
470 | - ASHx left: overflow if the bits shifted out do not equal the sign\r | |
471 | of the result (convert shift out to 1/0, xor against sign).\r | |
472 | - ASHx right: if right shift sign extends, then the shift and\r | |
473 | conditional or of shifted -1 is redundant. If right shift zero\r | |
474 | extends, then the shift and conditional or does sign extension.\r | |
475 | */\r | |
476 | \r | |
477 | case 007: /* EIS */\r | |
478 | srcspec = srcspec & 07; /* get src reg */\r | |
479 | switch ((IR >> 9) & 07) { /* decode IR<11:9> */\r | |
480 | \r | |
481 | case 0: /* MUL */\r | |
482 | if (dstreg) src2 = RdRegW (dstspec); /* get src2 */\r | |
483 | else src2 = RdMemW (GeteaW (dstspec));\r | |
484 | src = RdRegW (srcspec); /* get src */\r | |
485 | if (src2 & WSIGN) src2 = src2 | ~WMASK; /* sext src, src2 */\r | |
486 | if (src & WSIGN) src = src | ~WMASK;\r | |
487 | dst = src * src2; /* multiply */\r | |
488 | WrRegW ((dst >> 16) & WMASK, srcspec); /* high 16b */\r | |
489 | WrRegW (dst & WMASK, srcspec | 1); /* low 16b */\r | |
490 | CC_IIZZ_L (dst & LMASK);\r | |
491 | if ((dst > 077777) || (dst < -0100000)) cc = cc | CC_C;\r | |
492 | break;\r | |
493 | \r | |
494 | case 1: /* DIV */\r | |
495 | if (dstreg) src2 = RdRegW (dstspec); /* get src2 */\r | |
496 | else src2 = RdMemW (GeteaW (dstspec));\r | |
497 | t = RdRegW (srcspec);\r | |
498 | src = (((uint32) t) << 16) | RdRegW (srcspec | 1);\r | |
499 | if (src2 == 0) { /* div by 0? */\r | |
500 | cc = CC_V | CC_C; /* set cc's */\r | |
501 | break; /* done */\r | |
502 | }\r | |
503 | if ((src == LSIGN) && (src2 == WMASK)) { /* -2^31 / -1? */\r | |
504 | cc = CC_V; /* overflow */\r | |
505 | break; /* done */\r | |
506 | }\r | |
507 | if (src2 & WSIGN) src2 = src2 | ~WMASK; /* sext src, src2 */\r | |
508 | if (t & WSIGN) src = src | ~LMASK;\r | |
509 | dst = src / src2; /* divide */\r | |
510 | if ((dst > 077777) || (dst < -0100000)) { /* out of range? */\r | |
511 | cc = CC_V; /* overflow */\r | |
512 | break;\r | |
513 | }\r | |
514 | CC_IIZZ_W (dst & WMASK); /* set cc's */\r | |
515 | WrRegW (dst & WMASK, srcspec); /* quotient */\r | |
516 | WrRegW ((src - (src2 * dst)) & WMASK, srcspec | 1);\r | |
517 | break;\r | |
518 | \r | |
519 | case 2: /* ASH */\r | |
520 | if (dstreg) src2 = RdRegW (dstspec); /* get src2 */\r | |
521 | else src2 = RdMemW (GeteaW (dstspec));\r | |
522 | src2 = src2 & 077;\r | |
523 | src = RdRegW (srcspec); /* get src */\r | |
524 | if (sign = ((src & WSIGN)? 1: 0)) src = src | ~WMASK;\r | |
525 | if (src2 == 0) { /* [0] */\r | |
526 | dst = src; /* result */\r | |
527 | oc = 0; /* last bit out */\r | |
528 | }\r | |
529 | else if (src2 <= 15) { /* [1,15] */\r | |
530 | dst = src << src2;\r | |
531 | i = (src >> (16 - src2)) & WMASK;\r | |
532 | oc = (i & 1)? CC_C: 0;\r | |
533 | if ((dst & WSIGN)? (i != WMASK): (i != 0)) oc = oc | CC_V;\r | |
534 | }\r | |
535 | else if (src2 <= 31) { /* [16,31] */\r | |
536 | dst = 0;\r | |
537 | oc = ((src << (src2 - 16)) & 1)? CC_C: 0;\r | |
538 | if (src) oc = oc | CC_V;\r | |
539 | }\r | |
540 | else if (src2 == 32) { /* [32] = -32 */\r | |
541 | dst = -sign;\r | |
542 | oc = sign? CC_C: 0;\r | |
543 | }\r | |
544 | else { /* [33,63] = -31,-1 */\r | |
545 | dst = (src >> (64 - src2)) | (-sign << (src2 - 32));\r | |
546 | oc = ((src >> (63 - src2)) & 1)? CC_C: 0;\r | |
547 | }\r | |
548 | WrRegW (dst = dst & WMASK, srcspec); /* result */\r | |
549 | CC_IIZZ_W (dst);\r | |
550 | cc = cc | oc;\r | |
551 | break;\r | |
552 | \r | |
553 | case 3: /* ASHC */\r | |
554 | if (dstreg) src2 = RdRegW (dstspec); /* get src2 */\r | |
555 | else src2 = RdMemW (GeteaW (dstspec));\r | |
556 | src2 = src2 & 077;\r | |
557 | t = RdRegW (srcspec);\r | |
558 | src = (((uint32) t) << 16) | RdRegW (srcspec | 1);\r | |
559 | sign = (t & WSIGN)? 1: 0; /* get src sign */\r | |
560 | if (src2 == 0) { /* [0] */\r | |
561 | dst = src; /* result */\r | |
562 | oc = 0; /* last bit out */\r | |
563 | }\r | |
564 | else if (src2 <= 31) { /* [1,31] */\r | |
565 | dst = ((uint32) src) << src2;\r | |
566 | i = ((src >> (32 - src2)) | (-sign << src2)) & LMASK;\r | |
567 | oc = (i & 1)? CC_C: 0;\r | |
568 | if ((dst & LSIGN)? (i != LMASK): (i != 0)) oc = oc | CC_V;\r | |
569 | }\r | |
570 | else if (src2 == 32) { /* [32] = -32 */\r | |
571 | dst = -sign;\r | |
572 | oc = sign? CC_C: 0;\r | |
573 | }\r | |
574 | else { /* [33,63] = -31,-1 */\r | |
575 | dst = (src >> (64 - src2)) | (-sign << (src2 - 32));\r | |
576 | oc = ((src >> (63 - src2)) & 1)? CC_C: 0;\r | |
577 | }\r | |
578 | WrRegW ((dst >> 16) & WMASK, srcspec); /* high result */\r | |
579 | WrRegW (dst & WMASK, srcspec | 1); /* low result */\r | |
580 | CC_IIZZ_L (dst & LMASK);\r | |
581 | cc = cc | oc;\r | |
582 | break;\r | |
583 | \r | |
584 | case 4: /* XOR */\r | |
585 | src = RdRegW (srcspec); /* get src */\r | |
586 | if (dstreg) src2 = RdRegW (dstspec); /* get dst */\r | |
587 | else src2 = RdMemMW (ea = GeteaW (dstspec));\r | |
588 | dst = src2 ^ src;\r | |
589 | if (dstreg) WrRegW (dst, dstspec); /* result */\r | |
590 | else WrMemW (dst, ea);\r | |
591 | CC_IIZP_W (dst);\r | |
592 | break;\r | |
593 | \r | |
594 | case 7: /* SOB */\r | |
595 | dst = (RdRegW (srcspec) - 1) & WMASK; /* decr reg */\r | |
596 | WrRegW (dst, srcspec); /* result */\r | |
597 | if (dst != 0) { /* br if zero */\r | |
598 | CMODE_JUMP ((PC - dstspec - dstspec) & WMASK);\r | |
599 | }\r | |
600 | break;\r | |
601 | \r | |
602 | default:\r | |
603 | CMODE_FAULT (CMODE_RSVI); /* end switch EIS */\r | |
604 | }\r | |
605 | break; /* end case 007 */\r | |
606 | \r | |
607 | /* Opcode 10: branches, traps, SOPs */\r | |
608 | \r | |
609 | case 010:\r | |
610 | switch ((IR >> 6) & 077) { /* decode IR<11:6> */\r | |
611 | case 000: case 001: /* BPL */\r | |
612 | if ((cc & CC_N) == 0) { BRANCH_F (IR); } \r | |
613 | break;\r | |
614 | \r | |
615 | case 002: case 003: /* BPL */\r | |
616 | if ((cc & CC_N) == 0) { BRANCH_B (IR); }\r | |
617 | break;\r | |
618 | \r | |
619 | case 004: case 005: /* BMI */\r | |
620 | if (cc & CC_N) { BRANCH_F (IR); } \r | |
621 | break;\r | |
622 | \r | |
623 | case 006: case 007: /* BMI */\r | |
624 | if (cc & CC_N) { BRANCH_B (IR); }\r | |
625 | break;\r | |
626 | \r | |
627 | case 010: case 011: /* BHI */\r | |
628 | if ((cc & (CC_C | CC_Z)) == 0) { BRANCH_F (IR); } \r | |
629 | break;\r | |
630 | \r | |
631 | case 012: case 013: /* BHI */\r | |
632 | if ((cc & (CC_C | CC_Z)) == 0) { BRANCH_B (IR); }\r | |
633 | break;\r | |
634 | \r | |
635 | case 014: case 015: /* BLOS */\r | |
636 | if (cc & (CC_C | CC_Z)) { BRANCH_F (IR); } \r | |
637 | break;\r | |
638 | \r | |
639 | case 016: case 017: /* BLOS */\r | |
640 | if (cc & (CC_C | CC_Z)) { BRANCH_B (IR); }\r | |
641 | break;\r | |
642 | \r | |
643 | case 020: case 021: /* BVC */\r | |
644 | if ((cc & CC_V) == 0) { BRANCH_F (IR); } \r | |
645 | break;\r | |
646 | \r | |
647 | case 022: case 023: /* BVC */\r | |
648 | if ((cc & CC_V) == 0) { BRANCH_B (IR); }\r | |
649 | break;\r | |
650 | \r | |
651 | case 024: case 025: /* BVS */\r | |
652 | if (cc & CC_V) { BRANCH_F (IR); } \r | |
653 | break;\r | |
654 | \r | |
655 | case 026: case 027: /* BVS */\r | |
656 | if (cc & CC_V) { BRANCH_B (IR); }\r | |
657 | break;\r | |
658 | \r | |
659 | case 030: case 031: /* BCC */\r | |
660 | if ((cc & CC_C) == 0) { BRANCH_F (IR); } \r | |
661 | break;\r | |
662 | \r | |
663 | case 032: case 033: /* BCC */\r | |
664 | if ((cc & CC_C) == 0) { BRANCH_B (IR); }\r | |
665 | break;\r | |
666 | \r | |
667 | case 034: case 035: /* BCS */\r | |
668 | if (cc & CC_C) { BRANCH_F (IR); } \r | |
669 | break;\r | |
670 | \r | |
671 | case 036: case 037: /* BCS */\r | |
672 | if (cc & CC_C) { BRANCH_B (IR); }\r | |
673 | break;\r | |
674 | \r | |
675 | case 040: case 041: case 042: case 043: /* EMT */\r | |
676 | CMODE_FAULT (CMODE_EMT);\r | |
677 | break;\r | |
678 | \r | |
679 | case 044: case 045: case 046: case 047: /* TRAP */\r | |
680 | CMODE_FAULT (CMODE_TRAP);\r | |
681 | break;\r | |
682 | \r | |
683 | case 050: /* CLRB */\r | |
684 | if (dstreg) WrRegB (0, dstspec);\r | |
685 | else WrMemB (0, GeteaB (dstspec));\r | |
686 | cc = CC_Z;\r | |
687 | break;\r | |
688 | \r | |
689 | case 051: /* COMB */\r | |
690 | if (dstreg) src = RdRegB (dstspec);\r | |
691 | else src = RdMemMB (ea = GeteaB (dstspec));\r | |
692 | dst = src ^ BMASK;\r | |
693 | if (dstreg) WrRegB (dst, dstspec);\r | |
694 | else WrMemB (dst, ea);\r | |
695 | CC_IIZZ_B (dst);\r | |
696 | cc = cc | CC_C;\r | |
697 | break;\r | |
698 | \r | |
699 | case 052: /* INCB */\r | |
700 | if (dstreg) src = RdRegB (dstspec);\r | |
701 | else src = RdMemMB (ea = GeteaB (dstspec));\r | |
702 | dst = (src + 1) & BMASK;\r | |
703 | if (dstreg) WrRegB (dst, dstspec);\r | |
704 | else WrMemB (dst, ea);\r | |
705 | CC_IIZP_B (dst);\r | |
706 | if (dst == 0200) cc = cc | CC_V;\r | |
707 | break;\r | |
708 | \r | |
709 | case 053: /* DECB */\r | |
710 | if (dstreg) src = RdRegB (dstspec);\r | |
711 | else src = RdMemMB (ea = GeteaB (dstspec));\r | |
712 | dst = (src - 1) & BMASK;\r | |
713 | if (dstreg) WrRegB (dst, dstspec);\r | |
714 | else WrMemB (dst, ea);\r | |
715 | CC_IIZP_B (dst);\r | |
716 | if (dst == 0177) cc = cc | CC_V;\r | |
717 | break;\r | |
718 | \r | |
719 | case 054: /* NEGB */\r | |
720 | if (dstreg) src = RdRegB (dstspec);\r | |
721 | else src = RdMemMB (ea = GeteaB (dstspec));\r | |
722 | dst = (-src) & BMASK;\r | |
723 | if (dstreg) WrRegB (dst, dstspec);\r | |
724 | else WrMemB (dst, ea);\r | |
725 | CC_IIZZ_B (dst);\r | |
726 | if (dst == 0200) cc = cc | CC_V;\r | |
727 | if (dst) cc = cc | CC_C;\r | |
728 | break;\r | |
729 | \r | |
730 | case 055: /* ADCB */\r | |
731 | if (dstreg) src = RdRegB (dstspec);\r | |
732 | else src = RdMemMB (ea = GeteaB (dstspec));\r | |
733 | dst = (src + (cc & CC_C)) & BMASK;\r | |
734 | if (dstreg) WrRegB (dst, dstspec);\r | |
735 | else WrMemB (dst, ea);\r | |
736 | CC_IIZZ_B (dst);\r | |
737 | if ((src == 0177) && (dst == 0200)) cc = cc | CC_V;\r | |
738 | if ((src == 0377) && (dst == 0)) cc = cc | CC_C;\r | |
739 | break;\r | |
740 | \r | |
741 | case 056: /* SBCB */\r | |
742 | if (dstreg) src = RdRegB (dstspec);\r | |
743 | else src = RdMemMB (ea = GeteaB (dstspec));\r | |
744 | dst = (src - (cc & CC_C)) & BMASK;\r | |
745 | if (dstreg) WrRegB (dst, dstspec);\r | |
746 | else WrMemB (dst, ea);\r | |
747 | CC_IIZZ_B (dst);\r | |
748 | if ((src == 0200) && (dst == 0177)) cc = cc | CC_V;\r | |
749 | if ((src == 0) && (dst == 0377)) cc = cc | CC_C;\r | |
750 | break;\r | |
751 | \r | |
752 | case 057: /* TSTB */\r | |
753 | if (dstreg) src = RdRegB (dstspec);\r | |
754 | else src = RdMemB (GeteaB (dstspec));\r | |
755 | CC_IIZZ_B (src);\r | |
756 | break;\r | |
757 | \r | |
758 | case 060: /* RORB */\r | |
759 | if (dstreg) src = RdRegB (dstspec);\r | |
760 | else src = RdMemMB (ea = GeteaB (dstspec));\r | |
761 | dst = (src >> 1) | ((cc & CC_C)? BSIGN: 0);\r | |
762 | if (dstreg) WrRegB (dst, dstspec);\r | |
763 | else WrMemB (dst, ea);\r | |
764 | CC_IIZZ_B (dst);\r | |
765 | if (src & 1) cc = cc | CC_C;\r | |
766 | if (CC_XOR_NC (cc)) cc = cc | CC_V;\r | |
767 | break;\r | |
768 | \r | |
769 | case 061: /* ROLB */\r | |
770 | if (dstreg) src = RdRegB (dstspec);\r | |
771 | else src = RdMemMB (ea = GeteaB (dstspec));\r | |
772 | dst = ((src << 1) | ((cc & CC_C)? 1: 0)) & BMASK;\r | |
773 | if (dstreg) WrRegB (dst, dstspec);\r | |
774 | else WrMemB (dst, ea);\r | |
775 | CC_IIZZ_B (dst);\r | |
776 | if (src & BSIGN) cc = cc | CC_C;\r | |
777 | if (CC_XOR_NC (cc)) cc = cc | CC_V;\r | |
778 | break;\r | |
779 | \r | |
780 | case 062: /* ASRB */\r | |
781 | if (dstreg) src = RdRegB (dstspec);\r | |
782 | else src = RdMemMB (ea = GeteaB (dstspec));\r | |
783 | dst = (src >> 1) | (src & BSIGN);\r | |
784 | if (dstreg) WrRegB (dst, dstspec);\r | |
785 | else WrMemB (dst, ea);\r | |
786 | CC_IIZZ_B (dst);\r | |
787 | if (src & 1) cc = cc | CC_C;\r | |
788 | if (CC_XOR_NC (cc)) cc = cc | CC_V;\r | |
789 | break;\r | |
790 | \r | |
791 | case 063: /* ASLB */\r | |
792 | if (dstreg) src = RdRegB (dstspec);\r | |
793 | else src = RdMemMB (ea = GeteaB (dstspec));\r | |
794 | dst = (src << 1) & BMASK;\r | |
795 | if (dstreg) WrRegB (dst, dstspec);\r | |
796 | else WrMemB (dst, ea);\r | |
797 | CC_IIZZ_B (dst);\r | |
798 | if (src & BSIGN) cc = cc | CC_C;\r | |
799 | if (CC_XOR_NC (cc)) cc = cc | CC_V;\r | |
800 | break;\r | |
801 | \r | |
802 | case 065: /* MFPD */\r | |
803 | if (dstreg) dst = RdRegW (dstspec); /* "mov dst,-(sp)" */\r | |
804 | else dst = RdMemW (GeteaW (dstspec));\r | |
805 | WrMemW (dst, (R[6] - 2) & WMASK);\r | |
806 | R[6] = (R[6] - 2) & WMASK;\r | |
807 | CC_IIZP_W (dst);\r | |
808 | break;\r | |
809 | \r | |
810 | case 066: /* MTPD */\r | |
811 | dst = RdMemW (R[6] & WMASK); /* "mov (sp)+,dst" */\r | |
812 | R[6] = (R[6] + 2) & WMASK;\r | |
813 | recq[recqptr++] = RQ_REC (AIN|RW, 6);\r | |
814 | if (dstreg) WrRegW (dst, dstspec);\r | |
815 | else WrMemW (dst, (GeteaW (dstspec) & WMASK));\r | |
816 | CC_IIZP_W (dst);\r | |
817 | break;\r | |
818 | \r | |
819 | default:\r | |
820 | CMODE_FAULT (CMODE_RSVI);\r | |
821 | break; } /* end switch SOPs */\r | |
822 | break; /* end case 010 */\r | |
823 | \r | |
824 | /* Opcodes 11 - 16: double operand byte instructions\r | |
825 | \r | |
826 | Cmp: v = [sign (src) != sign (src2)] and [sign (src2) = sign (result)]\r | |
827 | Sub: v = [sign (src) != sign (src2)] and [sign (src) = sign (result)]\r | |
828 | */\r | |
829 | \r | |
830 | case 011: /* MOVB */\r | |
831 | if (srcreg) src = RdRegB (srcspec);\r | |
832 | else src = RdMemB (GeteaB (srcspec));\r | |
833 | if (dstreg) WrRegW ((src & BSIGN)? (0xFF00 | src): src, dstspec);\r | |
834 | else WrMemB (src, GeteaB (dstspec));\r | |
835 | CC_IIZP_B (src);\r | |
836 | break;\r | |
837 | \r | |
838 | case 012: /* CMPB */\r | |
839 | if (srcreg) src = RdRegB (srcspec);\r | |
840 | else src = RdMemB (GeteaB (srcspec));\r | |
841 | if (dstreg) src2 = RdRegB (dstspec);\r | |
842 | else src2 = RdMemB (GeteaB (dstspec));\r | |
843 | dst = (src - src2) & BMASK;\r | |
844 | CC_IIZZ_B (dst);\r | |
845 | if (((src ^ src2) & (~src2 ^ dst)) & BSIGN) cc = cc | CC_V;\r | |
846 | if (src < src2) cc = cc | CC_C;\r | |
847 | break;\r | |
848 | \r | |
849 | case 013: /* BITB */\r | |
850 | if (srcreg) src = RdRegB (srcspec);\r | |
851 | else src = RdMemB (GeteaB (srcspec));\r | |
852 | if (dstreg) src2 = RdRegB (dstspec);\r | |
853 | else src2 = RdMemB (GeteaB (dstspec));\r | |
854 | dst = src2 & src;\r | |
855 | CC_IIZP_B (dst);\r | |
856 | break;\r | |
857 | \r | |
858 | case 014: /* BICB */\r | |
859 | if (srcreg) src = RdRegB (srcspec);\r | |
860 | else src = RdMemB (GeteaB (srcspec));\r | |
861 | if (dstreg) src2 = RdRegB (dstspec);\r | |
862 | else src2 = RdMemMB (ea = GeteaB (dstspec));\r | |
863 | dst = src2 & ~src;\r | |
864 | if (dstreg) WrRegB (dst, dstspec);\r | |
865 | else WrMemB (dst, ea);\r | |
866 | CC_IIZP_B (dst);\r | |
867 | break;\r | |
868 | \r | |
869 | case 015: /* BISB */\r | |
870 | if (srcreg) src = RdRegB (srcspec);\r | |
871 | else src = RdMemB (GeteaB (srcspec));\r | |
872 | if (dstreg) src2 = RdRegB (dstspec);\r | |
873 | else src2 = RdMemMB (ea = GeteaB (dstspec));\r | |
874 | dst = src2 | src;\r | |
875 | if (dstreg) WrRegB (dst, dstspec);\r | |
876 | else WrMemB (dst, ea);\r | |
877 | CC_IIZP_B (dst);\r | |
878 | break;\r | |
879 | \r | |
880 | case 016: /* SUB */\r | |
881 | if (srcreg) src = RdRegW (srcspec);\r | |
882 | else src = RdMemW (GeteaW (srcspec));\r | |
883 | if (dstreg) src2 = RdRegW (dstspec);\r | |
884 | else src2 = RdMemMW (ea = GeteaW (dstspec));\r | |
885 | dst = (src2 - src) & WMASK;\r | |
886 | if (dstreg) WrRegW (dst, dstspec);\r | |
887 | else WrMemW (dst, ea);\r | |
888 | CC_IIZZ_W (dst);\r | |
889 | if (((src ^ src2) & (~src ^ dst)) & WSIGN) cc = cc | CC_V;\r | |
890 | if (src2 < src) cc = cc | CC_C;\r | |
891 | break;\r | |
892 | \r | |
893 | default:\r | |
894 | CMODE_FAULT (CMODE_RSVI);\r | |
895 | break;\r | |
896 | } /* end switch op */\r | |
897 | \r | |
898 | return cc;\r | |
899 | }\r | |
900 | \r | |
901 | /* Effective address calculations\r | |
902 | \r | |
903 | Inputs:\r | |
904 | spec = specifier <5:0>\r | |
905 | Outputs:\r | |
906 | ea = effective address\r | |
907 | */\r | |
908 | \r | |
909 | int32 GeteaW (int32 spec)\r | |
910 | {\r | |
911 | int32 adr, reg;\r | |
912 | \r | |
913 | reg = spec & 07; /* register number */\r | |
914 | switch (spec >> 3) { /* decode spec<5:3> */\r | |
915 | \r | |
916 | default: /* can't get here */\r | |
917 | case 1: /* (R) */\r | |
918 | if (reg == 7) return (PC & WMASK);\r | |
919 | else return (R[reg] & WMASK);\r | |
920 | \r | |
921 | case 2: /* (R)+ */\r | |
922 | if (reg == 7) PC = ((adr = PC) + 2) & WMASK;\r | |
923 | else {\r | |
924 | R[reg] = ((adr = R[reg]) + 2) & WMASK;\r | |
925 | recq[recqptr++] = RQ_REC (AIN|RW, reg);\r | |
926 | }\r | |
927 | return adr;\r | |
928 | \r | |
929 | case 3: /* @(R)+ */\r | |
930 | if (reg == 7) PC = ((adr = PC) + 2) & WMASK;\r | |
931 | else {\r | |
932 | R[reg] = ((adr = R[reg]) + 2) & WMASK;\r | |
933 | recq[recqptr++] = RQ_REC (AIN|RW, reg);\r | |
934 | }\r | |
935 | return RdMemW (adr);\r | |
936 | \r | |
937 | case 4: /* -(R) */\r | |
938 | if (reg == 7) adr = PC = (PC - 2) & WMASK;\r | |
939 | else {\r | |
940 | adr = R[reg] = (R[reg] - 2) & WMASK;\r | |
941 | recq[recqptr++] = RQ_REC (ADC|RW, reg);\r | |
942 | }\r | |
943 | return adr;\r | |
944 | \r | |
945 | case 5: /* @-(R) */\r | |
946 | if (reg == 7) adr = PC = (PC - 2) & WMASK;\r | |
947 | else {\r | |
948 | adr = R[reg] = (R[reg] - 2) & WMASK;\r | |
949 | recq[recqptr++] = RQ_REC (ADC|RW, reg);\r | |
950 | }\r | |
951 | return RdMemW (adr);\r | |
952 | \r | |
953 | case 6: /* d(r) */\r | |
954 | adr = RdMemW (PC);\r | |
955 | PC = (PC + 2) & WMASK;\r | |
956 | if (reg == 7) return ((PC + adr) & WMASK);\r | |
957 | else return ((R[reg] + adr) & WMASK);\r | |
958 | \r | |
959 | case 7: /* @d(R) */\r | |
960 | adr = RdMemW (PC);\r | |
961 | PC = (PC + 2) & WMASK;\r | |
962 | if (reg == 7) adr = (PC + adr) & WMASK;\r | |
963 | else adr = (R[reg] + adr) & WMASK;\r | |
964 | return RdMemW (adr);\r | |
965 | } /* end switch */\r | |
966 | }\r | |
967 | \r | |
968 | int32 GeteaB (int32 spec)\r | |
969 | {\r | |
970 | int32 adr, reg;\r | |
971 | \r | |
972 | reg = spec & 07; /* reg number */\r | |
973 | switch (spec >> 3) { /* decode spec<5:3> */\r | |
974 | \r | |
975 | default: /* can't get here */\r | |
976 | case 1: /* (R) */\r | |
977 | if (reg == 7) return (PC & WMASK);\r | |
978 | else return (R[reg] & WMASK);\r | |
979 | \r | |
980 | case 2: /* (R)+ */\r | |
981 | if (reg == 7) PC = ((adr = PC) + 2) & WMASK;\r | |
982 | else if (reg == 6) {\r | |
983 | R[reg] = ((adr = R[reg]) + 2) & WMASK;\r | |
984 | recq[recqptr++] = RQ_REC (AIN|RW, reg);\r | |
985 | }\r | |
986 | else {\r | |
987 | R[reg] = ((adr = R[reg]) + 1) & WMASK;\r | |
988 | recq[recqptr++] = RQ_REC (AIN|RB, reg);\r | |
989 | }\r | |
990 | return adr;\r | |
991 | \r | |
992 | case 3: /* @(R)+ */\r | |
993 | if (reg == 7) PC = ((adr = PC) + 2) & WMASK;\r | |
994 | else {\r | |
995 | R[reg] = ((adr = R[reg]) + 2) & WMASK;\r | |
996 | recq[recqptr++] = RQ_REC (AIN|RW, reg);\r | |
997 | }\r | |
998 | return RdMemW (adr);\r | |
999 | \r | |
1000 | case 4: /* -(R) */\r | |
1001 | if (reg == 7) adr = PC = (PC - 2) & WMASK;\r | |
1002 | else if (reg == 6) {\r | |
1003 | adr = R[reg] = (R[reg] - 2) & WMASK;\r | |
1004 | recq[recqptr++] = RQ_REC (ADC|RW, reg);\r | |
1005 | }\r | |
1006 | else {\r | |
1007 | adr = R[reg] = (R[reg] - 1) & WMASK;\r | |
1008 | recq[recqptr++] = RQ_REC (ADC|RB, reg);\r | |
1009 | }\r | |
1010 | return adr;\r | |
1011 | \r | |
1012 | case 5: /* @-(R) */\r | |
1013 | if (reg == 7) adr = PC = (PC - 2) & WMASK;\r | |
1014 | else {\r | |
1015 | adr = R[reg] = (R[reg] - 2) & WMASK;\r | |
1016 | recq[recqptr++] = RQ_REC (ADC|RW, reg);\r | |
1017 | }\r | |
1018 | return RdMemW (adr);\r | |
1019 | \r | |
1020 | case 6: /* d(r) */\r | |
1021 | adr = RdMemW (PC);\r | |
1022 | PC = (PC + 2) & WMASK;\r | |
1023 | if (reg == 7) return ((PC + adr) & WMASK);\r | |
1024 | else return ((R[reg] + adr) & WMASK);\r | |
1025 | \r | |
1026 | case 7: /* @d(R) */\r | |
1027 | adr = RdMemW (PC);\r | |
1028 | PC = (PC + 2) & WMASK;\r | |
1029 | if (reg == 7) adr = (PC + adr) & WMASK;\r | |
1030 | else adr = (R[reg] + adr) & WMASK;\r | |
1031 | return RdMemW (adr);\r | |
1032 | } /* end switch */\r | |
1033 | }\r | |
1034 | \r | |
1035 | /* Memory and register access routines */\r | |
1036 | \r | |
1037 | int32 RdMemW (int32 a)\r | |
1038 | {\r | |
1039 | int32 acc = ACC_MASK (USER);\r | |
1040 | \r | |
1041 | if (a & 1) CMODE_FAULT (CMODE_ODD);\r | |
1042 | return Read (a, L_WORD, RA);\r | |
1043 | }\r | |
1044 | \r | |
1045 | int32 RdMemMW (int32 a)\r | |
1046 | {\r | |
1047 | int32 acc = ACC_MASK (USER);\r | |
1048 | \r | |
1049 | if (a & 1) CMODE_FAULT (CMODE_ODD);\r | |
1050 | return Read (a, L_WORD, WA);\r | |
1051 | }\r | |
1052 | \r | |
1053 | void WrMemW (int32 d, int32 a)\r | |
1054 | {\r | |
1055 | int32 acc = ACC_MASK (USER);\r | |
1056 | \r | |
1057 | if (a & 1) CMODE_FAULT (CMODE_ODD);\r | |
1058 | Write (a, d, L_WORD, WA);\r | |
1059 | return;\r | |
1060 | }\r | |
1061 | \r | |
1062 | int32 RdRegB (int32 rn)\r | |
1063 | {\r | |
1064 | if (rn == 7) return (PC & BMASK);\r | |
1065 | else return (R[rn] & BMASK);\r | |
1066 | }\r | |
1067 | \r | |
1068 | int32 RdRegW (int32 rn)\r | |
1069 | {\r | |
1070 | if (rn == 7) return (PC & WMASK);\r | |
1071 | else return (R[rn] & WMASK);\r | |
1072 | }\r | |
1073 | \r | |
1074 | void WrRegB (int32 val, int32 rn)\r | |
1075 | {\r | |
1076 | if (rn == 7) { CMODE_JUMP ((PC & ~BMASK) | val); }\r | |
1077 | else R[rn] = (R[rn] & ~BMASK) | val;\r | |
1078 | return;\r | |
1079 | }\r | |
1080 | \r | |
1081 | void WrRegW (int32 val, int32 rn)\r | |
1082 | {\r | |
1083 | if (rn == 7) { CMODE_JUMP (val); }\r | |
1084 | else R[rn] = val;\r | |
1085 | return;\r | |
1086 | }\r | |
1087 | \r | |
1088 | #else\r | |
1089 | \r | |
1090 | /* Subset VAX\r | |
1091 | \r | |
1092 | Never legal to set CM in PSL\r | |
1093 | Should never get to instruction execution\r | |
1094 | */\r | |
1095 | \r | |
1096 | extern jmp_buf save_env;\r | |
1097 | \r | |
1098 | t_bool BadCmPSL (int32 newpsl)\r | |
1099 | {\r | |
1100 | return TRUE; /* always bad */\r | |
1101 | }\r | |
1102 | \r | |
1103 | int32 op_cmode (int32 cc)\r | |
1104 | {\r | |
1105 | RSVD_INST_FAULT;\r | |
1106 | return cc;\r | |
1107 | }\r | |
1108 | \r | |
1109 | #endif\r |