Commit | Line | Data |
---|---|---|
196ba1fc PH |
1 | /* vax_sys.c: VAX simulator interface\r |
2 | \r | |
3 | Copyright (c) 1998-2006, Robert M Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | 17-Oct-06 RMS Re-ordered device list\r | |
27 | 17-May-06 RMS Added CR11/CD11 support (from John Dundas)\r | |
28 | 01-Oct-2004 RMS Cloned from vax_sys.c\r | |
29 | */\r | |
30 | \r | |
31 | #include "vax_defs.h"\r | |
32 | \r | |
33 | char sim_name[] = "VAX";\r | |
34 | \r | |
35 | extern DEVICE cpu_dev;\r | |
36 | extern DEVICE tlb_dev;\r | |
37 | extern DEVICE rom_dev;\r | |
38 | extern DEVICE nvr_dev;\r | |
39 | extern DEVICE sysd_dev;\r | |
40 | extern DEVICE qba_dev;\r | |
41 | extern DEVICE tti_dev, tto_dev;\r | |
42 | extern DEVICE cr_dev;\r | |
43 | extern DEVICE lpt_dev;\r | |
44 | extern DEVICE clk_dev;\r | |
45 | extern DEVICE rq_dev, rqb_dev, rqc_dev, rqd_dev;\r | |
46 | extern DEVICE rl_dev;\r | |
47 | extern DEVICE ry_dev;\r | |
48 | extern DEVICE ts_dev;\r | |
49 | extern DEVICE tq_dev;\r | |
50 | extern DEVICE dz_dev;\r | |
51 | extern DEVICE csi_dev, cso_dev;\r | |
52 | extern DEVICE xq_dev, xqb_dev;\r | |
53 | extern DEVICE vh_dev;\r | |
54 | \r | |
55 | extern int32 sim_switches;\r | |
56 | extern void WriteB (uint32 pa, int32 val);\r | |
57 | extern void rom_wr_B (int32 pa, int32 val);\r | |
58 | extern UNIT cpu_unit;\r | |
59 | \r | |
60 | DEVICE *sim_devices[] = { \r | |
61 | &cpu_dev,\r | |
62 | &tlb_dev,\r | |
63 | &rom_dev,\r | |
64 | &nvr_dev,\r | |
65 | &sysd_dev,\r | |
66 | &qba_dev,\r | |
67 | &clk_dev,\r | |
68 | &tti_dev,\r | |
69 | &tto_dev,\r | |
70 | &csi_dev,\r | |
71 | &cso_dev,\r | |
72 | &dz_dev,\r | |
73 | &vh_dev,\r | |
74 | &cr_dev,\r | |
75 | &lpt_dev,\r | |
76 | &rl_dev,\r | |
77 | &rq_dev,\r | |
78 | &rqb_dev,\r | |
79 | &rqc_dev,\r | |
80 | &rqd_dev,\r | |
81 | &ry_dev,\r | |
82 | &ts_dev,\r | |
83 | &tq_dev,\r | |
84 | &xq_dev,\r | |
85 | &xqb_dev,\r | |
86 | NULL\r | |
87 | };\r | |
88 | \r | |
89 | /* Binary loader\r | |
90 | \r | |
91 | The binary loader handles absolute system images, that is, system\r | |
92 | images linked /SYSTEM. These are simply a byte stream, with no\r | |
93 | origin or relocation information.\r | |
94 | \r | |
95 | -r load ROM\r | |
96 | -n load NVR\r | |
97 | -o for memory, specify origin\r | |
98 | */\r | |
99 | \r | |
100 | t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)\r | |
101 | {\r | |
102 | t_stat r;\r | |
103 | int32 i;\r | |
104 | uint32 origin, limit;\r | |
105 | extern int32 ssc_cnf;\r | |
106 | #define SSCCNF_BLO 0x80000000\r | |
107 | \r | |
108 | if (flag) return SCPE_ARG; /* dump? */\r | |
109 | if (sim_switches & SWMASK ('R')) { /* ROM? */\r | |
110 | origin = ROMBASE;\r | |
111 | limit = ROMBASE + ROMSIZE;\r | |
112 | }\r | |
113 | else if (sim_switches & SWMASK ('N')) { /* NVR? */\r | |
114 | origin = NVRBASE;\r | |
115 | limit = NVRBASE + NVRSIZE;\r | |
116 | ssc_cnf = ssc_cnf & ~SSCCNF_BLO;\r | |
117 | }\r | |
118 | else {\r | |
119 | origin = 0; /* memory */\r | |
120 | limit = (uint32) cpu_unit.capac;\r | |
121 | if (sim_switches & SWMASK ('O')) { /* origin? */\r | |
122 | origin = (int32) get_uint (cptr, 16, 0xFFFFFFFF, &r);\r | |
123 | if (r != SCPE_OK) return SCPE_ARG;\r | |
124 | }\r | |
125 | }\r | |
126 | while ((i = getc (fileref)) != EOF) { /* read byte stream */\r | |
127 | if (origin >= limit) return SCPE_NXM; /* NXM? */\r | |
128 | if (sim_switches & SWMASK ('R')) /* ROM? */\r | |
129 | rom_wr_B (origin, i); /* not writeable */\r | |
130 | else WriteB (origin, i); /* store byte */\r | |
131 | origin = origin + 1;\r | |
132 | }\r | |
133 | return SCPE_OK;\r | |
134 | }\r | |
135 | \r |