[pdp8.git] / sw / maindec / rk8e / dhrka / maindec-08-dhrka.index

RK8-E Diskless Control Test\r\r\rMAINDEC-08-DHRKA-E-D (Documentation)\rMAINDEC-08-DHRKA-B-PB (Paper Tape)\r\r\rTest	Addr.	PC	Description\r----------------------------------------------------------------------------------------------\r0	0226		Check if disk motor is off. Status 2200 expected.\r1	0235\r2	0242\r3	0250\r4	0256\r5	0272\r6	0305\r7	0314\r8	0323\r9	0334		Check if DCLR clears AC, try all AC combinations\r10	0343	0363\r11	0365\r12	0410\r13	0424\r13	0441\r15	0454	0505	Verify that DLAG loads sector and surface\r16	0507\r17	0537		Verify that disk address can be loaded and shifted into ldb\r18	0561\r19	0604\r20	0616\r21	0633	0645	Verify that DCLR(01) does not clear surface and sector\r22	0647\r23	0673\r24	0720\r25	0742	0765	Verify that DCLR(!=10) does not affect CRC using DLAG and DLDC\r26	0767	1026	Is CRC not affected by DLDC,DSKP,DRST,DLCA and read buffer?\r27	1030	1045	Verify that write lock inhibits load address when set\r28	1047	1075	DCLR,DLCA,DRST,DLDC,DSKP and read buffer affect sect & surf?\r29	1077	1130	Verify that command register is not affected by DLCR,... \r30	1132	1150	Verify that recalibrate inhibits load command on DLDC\r31	1152	1171	Verify that recalibrate inhibits load disk address on DLAG\r32	1173\r33\r34\r35\r36\r37\r38\r39\r40\r41	1526\r42\r43\r44\r45	1615	1650\r46\r47\r48\r49	2000	2033	Verify that Data Request Late occurs when ldb is empty \r50	2035	2075\r51	2077	2115	Verify that DSKP skips on DRL error\r52\r53	2134	2157\r54	2200	2226\r55	2253	2230	Verify that recalibrate does set drive status error\r56	2270	2255\r57	2306	2272\r58\r59\r60\r61\r62	2444	2466	Does maintenance mode inhibit drive status error skip?\r63	2470	2526	Does recalibrate, then DCLR set control busy and status error?\r64	2530	2566	Does recalibrate, then DRL set DRL, status error and done?\r65	2600	2634	Does recalibrate, then DLCA set control busy and status error?\r66	2636	2655\r67	2657	2675 \r68	2677	2716	Verify that skip occurs on control busy error\r69	2720	2751	Verify that DCLR(0) clears all of status register\r70	2753	2775	Verify that interrupt occurs on control busy error\r71	2777	3042	Verify that read buffer,DCLR,DRST,DLAG,DSKP not affect status\r72	3044	3116	Does word count overflow after 256 12-bit-shifts and set done?\r73\r74	3271	3341	Does half block flag in command register work?\r75\r76\r77	3443	3471	Verify data break at loc. 0 of current field with "write"\r78\r79\r80\r81\r82\r83\r84	3737	3777	Verify current address increments from 7777 to 0 on "write"\r85	4001	4052	Verify current address increments from 200 to TST85 on "write"\r86	4054	4153	Is write inhibit set after 256 breaks and cleared by DLAG?\r87	4200	4272	Is write inhibit set after 128 breaks and cleared by DLAG?\r88	4274	4321	Verify "read" data break at 0000 and 7777\r89\r90\r91\r92\r93\r94			Verify that command 2 causes a "read" data break\r95			Verify that command 3 causes a "read" data break\r96	-	-	-\r97	5000	5027	Verify that command 6 causes a "read" data break\r98			Verify that command 7 causes a "read" data break\r99	5063	5127	Verify that all data buffers can be full by "read" data break\r100\r101\r102\r103\r104\r105\r