[pdp8.git] / sw / rescue / lab8e_goettingen / disk2_11 / rka / paroff / clock.ra

/	\ eCLOCK.RA - DK8-EP HANDLER\r
/\r
/	TO ASSEMBLE DK8-EP HANDLER FOR FIRST CLOCK: NO SWITCHES\r
/	TO ASSEMBLE DK8-EP HANDLER FOR 2 ND  CLOCK: /1 SWITCH\r
/	TO ENABLE TIME ROUTINE TO APPROPIATE CLOCK : /2 SWITCH \r
/	TO ENABLE CLOCK STATUS TO GENERAL RTS ROUTINES: /3 SWITCH\r
/	SO NORMALLY FOR FIRST CLOCK USE /3 SWITCH!\r
/	TO ENABLE CLOCK TO SCHMITT TRIGGER EVENT USE /4 SWITCH\r
/	DO NOT COMBINE /2 AND /4 SWITCHES!\r
/	  THIS GENERATES CLOCK4:\r
/	  NO PRESET TO DK8-EP\r
/	  MODE BITS: 11\r
/	  SELECT RATE: N/4096\r
/	  APPLICABLE FOR BOTH DK8-EP CLOCKS. BUT ONLY FOR ONE PER PROGRAM!\r
/\r
/\r
/	1.0  18-MAR-85 H.A.  (COPY OF CLOCK.RA )\r
/	1.1  26-JUN-85 H.A.\r
/\r
	EXTERN #DISP	/SYSTEM PAGE 0,NEEDED TO\r
			/PUT CLOCK STATUS ON PG0\r
			/(CSTAT) FOR USE BY GEN\r
			/USER CLOCK SERVICE ROUTS\r
	EXTERN #T812	/RTS CPTYP\r
	EXTERN ONQI	/INTERRUPT QUEUER\r
/\r
	IFNSW	1 <\r
	ENTRY	#CLINT	/USER EXTENDED CLOCK ROUTINE\r
	DEVICE=13*10\r
	>\r
	IFSW	3 <\r
	CSTAT=157	/IDOCLK PUTS CLSA BITS OF FIRST CLOCK\r
			/IN HERE FOR SOMEBODY ELSE\r
	>\r
	IFSW	2 <\r
	ENTRY	TIME	/ ENABLE TIME ROUTINE TO RTS\r
	>\r
	IFSW	1 <\r
	ENTRY	#CLIN1 /USER EXTENDED CLOCK ROUTINE\r
	DEVICE=17*10\r
	>\r
	CLZE=6000!DEVICE /CLOCK IOTS\r
	CLSK=6001!DEVICE\r
	CLLR=6002!DEVICE /ALSO CLOE\r
	CLAB=6003!DEVICE\r
	CLEN=6004!DEVICE\r
	CLSA=6005!DEVICE\r
\f          BASE FTMP0\r
          INDEX FCNWD\r
          IFNSW 2 <\r
          IFSW 1 <\r
          FIELD1 #SYNC >\r
          IFSW 4 <\r
          FIELD1 SYNC4 >\r
	>\r
	IFSW	2 <\r
	FIELD1	SYNC >\r
	BASE FTMP0\r
	INDEX FCNWD\r
	JSA SETUP	/HERE TO READ A STRIG\r
			/INITIALIZE ARGS\r
	TRAP4 DOSYNC	/FCNWD (XR) HOLDS STRIG\r
			/TO READ\r
	XTA FCNWD	/=ANS=0,1\r
	FSTA% FTMP1	/GIVE ANS TO CALLER\r
	JA GOBAK\r
FTMP0,	F 0.0		/BASE PAGE\r
FTMP1,	F 0.0\r
RPTR,	27;ADDR RTBL	/PTR TO RATE TBL, ALSO\r
			/USED TO FLT OVRCNT (NOTE\r
			/THAT THE EXPONENT=27)\r
MINRAT,	F .02		/MIN ALLOWABLE RATE\r
TOVR,	F 0.0\r
	IFNSW  4 <\r
	IFNSW	1 <\r
NAME,	TEXT	+CLOCK + >\r
	IFSW	1 <\r
NAME,	TEXT	+CLOCK1+ >\r
	>\r
	IFSW  4 <\r
	IFNSW	1 <\r
NAME,	TEXT	+CLOCK4+ >\r
	IFSW	1 <\r
NAME,	TEXT	+CLOC14+ >\r
	>\r
	ORG	10*3+FTMP0\r
	FNOP\r
	JA	NAME+3\r
	0\r
GOBAK,	JA	.\r
RTBL,	F 16.0		/CONSTANT USED TO CHK FOR\r
			/EXT CLK BIT IN FCNWD\r
			/THIS CONST MUST BE NE 0\r
MAXRAT,\r
F4096,	F 4096.0	/USED TO GET OVRFLO COUNT\r
	F 100000.0	/FASTEST RATE IN HERTZ\r
	F 10000.0	/NEXT FASTEST RATE\r
	F 1000.0\r
	F 100.0		/SLOWEST RATE\r
	F 1.0		/USED BY TIME FOR EXT CLK\r
\f	BASE 0\r
 \r
SETUP,	0;0		/HERE TO INIT ALL FPP SUBS\r
	STARTD\r
	FLDA 30		/PICK UP RTN TO CALLER\r
	FSTA GOBAK\r
	FLDA 0		/GET PTR TO CALLERS ARGS\r
	SETX FCNWD	/CLOCK XR AND BASE\r
	SETB FTMP0\r
	BASE FTMP0\r
	FSTA FTMP1\r
	FLDA% FTMP1,P1\r
	FSTA FTMP0	/PTR TO 1ST ARG\r
	FLDA% FTMP1,P2\r
	FSTA FTMP1	/PTR TO 2ND ARG\r
	FLDA #T812	/TELLS PDP8,PDP12\r
	ATX CPTYP	/0=8=DK8ES,1=12=KW12A\r
	STARTF\r
	FLDA% FTMP0	/=1ST ARG\r
	ATX FCNWD	/ALWAYS IN FCNWD\r
	JA SETUP\r
\f        IFNSW   4 <\r
	IFNSW	2 <\r
        IFNSW   1 <\r
        ENTRY   CLOCK\r
CLOCK,  > >\r
        IFSW    1 <\r
        ENTRY CLOCK1\r
CLOCK1, >\r
	    >\r
	IFSW	2 <\r
	ENTRY	CLOCK\r
CLOCK,	>\r
        IFSW    4 <\r
        IFNSW   1 <\r
        ENTRY   CLOCK4\r
CLOCK4, >\r
        IFSW    1 <\r
        ENTRY CLOC14\r
CLOC14, >\r
        >\r
	JSA SETUP	/HERE FOR CLOCK START\r
	FLDA%	FTMP0\r
	FSUB RTBL	/FCNWD IS IN FAC,IF GE 16\r
	JGE ITSEXT	/(RTBL=16.0) THEN USER IS\r
			/REQUESTING AN EXTERNAL\r
			/CLOCK I.E. B8 OF FCNWD\r
			/IS SET.\r
	FLDA% FTMP1	/=REQUESTED RATE IN HERTZ\r
	FSUB MINRAT	/.LE. MINUMUM RATE\r
	JLE GOTR-2	/MEANS STOP CLOCK.\r
	FADD MINRAT\r
	FSUB MAXRAT	/CHK FOR TOO FAST\r
	JGT GOTR-2\r
	LDX -4,OVRFLO	/THERE ARE 4 BASIC RATES\r
	LDX 1,RATE	/=INDEX INTO RTBL; UPON\r
			/TRAP(CLOCK) RATE=(0,\r
			/2,3,4,5,6) 0=STOP,\r
			/6=EXTERNAL\r
			/2-5=PROGRAMMABLE RATES\r
LOP0,	FLDA% RPTR,RATE+\r
			/GET NEXT SLOWEST RATE\r
	FDIV% FTMP1	/=REQUESTED RATE IN HZ.\r
			/FAC=OVRFLO COUNT;\r
	FSUB F4096	/MUST BE MODULO 12 BITS.\r
	JLE GOTR	/FOUND IT\r
	JXN LOP0,OVRFLO+\r
	LDX 0,RATE	/RATE IS TOO SLOW, STOP\r
			/CLOCK.\r
GOTR,	FADD F4096	/RESTORE\r
	FSTA TOVR\r
	ATX OVRFLO	/OVER FLOW COUNT\r
	TRAP4 SETCLK	/GO START CLOCK\r
	JA GOBAK		/RTN TO CALLER\r
ITSEXT,	LDX 6,RATE	/=RATE FOR EXT CLK\r
	FLDA% FTMP1	/REQUESTED RATE IS\r
			/INTERPRETED AS OVRFLO\r
	JA GOTR+1	/WHEN RATE IS EXTERNAL\r
\f/MAGIC TABLE USED BY SETCLK TO SET CLOCK ENABLE\r
/BITS. EVEN NUMBERED ENTRIES ARE FOR THE DK8ES;\r
/ODD NUMBERED ONES ARE FOR THE KW12A.\r
 \r
CLKTBL,\r
	IFNSW	4 <\r
	0675	>	/"STANDARD" DK BITS\r
	IFSW	4 <\r
	0670	>	/ MODE BITS 10\r
	300		/STND KW BITS\r
	1		/DK STRIG1 BIT\r
	60		/KW STRIG1 BITS\r
	2		/DK S2\r
	14		/KW S2\r
	4		/S3\r
P3,	3		/S3\r
	40		/DK ADC ON OVR BIT\r
	400		/KW ADC ON OVR BIT\r
 \r
			/IF NOT NEXT PAGE DO ORG\r
	IFNEG .-200 < ORG .-SYNC&7600+200+SYNC >\r
\fSETCLK,	0		/TRAP HERE TO START CLK\r
			/THIS ROUT HANDLES BOTH\r
			/DK8ES AND KW12A.\r
	CLLR		/STOP KW AND SET MODE 0;\r
			/NOP FOR DK.\r
	CLEN		/CLR KW12 ENABLE OR\r
			/READ DK ENABLE.\r
	CLA\r
	TAD P7540	/TOGGLE KW MODE 0 TO 1 TO\r
	CLLR		/CLR CLK COUNTER, OR SET\r
			/DK ENABLE BITS, RATE FOR\r
	CLA CMA		/BOTH NOW=7=STOP.\r
	CLZE		/CLR ALL DK ENABLE BITS,\r
	CLSA		/CLR STATUS OF BOTH, ALL \r
	CLA		/IS NOW CLEAR.\r
	TAD FCNTBL+1	/SET PTR TO CLKTBL FOR\r
			/SETTING OF ENABLE REGS.\r
	TAD CPTYP	/=0 IF PDP8 =1 IF PDP12\r
	DCA FCNPTR	/TBL ENTRIES ALTERNATE\r
			/FOR 8 AND 12. CPTYP SETS\r
			/PTR TO 1ST 8 OR 1ST 12\r
			/ENTRY\r
	TAD IDOCLK	/(AC=JMP AROUND). THE\r
			/FOLLOWING IS ONCE ONLY\r
			/CODE. THESE LOCS ARE\r
			/SUBSEQUENTLY USED AS\r
			/OPERANDS\r
	DCA .-1\r
			/THE TAG "ISVBIT" MUST BE\r
			/IN FRONT OF THE STRIG\r
			/FLAGS (STFLG) TO COVER\r
			/THE ILLEGAL CASE OF\r
			/STRIG 0 IN A FORT CALL\r
			/TO SYNC.\r
ISVBIT,	TAD CPTYP	/(AC=0,1) MAKE THE INST\r
			/RAR CLL (FOR DK) OR THE\r
			/INST RTR CLL FOR IDOCLK;\r
STFLG,	RAL CLL		/BECAUSE STATUS BITS FOR\r
	TAD RARCLL	/STRIGS DIFFER ON DK,KW.\r
	DCA LOP2+1	/SEE SUB IDOCLK.\r
			/THE ABOVE 3 LOCS ARE\r
			/SCHMITT TRIGGER FLAGS.\r
			/THE ORDER IS S1,S2,S3\r
			/FOR PDP8 AND S3,S2,S1\r
			/FOR PDP12. THE MAIN\r
			/REASON FOR REVERSING\r
			/THE ORDER IS BECAUSE\r
			/ENGINEERS NEVER CONSULT\r
			/PROGRAMMERS WHEN THEY\r
			/ARE BUILDING NEW \r
			/HARDWARE (CHK THE STATUS\r
			/BITS FOR DK AND KW).\r
	JMS% KONQI+1	/PUT CLOCK ON THE\r
ITMP0,	CLSK		/INTERRUPT QUE\r
			/VIA ONQI.\r
CLENAB,	ADDR IDOCLK	/THIS LOC WILL HOLD THE\r
			/ENABLE BITS FOR DK,KW\r
AROUND,	TAD RATE	/(AC=0,2,3,4,5,6) RATE IS\r
			/SET BY FPP\r
	RTR CLL		/START TO POSITION RATE\r
	RAR		/BITS. B3-B5 FOR DK\r
			/B0-B2 FOR KW\r
	TAD CPTYP	/(THIS IS TRICKY) NEED\r
	RAR		/CPTYP IN LNK BECAUSE\r
			/POSITION OF RATE BITS\r
			/DIFFER FOR DK KW.\r
	TAD% FCNPTR	/AC="STANDARD"\r
			/ENABLE BITS FOR DK,KW.\r
	SZL		/IF ITS A KW THE RATE AND\r
			/AND STND BITS ARE ALREADY\r
			/POSITIONED AS FOLLOWS:\r
			/RRR011000000\r
			/B0-B3 AND B5 WILL GO TO\r
			/KW CONTROL. B4,B5 WILL\r
			/GO TO ENABLE. B3 IS ADC\r
			/ON OVRFLO AND MAY BE SET\r
			/BELOW. B5 ON CONTROL IS\r
			/MODE 1. B4 AND B5 ON\r
			/ENABLE ARE BUFF PRESET TO\r
			/CLOCK COUNTER AND INTRUPT\r
			/ON OVRFLO RESPECTIVELY.\r
	JMP NOBIT-1	/ITS KW GO PUT IN CLENAB.\r
	RAR STL		/ITS DK; POSITION RATE TO\r
	RTR		/B3-B5. NOTE THAT THE LNK\r
			/(CPTYP=0) IS BEING USED.\r
	CMA		/NOTE ALSO THAT THE RATE\r
			/AND STND BITS ARE THE 1S\r
			/COMP. OF WHAT THEY SHOULD\r
			/BE, IE CPTYP=LNK=0\r
			/BECOMES\r
			/B2=1 OF ENABLE=BUFF\r
			/PRESET TO CLK CNTR ON\r
			/OVERFLO. LOOK AT THE RATE\r
			/BITS IN THE HANDBOOK FOR\r
			/BOTH DK,KW. R2,R5\r
			/FOR DK IS 100HZ, 100KHZ\r
			/RESPECTIVELY. R2,R5 FOR\r
			/KW IS 100KHZ,100HZ.\r
			/1S COMP.OF 2=5 ETC.\r
			/SMARTEN UP STEVE!\r
			/THE FINAL VALUE OF THE\r
			/STND DK ENABLE BITS (1ST\r
			/ENTRY IN CLKTBL) IS LEFT\r
			/AS AN EXERCISE FOR THE\r
			/PROGRAMMER.\r
	JMP NOBIT-1	/GO PUT IN CLENAB\r
LOP1,	RAR CLL		/ROT 1 FCN BIT INTO LNK.\r
			/B7=EXT CLK AND IS\r
			/IGNORED HERE. B8=ADC ON\r
			/OVRFLO, B9-B11 ARE STRIG3\r
			/-STRIG1 RESP. BX=1=ENABLE\r
			/FCN. 0=DISABLE\r
	DCA FCNWD	/PUT IT BACK (FCNWD IS\r
			/SET BY FPP)\r
	SNL		/ENABLE FCN ?\r
	JMP NOBIT	/NO\r
	TAD% FCNPTR	/GET BITS FROM THE MAGIC\r
	TAD CLENAB	/TABLE.\r
	DCA CLENAB	/UPDATE ENABLE WORD.\r
NOBIT,	ISZ FCNPTR	/ADV TO NEXT\r
	ISZ FCNPTR	/TBL ENTRY.\r
	TAD FCNWD	/WHEN FCNWD GOES TO 0\r
	AND P17		/WE ARE ALL DONE.\r
			/THE "AND" IS DONE TO\r
			/PROTECT AGAINST A BAD\r
			/ARG FROM THE FORT CALL.\r
			/IN A FRIENDLY ENIVORN,\r
			/ITS NOT NECESSARY.\r
			/NEVER TRUST A FORTRAN\r
			/"PROGRAMMER".\r
P7540,	SMA SZA		/SMA IS SUPERFLOUS TO\r
			/THE ROUT; BUT IT\r
			/CREATES A NICE CONST.\r
	JMP LOP1	/MORE TO DO\r
	DCA STFLG	/CLR THE SCHMITT\r
	DCA STFLG+1	/TRIGGER FLAGS.\r
	DCA STFLG+2\r
	TAD OVRFLO	/SET BUFF PRESET\r
	CIA		/(FPP SET THIS ARG)\r
	IFNSW 4 <\r
	CLAB  >		/ SET PRESET COUNTER\r
	CLA\r
	IFSW	4 <	/ ZERO PRESET COUNTER\r
	CLAB	>\r
	TAD CLENAB	/THIS IS FOR KW ONLY.\r
	AND P377	/AC=3XX. 3= OR BUFF PRE\r
			/INTO CLK CNTR AND ENAB\r
			/INT ON OVRFLO.\r
			/XX ARE THE STRIGS.\r
	CLEN		/SET KW ENABLE OR\r
	CLA		/READ DK ENABLE.\r
	DCA OVRCNT+1	/CLR NUM OF CLK OVRFLOS\r
	DCA OVRCNT	/SINCE TIME 0.\r
	TAD CPTYP	/NEED TYPE IN ORDER TO\r
RARCLL,	RAR CLL		/ISOLATE CONTROL\r
	TAD CLENAB	/BITS FOR\r
	SZL		/KW ?\r
	AND P7540	/YES, B0-B2 IS RATE,\r
			/B3 IS ADC, B5 IS BUFF\r
			/PRE TO CLK CNTR ON\r
			/OVRFLO, B6 IS MOX NIX.\r
			/IF DK ALL BITS MAY HAVE\r
			/MEANING\r
	CLLR		/START THE CLOCK\r
	CLA\r
	CIF CDF\r
	JMP% SETCLK	/RTN TO RTS\r
\fDOSYNC,	0		/HERE TO DISPOSITION A\r
			/A SCHMITT TRIGGER.\r
	TAD CPTYP	/DK AND KW FLAGS ARE IN\r
	RAR CLL		/REVERSE ORDER. IF DK\r
			/ARG IS OK; IF KW THEN\r
			/MUST SET 1=3, 2=2, 3=1\r
			/TO GET INDEX TO\r
			/CORRECT FLAG.\r
	TAD FCNWD	/=REQUESTED STRIG=1,2,3\r
			/(SET BY FPP)\r
	SZL		/DK ?\r
	CIA		/NO KW\r
	AND P3		/IE 1 GOES TO -1 GOES\r
			/TO 3 ETC. "AND" ALSO\r
			/INSURES RANGE IS 0-3.\r
			/IF ARG IS 0 RESULT IS\r
			/ALWAYS 0.\r
	TAD KSTFLG+1	/GET PTR TO FLAG\r
	DCA SETCLK\r
	TAD% SETCLK	/FLAG=0 IF TRIG HAS NOT\r
			/TRIPPED SINCE THE LAST\r
			/CALL TO SYNC; =1\r
			/OTHERWISE IE RTN 0=FALSE\r
	DCA FCNWD	/,1=TRUE (FPP WILL PICK\r
			/ UP FCNWD)\r
	DCA% SETCLK	/CLR FLAG ANYWAY\r
	CIF CDF\r
	JMP% DOSYNC	/RTN TO RTS\r
\f/	INTERRUPT SERVICE ROUTINE\r
/\r
IDOCLK,	JMP AROUND	/HERE ON CLOCK INTERRUPT\r
			/(JMP AROUND IS A ONCE\r
			/ONLY CONSTANT).\r
	TAD KSTFLG+1	/SET PTR TO STRIG FLAGS.\r
	DCA ITMP0\r
	CLSA		/GET CLOCK BITS.\r
	IFREF	CSTAT <\r
	DCAZ CSTAT	/SAVE THEM FOR SOME\r
	TADZ CSTAT	/BODY ELSE.\r
	>\r
	IFNDEF	CSTAT <\r
	JMP	.+2	/ WE DO NOT SAVE STATUS OF SECOND CLOCK\r
	NOP	>\r
	SPA		/OVER FLOW ?\r
	ISZ OVRCNT+1	/YES BUMP LO ORD CNTR\r
	SKP\r
	ISZ OVRCNT	/BUMP HI ORD\r
	JMP DOTRIG	/(HI ORD ISZ SKP IS\r
			/HARMLESS)\r
LOP2,	ISZ ITMP0	/ADV STRIG FLAG PTR.\r
	RAR CLL		/(OR RTR CLL IF KW)\r
			/IE PUT STRIG BIT IN LNK.\r
			/IF DK THE ORDER OF\r
			/INTERROGATION IS S1,S2,S3\r
			/IF KW THE ORDER IS S3,\r
			/S2,S1. THE STATUS BITS\r
			/FOR DK ARE ADJACENT IE\r
			/ B9(S3),B10(S2),B11(S1)\r
			/FOR KW ITS EVERY OTHER,\r
			/B6(S1),B8(S2),B10(S3).\r
	DCA ISVBIT	/SAVE WHATS LEFT.\r
/	RAL		/COPY LNK INTO FLAG IF=1\r
/	SZA		/IE DONT CLR FLAG WHEN\r
/	DCA% ITMP0	/ITS SET.\r
/\r
	SZL		/ HERE WE COUNT THE NUMBER OF EVENTS BETWEEN\r
	ISZ% ITMP0	/  CALL TO SYNC ROUTINE (NO OVERFLOW PROTECTION!)\r
	ISZ% ITMP0	/ HERE TO PROTECT ISZ\r
/\r
	TAD ISVBIT\r
DOTRIG,	AND P377	/THE "AND" INSURES THAT\r
			/THE HI ORD BITS ARE\r
			/CLRED SO THAT ISVBIT\r
			/GOES TO 0 WHEN ALL\r
			/STRIGS HAVE BEEN\r
			/DISPOSITIONED. IE\r
			/CLR OVRFLO BIT FOR DK,KW\r
			/AND CLR PRE-EVENT BIT\r
			/ON KW  IF IT IS SET\r
	SZA		/DONE ?\r
	JMP LOP2	/NO\r
	TAD CLINT	/CALL USER EXTENDED\r
	SZA CLA		/CLOCK ROUT ?\r
	JMS% CLINT+1	/YES\r
	JMP% IDOCLK	/RTN TO IHANDL\r
\fFCNPTR,\r
OVRCNT,\r
KONQI,	ADDR ONQI\r
P17,	17\r
P377,	377\r
FCNWD,	0		/FPP XRS\r
CPTYP,	0\r
RATE,	0\r
P1,	1\r
P2,	2\r
OVRFLO,\r
FCNTBL,	ADDR CLKTBL\r
KSTFLG,	ADDR STFLG-1\r
	IFNSW	1 <\r
#CLINT,	0;0\r
CLINT=	#CLINT >\r
	IFSW	1 <\r
#CLIN1,	0;0\r
CLINT=	#CLIN1 >\r
	IFNSW   4 <\r
	IFSW	2 <\r
/	ENTRY TIME	/FIGURE WHAT TIME IT IS\r
TIME,	>\r
	>\r
	JSA SETUP\r
	FLDA RPTR	/=27;X;X IS USED TO FLOAT\r
	STARTD\r
	FLDA# OVRCNT	/NUM OF CLK OVRFLOS SINCE\r
	STARTF		/TIME 0\r
	FNORM\r
	FMUL TOVR	/=NUM OF BASIC TICKS PER\r
			/CLOCK OVER FLOW.\r
			/FAC=NUM OF TICKS SINCE\r
			/TIME 0.\r
	FDIV% RPTR,RATE	/DIV BY BASIC RATE IN HZ\r
			/OR 1 IF EXTERNAL CLK.\r
	FSTA% FTMP0	/GIVE ANS TO CALLER, ALSO\r
			/LEAVE ANS IN FAC IN\r
			/CASE TIME WAS A FCN\r
			/CALL. ANS=ELAPSED TIME IN\r
			/SECONDS SINCE TIME 0 OR\r
			/NUM OF EXTERNAL UNIT\r
	JA GOBAK	/TICKS\r
\f\1a\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0
Commit	Line	Data
81e70d48 PH	1	/ \ eCLOCK.RA - DK8-EP HANDLER\r
	2	/\r
	3	/ TO ASSEMBLE DK8-EP HANDLER FOR FIRST CLOCK: NO SWITCHES\r
	4	/ TO ASSEMBLE DK8-EP HANDLER FOR 2 ND CLOCK: /1 SWITCH\r
	5	/ TO ENABLE TIME ROUTINE TO APPROPIATE CLOCK : /2 SWITCH \r
	6	/ TO ENABLE CLOCK STATUS TO GENERAL RTS ROUTINES: /3 SWITCH\r
	7	/ SO NORMALLY FOR FIRST CLOCK USE /3 SWITCH!\r
	8	/ TO ENABLE CLOCK TO SCHMITT TRIGGER EVENT USE /4 SWITCH\r
	9	/ DO NOT COMBINE /2 AND /4 SWITCHES!\r
	10	/ THIS GENERATES CLOCK4:\r
	11	/ NO PRESET TO DK8-EP\r
	12	/ MODE BITS: 11\r
	13	/ SELECT RATE: N/4096\r
	14	/ APPLICABLE FOR BOTH DK8-EP CLOCKS. BUT ONLY FOR ONE PER PROGRAM!\r
	15	/\r
	16	/\r
	17	/ 1.0 18-MAR-85 H.A. (COPY OF CLOCK.RA )\r
	18	/ 1.1 26-JUN-85 H.A.\r
	19	/\r
	20	EXTERN #DISP /SYSTEM PAGE 0,NEEDED TO\r
	21	/PUT CLOCK STATUS ON PG0\r
	22	/(CSTAT) FOR USE BY GEN\r
	23	/USER CLOCK SERVICE ROUTS\r
	24	EXTERN #T812 /RTS CPTYP\r
	25	EXTERN ONQI /INTERRUPT QUEUER\r
	26	/\r
	27	IFNSW 1 <\r
	28	ENTRY #CLINT /USER EXTENDED CLOCK ROUTINE\r
	29	DEVICE=13*10\r
	30	>\r
	31	IFSW 3 <\r
	32	CSTAT=157 /IDOCLK PUTS CLSA BITS OF FIRST CLOCK\r
	33	/IN HERE FOR SOMEBODY ELSE\r
	34	>\r
	35	IFSW 2 <\r
	36	ENTRY TIME / ENABLE TIME ROUTINE TO RTS\r
	37	>\r
	38	IFSW 1 <\r
	39	ENTRY #CLIN1 /USER EXTENDED CLOCK ROUTINE\r
	40	DEVICE=17*10\r
	41	>\r
	42	CLZE=6000!DEVICE /CLOCK IOTS\r
	43	CLSK=6001!DEVICE\r
	44	CLLR=6002!DEVICE /ALSO CLOE\r
	45	CLAB=6003!DEVICE\r
	46	CLEN=6004!DEVICE\r
	47	CLSA=6005!DEVICE\r
	48	\f BASE FTMP0\r
	49	INDEX FCNWD\r
	50	IFNSW 2 <\r
	51	IFSW 1 <\r
	52	FIELD1 #SYNC >\r
	53	IFSW 4 <\r
	54	FIELD1 SYNC4 >\r
	55	>\r
	56	IFSW 2 <\r
	57	FIELD1 SYNC >\r
	58	BASE FTMP0\r
	59	INDEX FCNWD\r
	60	JSA SETUP /HERE TO READ A STRIG\r
	61	/INITIALIZE ARGS\r
	62	TRAP4 DOSYNC /FCNWD (XR) HOLDS STRIG\r
	63	/TO READ\r
	64	XTA FCNWD /=ANS=0,1\r
65	FSTA% FTMP1 /GIVE ANS TO CALLER\r
66	JA GOBAK\r
67	FTMP0, F 0.0 /BASE PAGE\r
68	FTMP1, F 0.0\r
69	RPTR, 27;ADDR RTBL /PTR TO RATE TBL, ALSO\r
70	/USED TO FLT OVRCNT (NOTE\r
71	/THAT THE EXPONENT=27)\r
72	MINRAT, F .02 /MIN ALLOWABLE RATE\r
73	TOVR, F 0.0\r
74	IFNSW 4 <\r
75	IFNSW 1 <\r
76	NAME, TEXT +CLOCK + >\r
77	IFSW 1 <\r
78	NAME, TEXT +CLOCK1+ >\r
79	>\r
80	IFSW 4 <\r
81	IFNSW 1 <\r
82	NAME, TEXT +CLOCK4+ >\r
83	IFSW 1 <\r
84	NAME, TEXT +CLOC14+ >\r
85	>\r
86	ORG 10*3+FTMP0\r
87	FNOP\r
88	JA NAME+3\r
89	0\r
90	GOBAK, JA .\r
91	RTBL, F 16.0 /CONSTANT USED TO CHK FOR\r
92	/EXT CLK BIT IN FCNWD\r
93	/THIS CONST MUST BE NE 0\r
94	MAXRAT,\r
95	F4096, F 4096.0 /USED TO GET OVRFLO COUNT\r
96	F 100000.0 /FASTEST RATE IN HERTZ\r
97	F 10000.0 /NEXT FASTEST RATE\r
98	F 1000.0\r
99	F 100.0 /SLOWEST RATE\r
100	F 1.0 /USED BY TIME FOR EXT CLK\r
101	\f BASE 0\r
102	\r
103	SETUP, 0;0 /HERE TO INIT ALL FPP SUBS\r
104	STARTD\r
105	FLDA 30 /PICK UP RTN TO CALLER\r
106	FSTA GOBAK\r
107	FLDA 0 /GET PTR TO CALLERS ARGS\r
108	SETX FCNWD /CLOCK XR AND BASE\r
109	SETB FTMP0\r
110	BASE FTMP0\r
111	FSTA FTMP1\r
112	FLDA% FTMP1,P1\r
113	FSTA FTMP0 /PTR TO 1ST ARG\r
114	FLDA% FTMP1,P2\r
115	FSTA FTMP1 /PTR TO 2ND ARG\r
116	FLDA #T812 /TELLS PDP8,PDP12\r
117	ATX CPTYP /0=8=DK8ES,1=12=KW12A\r
118	STARTF\r
119	FLDA% FTMP0 /=1ST ARG\r
120	ATX FCNWD /ALWAYS IN FCNWD\r
121	JA SETUP\r
122	\f IFNSW 4 <\r
123	IFNSW 2 <\r
124	IFNSW 1 <\r
125	ENTRY CLOCK\r
126	CLOCK, > >\r
127	IFSW 1 <\r
128	ENTRY CLOCK1\r
129	CLOCK1, >\r
130	>\r
131	IFSW 2 <\r
132	ENTRY CLOCK\r
133	CLOCK, >\r
134	IFSW 4 <\r
135	IFNSW 1 <\r
136	ENTRY CLOCK4\r
137	CLOCK4, >\r
138	IFSW 1 <\r
139	ENTRY CLOC14\r
140	CLOC14, >\r
141	>\r
142	JSA SETUP /HERE FOR CLOCK START\r
143	FLDA% FTMP0\r
144	FSUB RTBL /FCNWD IS IN FAC,IF GE 16\r
145	JGE ITSEXT /(RTBL=16.0) THEN USER IS\r
146	/REQUESTING AN EXTERNAL\r
147	/CLOCK I.E. B8 OF FCNWD\r
148	/IS SET.\r
149	FLDA% FTMP1 /=REQUESTED RATE IN HERTZ\r
150	FSUB MINRAT /.LE. MINUMUM RATE\r
151	JLE GOTR-2 /MEANS STOP CLOCK.\r
152	FADD MINRAT\r
153	FSUB MAXRAT /CHK FOR TOO FAST\r
154	JGT GOTR-2\r
155	LDX -4,OVRFLO /THERE ARE 4 BASIC RATES\r
156	LDX 1,RATE /=INDEX INTO RTBL; UPON\r
157	/TRAP(CLOCK) RATE=(0,\r
158	/2,3,4,5,6) 0=STOP,\r
159	/6=EXTERNAL\r
160	/2-5=PROGRAMMABLE RATES\r
161	LOP0, FLDA% RPTR,RATE+\r
162	/GET NEXT SLOWEST RATE\r
163	FDIV% FTMP1 /=REQUESTED RATE IN HZ.\r
164	/FAC=OVRFLO COUNT;\r
165	FSUB F4096 /MUST BE MODULO 12 BITS.\r
166	JLE GOTR /FOUND IT\r
167	JXN LOP0,OVRFLO+\r
168	LDX 0,RATE /RATE IS TOO SLOW, STOP\r
169	/CLOCK.\r
170	GOTR, FADD F4096 /RESTORE\r
171	FSTA TOVR\r
172	ATX OVRFLO /OVER FLOW COUNT\r
173	TRAP4 SETCLK /GO START CLOCK\r
174	JA GOBAK /RTN TO CALLER\r
175	ITSEXT, LDX 6,RATE /=RATE FOR EXT CLK\r
176	FLDA% FTMP1 /REQUESTED RATE IS\r
177	/INTERPRETED AS OVRFLO\r
178	JA GOTR+1 /WHEN RATE IS EXTERNAL\r
179	\f/MAGIC TABLE USED BY SETCLK TO SET CLOCK ENABLE\r
180	/BITS. EVEN NUMBERED ENTRIES ARE FOR THE DK8ES;\r
181	/ODD NUMBERED ONES ARE FOR THE KW12A.\r
182	\r
183	CLKTBL,\r
184	IFNSW 4 <\r
185	0675 > /"STANDARD" DK BITS\r
186	IFSW 4 <\r
187	0670 > / MODE BITS 10\r
188	300 /STND KW BITS\r
189	1 /DK STRIG1 BIT\r
190	60 /KW STRIG1 BITS\r
191	2 /DK S2\r
192	14 /KW S2\r
193	4 /S3\r
194	P3, 3 /S3\r
195	40 /DK ADC ON OVR BIT\r
196	400 /KW ADC ON OVR BIT\r
197	\r
198	/IF NOT NEXT PAGE DO ORG\r
199	IFNEG .-200 < ORG .-SYNC&7600+200+SYNC >\r
200	\fSETCLK, 0 /TRAP HERE TO START CLK\r
201	/THIS ROUT HANDLES BOTH\r
202	/DK8ES AND KW12A.\r
203	CLLR /STOP KW AND SET MODE 0;\r
204	/NOP FOR DK.\r
205	CLEN /CLR KW12 ENABLE OR\r
206	/READ DK ENABLE.\r
207	CLA\r
208	TAD P7540 /TOGGLE KW MODE 0 TO 1 TO\r
209	CLLR /CLR CLK COUNTER, OR SET\r
210	/DK ENABLE BITS, RATE FOR\r
211	CLA CMA /BOTH NOW=7=STOP.\r
212	CLZE /CLR ALL DK ENABLE BITS,\r
213	CLSA /CLR STATUS OF BOTH, ALL \r
214	CLA /IS NOW CLEAR.\r
215	TAD FCNTBL+1 /SET PTR TO CLKTBL FOR\r
216	/SETTING OF ENABLE REGS.\r
217	TAD CPTYP /=0 IF PDP8 =1 IF PDP12\r
218	DCA FCNPTR /TBL ENTRIES ALTERNATE\r
219	/FOR 8 AND 12. CPTYP SETS\r
220	/PTR TO 1ST 8 OR 1ST 12\r
221	/ENTRY\r
222	TAD IDOCLK /(AC=JMP AROUND). THE\r
223	/FOLLOWING IS ONCE ONLY\r
224	/CODE. THESE LOCS ARE\r
225	/SUBSEQUENTLY USED AS\r
226	/OPERANDS\r
227	DCA .-1\r
228	/THE TAG "ISVBIT" MUST BE\r
229	/IN FRONT OF THE STRIG\r
230	/FLAGS (STFLG) TO COVER\r
231	/THE ILLEGAL CASE OF\r
232	/STRIG 0 IN A FORT CALL\r
233	/TO SYNC.\r
234	ISVBIT, TAD CPTYP /(AC=0,1) MAKE THE INST\r
235	/RAR CLL (FOR DK) OR THE\r
236	/INST RTR CLL FOR IDOCLK;\r
237	STFLG, RAL CLL /BECAUSE STATUS BITS FOR\r
238	TAD RARCLL /STRIGS DIFFER ON DK,KW.\r
239	DCA LOP2+1 /SEE SUB IDOCLK.\r
240	/THE ABOVE 3 LOCS ARE\r
241	/SCHMITT TRIGGER FLAGS.\r
242	/THE ORDER IS S1,S2,S3\r
243	/FOR PDP8 AND S3,S2,S1\r
244	/FOR PDP12. THE MAIN\r
245	/REASON FOR REVERSING\r
246	/THE ORDER IS BECAUSE\r
247	/ENGINEERS NEVER CONSULT\r
248	/PROGRAMMERS WHEN THEY\r
249	/ARE BUILDING NEW \r
250	/HARDWARE (CHK THE STATUS\r
251	/BITS FOR DK AND KW).\r
252	JMS% KONQI+1 /PUT CLOCK ON THE\r
253	ITMP0, CLSK /INTERRUPT QUE\r
254	/VIA ONQI.\r
255	CLENAB, ADDR IDOCLK /THIS LOC WILL HOLD THE\r
256	/ENABLE BITS FOR DK,KW\r
257	AROUND, TAD RATE /(AC=0,2,3,4,5,6) RATE IS\r
258	/SET BY FPP\r
259	RTR CLL /START TO POSITION RATE\r
260	RAR /BITS. B3-B5 FOR DK\r
261	/B0-B2 FOR KW\r
262	TAD CPTYP /(THIS IS TRICKY) NEED\r
263	RAR /CPTYP IN LNK BECAUSE\r
264	/POSITION OF RATE BITS\r
265	/DIFFER FOR DK KW.\r
266	TAD% FCNPTR /AC="STANDARD"\r
267	/ENABLE BITS FOR DK,KW.\r
268	SZL /IF ITS A KW THE RATE AND\r
269	/AND STND BITS ARE ALREADY\r
270	/POSITIONED AS FOLLOWS:\r
271	/RRR011000000\r
272	/B0-B3 AND B5 WILL GO TO\r
273	/KW CONTROL. B4,B5 WILL\r
274	/GO TO ENABLE. B3 IS ADC\r
275	/ON OVRFLO AND MAY BE SET\r
276	/BELOW. B5 ON CONTROL IS\r
277	/MODE 1. B4 AND B5 ON\r
278	/ENABLE ARE BUFF PRESET TO\r
279	/CLOCK COUNTER AND INTRUPT\r
280	/ON OVRFLO RESPECTIVELY.\r
281	JMP NOBIT-1 /ITS KW GO PUT IN CLENAB.\r
282	RAR STL /ITS DK; POSITION RATE TO\r
283	RTR /B3-B5. NOTE THAT THE LNK\r
284	/(CPTYP=0) IS BEING USED.\r
285	CMA /NOTE ALSO THAT THE RATE\r
286	/AND STND BITS ARE THE 1S\r
287	/COMP. OF WHAT THEY SHOULD\r
288	/BE, IE CPTYP=LNK=0\r
289	/BECOMES\r
290	/B2=1 OF ENABLE=BUFF\r
291	/PRESET TO CLK CNTR ON\r
292	/OVERFLO. LOOK AT THE RATE\r
293	/BITS IN THE HANDBOOK FOR\r
294	/BOTH DK,KW. R2,R5\r
295	/FOR DK IS 100HZ, 100KHZ\r
296	/RESPECTIVELY. R2,R5 FOR\r
297	/KW IS 100KHZ,100HZ.\r
298	/1S COMP.OF 2=5 ETC.\r
299	/SMARTEN UP STEVE!\r
300	/THE FINAL VALUE OF THE\r
301	/STND DK ENABLE BITS (1ST\r
302	/ENTRY IN CLKTBL) IS LEFT\r
303	/AS AN EXERCISE FOR THE\r
304	/PROGRAMMER.\r
305	JMP NOBIT-1 /GO PUT IN CLENAB\r
306	LOP1, RAR CLL /ROT 1 FCN BIT INTO LNK.\r
307	/B7=EXT CLK AND IS\r
308	/IGNORED HERE. B8=ADC ON\r
309	/OVRFLO, B9-B11 ARE STRIG3\r
310	/-STRIG1 RESP. BX=1=ENABLE\r
311	/FCN. 0=DISABLE\r
312	DCA FCNWD /PUT IT BACK (FCNWD IS\r
313	/SET BY FPP)\r
314	SNL /ENABLE FCN ?\r
315	JMP NOBIT /NO\r
316	TAD% FCNPTR /GET BITS FROM THE MAGIC\r
317	TAD CLENAB /TABLE.\r
318	DCA CLENAB /UPDATE ENABLE WORD.\r
319	NOBIT, ISZ FCNPTR /ADV TO NEXT\r
320	ISZ FCNPTR /TBL ENTRY.\r
321	TAD FCNWD /WHEN FCNWD GOES TO 0\r
322	AND P17 /WE ARE ALL DONE.\r
323	/THE "AND" IS DONE TO\r
324	/PROTECT AGAINST A BAD\r
325	/ARG FROM THE FORT CALL.\r
326	/IN A FRIENDLY ENIVORN,\r
327	/ITS NOT NECESSARY.\r
328	/NEVER TRUST A FORTRAN\r
329	/"PROGRAMMER".\r
330	P7540, SMA SZA /SMA IS SUPERFLOUS TO\r
331	/THE ROUT; BUT IT\r
332	/CREATES A NICE CONST.\r
333	JMP LOP1 /MORE TO DO\r
334	DCA STFLG /CLR THE SCHMITT\r
335	DCA STFLG+1 /TRIGGER FLAGS.\r
336	DCA STFLG+2\r
337	TAD OVRFLO /SET BUFF PRESET\r
338	CIA /(FPP SET THIS ARG)\r
339	IFNSW 4 <\r
340	CLAB > / SET PRESET COUNTER\r
341	CLA\r
342	IFSW 4 < / ZERO PRESET COUNTER\r
343	CLAB >\r
344	TAD CLENAB /THIS IS FOR KW ONLY.\r
345	AND P377 /AC=3XX. 3= OR BUFF PRE\r
346	/INTO CLK CNTR AND ENAB\r
347	/INT ON OVRFLO.\r
348	/XX ARE THE STRIGS.\r
349	CLEN /SET KW ENABLE OR\r
350	CLA /READ DK ENABLE.\r
351	DCA OVRCNT+1 /CLR NUM OF CLK OVRFLOS\r
352	DCA OVRCNT /SINCE TIME 0.\r
353	TAD CPTYP /NEED TYPE IN ORDER TO\r
354	RARCLL, RAR CLL /ISOLATE CONTROL\r
355	TAD CLENAB /BITS FOR\r
356	SZL /KW ?\r
357	AND P7540 /YES, B0-B2 IS RATE,\r
358	/B3 IS ADC, B5 IS BUFF\r
359	/PRE TO CLK CNTR ON\r
360	/OVRFLO, B6 IS MOX NIX.\r
361	/IF DK ALL BITS MAY HAVE\r
362	/MEANING\r
363	CLLR /START THE CLOCK\r
364	CLA\r
365	CIF CDF\r
366	JMP% SETCLK /RTN TO RTS\r
367	\fDOSYNC, 0 /HERE TO DISPOSITION A\r
368	/A SCHMITT TRIGGER.\r
369	TAD CPTYP /DK AND KW FLAGS ARE IN\r
370	RAR CLL /REVERSE ORDER. IF DK\r
371	/ARG IS OK; IF KW THEN\r
372	/MUST SET 1=3, 2=2, 3=1\r
373	/TO GET INDEX TO\r
374	/CORRECT FLAG.\r
375	TAD FCNWD /=REQUESTED STRIG=1,2,3\r
376	/(SET BY FPP)\r
377	SZL /DK ?\r
378	CIA /NO KW\r
379	AND P3 /IE 1 GOES TO -1 GOES\r
380	/TO 3 ETC. "AND" ALSO\r
381	/INSURES RANGE IS 0-3.\r
382	/IF ARG IS 0 RESULT IS\r
383	/ALWAYS 0.\r
384	TAD KSTFLG+1 /GET PTR TO FLAG\r
385	DCA SETCLK\r
386	TAD% SETCLK /FLAG=0 IF TRIG HAS NOT\r
387	/TRIPPED SINCE THE LAST\r
388	/CALL TO SYNC; =1\r
389	/OTHERWISE IE RTN 0=FALSE\r
390	DCA FCNWD /,1=TRUE (FPP WILL PICK\r
391	/ UP FCNWD)\r
392	DCA% SETCLK /CLR FLAG ANYWAY\r
393	CIF CDF\r
394	JMP% DOSYNC /RTN TO RTS\r
395	\f/ INTERRUPT SERVICE ROUTINE\r
396	/\r
397	IDOCLK, JMP AROUND /HERE ON CLOCK INTERRUPT\r
398	/(JMP AROUND IS A ONCE\r
399	/ONLY CONSTANT).\r
400	TAD KSTFLG+1 /SET PTR TO STRIG FLAGS.\r
401	DCA ITMP0\r
402	CLSA /GET CLOCK BITS.\r
403	IFREF CSTAT <\r
404	DCAZ CSTAT /SAVE THEM FOR SOME\r
405	TADZ CSTAT /BODY ELSE.\r
406	>\r
407	IFNDEF CSTAT <\r
408	JMP .+2 / WE DO NOT SAVE STATUS OF SECOND CLOCK\r
409	NOP >\r
410	SPA /OVER FLOW ?\r
411	ISZ OVRCNT+1 /YES BUMP LO ORD CNTR\r
412	SKP\r
413	ISZ OVRCNT /BUMP HI ORD\r
414	JMP DOTRIG /(HI ORD ISZ SKP IS\r
415	/HARMLESS)\r
416	LOP2, ISZ ITMP0 /ADV STRIG FLAG PTR.\r
417	RAR CLL /(OR RTR CLL IF KW)\r
418	/IE PUT STRIG BIT IN LNK.\r
419	/IF DK THE ORDER OF\r
420	/INTERROGATION IS S1,S2,S3\r
421	/IF KW THE ORDER IS S3,\r
422	/S2,S1. THE STATUS BITS\r
423	/FOR DK ARE ADJACENT IE\r
424	/ B9(S3),B10(S2),B11(S1)\r
425	/FOR KW ITS EVERY OTHER,\r
426	/B6(S1),B8(S2),B10(S3).\r
427	DCA ISVBIT /SAVE WHATS LEFT.\r
428	/ RAL /COPY LNK INTO FLAG IF=1\r
429	/ SZA /IE DONT CLR FLAG WHEN\r
430	/ DCA% ITMP0 /ITS SET.\r
431	/\r
432	SZL / HERE WE COUNT THE NUMBER OF EVENTS BETWEEN\r
433	ISZ% ITMP0 / CALL TO SYNC ROUTINE (NO OVERFLOW PROTECTION!)\r
434	ISZ% ITMP0 / HERE TO PROTECT ISZ\r
435	/\r
436	TAD ISVBIT\r
437	DOTRIG, AND P377 /THE "AND" INSURES THAT\r
438	/THE HI ORD BITS ARE\r
439	/CLRED SO THAT ISVBIT\r
440	/GOES TO 0 WHEN ALL\r
441	/STRIGS HAVE BEEN\r
442	/DISPOSITIONED. IE\r
443	/CLR OVRFLO BIT FOR DK,KW\r
444	/AND CLR PRE-EVENT BIT\r
445	/ON KW IF IT IS SET\r
446	SZA /DONE ?\r
447	JMP LOP2 /NO\r
448	TAD CLINT /CALL USER EXTENDED\r
449	SZA CLA /CLOCK ROUT ?\r
450	JMS% CLINT+1 /YES\r
451	JMP% IDOCLK /RTN TO IHANDL\r
452	\fFCNPTR,\r
453	OVRCNT,\r
454	KONQI, ADDR ONQI\r
455	P17, 17\r
456	P377, 377\r
457	FCNWD, 0 /FPP XRS\r
458	CPTYP, 0\r
459	RATE, 0\r
460	P1, 1\r
461	P2, 2\r
462	OVRFLO,\r
463	FCNTBL, ADDR CLKTBL\r
464	KSTFLG, ADDR STFLG-1\r
465	IFNSW 1 <\r
466	#CLINT, 0;0\r
467	CLINT= #CLINT >\r
468	IFSW 1 <\r
469	#CLIN1, 0;0\r
470	CLINT= #CLIN1 >\r
471	IFNSW 4 <\r
472	IFSW 2 <\r
473	/ ENTRY TIME /FIGURE WHAT TIME IT IS\r
474	TIME, >\r
475	>\r
476	JSA SETUP\r
477	FLDA RPTR /=27;X;X IS USED TO FLOAT\r
478	STARTD\r
479	FLDA# OVRCNT /NUM OF CLK OVRFLOS SINCE\r
480	STARTF /TIME 0\r
481	FNORM\r
482	FMUL TOVR /=NUM OF BASIC TICKS PER\r
483	/CLOCK OVER FLOW.\r
484	/FAC=NUM OF TICKS SINCE\r
485	/TIME 0.\r
486	FDIV% RPTR,RATE /DIV BY BASIC RATE IN HZ\r
487	/OR 1 IF EXTERNAL CLK.\r
488	FSTA% FTMP0 /GIVE ANS TO CALLER, ALSO\r
489	/LEAVE ANS IN FAC IN\r
490	/CASE TIME WAS A FCN\r
491	/CALL. ANS=ELAPSED TIME IN\r
492	/SECONDS SINCE TIME 0 OR\r
493	/NUM OF EXTERNAL UNIT\r
494	JA GOBAK /TICKS\r
495	\f\1a\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0