| 1 | /* altairz80_cpu.c: MITS Altair CPU (8080 and Z80)\r |
| 2 | \r |
| 3 | Copyright (c) 2002-2008, Peter Schorn\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | PETER SCHORN BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Peter Schorn shall not\r |
| 23 | be used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Peter Schorn.\r |
| 25 | \r |
| 26 | Based on work by Charles E Owen (c) 1997\r |
| 27 | Code for Z80 CPU from Frank D. Cringle ((c) 1995 under GNU license)\r |
| 28 | */\r |
| 29 | \r |
| 30 | #include "altairz80_defs.h"\r |
| 31 | #include <ctype.h>\r |
| 32 | #define SWITCHCPU_DEFAULT 0xfd\r |
| 33 | \r |
| 34 | #if defined (_WIN32)\r |
| 35 | #include <windows.h>\r |
| 36 | #else\r |
| 37 | #include <unistd.h>\r |
| 38 | #endif\r |
| 39 | \r |
| 40 | #define PCQ_SIZE 64 /* must be 2**n */\r |
| 41 | #define PCQ_SIZE_LOG2 6 /* log2 of PCQ_SIZE */\r |
| 42 | #define PCQ_MASK (PCQ_SIZE - 1)\r |
| 43 | #define PCQ_ENTRY(PC) if (pcq[pcq_p] != (PC)) { pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = (PC); }\r |
| 44 | \r |
| 45 | #define FLAG_C 1\r |
| 46 | #define FLAG_N 2\r |
| 47 | #define FLAG_P 4\r |
| 48 | #define FLAG_H 16\r |
| 49 | #define FLAG_Z 64\r |
| 50 | #define FLAG_S 128\r |
| 51 | \r |
| 52 | #define SETFLAG(f,c) AF = (c) ? AF | FLAG_ ## f : AF & ~FLAG_ ## f\r |
| 53 | #define TSTFLAG(f) ((AF & FLAG_ ## f) != 0)\r |
| 54 | \r |
| 55 | #define LOW_DIGIT(x) ((x) & 0xf)\r |
| 56 | #define HIGH_DIGIT(x) (((x) >> 4) & 0xf)\r |
| 57 | #define LOW_REGISTER(x) ((x) & 0xff)\r |
| 58 | #define HIGH_REGISTER(x) (((x) >> 8) & 0xff)\r |
| 59 | \r |
| 60 | #define SET_LOW_REGISTER(x, v) x = (((x) & 0xff00) | ((v) & 0xff))\r |
| 61 | #define SET_HIGH_REGISTER(x, v) x = (((x) & 0xff) | (((v) & 0xff) << 8))\r |
| 62 | \r |
| 63 | #define PARITY(x) parityTable[(x) & 0xff]\r |
| 64 | /* SET_PV and SET_PV2 are used to provide correct PARITY flag semantics for the 8080 in cases\r |
| 65 | where the Z80 uses the overflow flag\r |
| 66 | */\r |
| 67 | #define SET_PVS(s) ((chiptype == CHIP_TYPE_Z80) ? (((cbits >> 6) ^ (cbits >> 5)) & 4) : (PARITY(s)))\r |
| 68 | #define SET_PV (SET_PVS(sum))\r |
| 69 | #define SET_PV2(x) ((chiptype == CHIP_TYPE_Z80) ? (((temp == (x)) << 2)) : (PARITY(temp)))\r |
| 70 | \r |
| 71 | /* CHECK_CPU_8080 must be invoked whenever a Z80 only instruction is executed\r |
| 72 | In case a Z80 instruction is executed on an 8080 the following two cases exist:\r |
| 73 | 1) Trapping is enabled: execution stops\r |
| 74 | 2) Trapping is not enabled: decoding continues with the next byte\r |
| 75 | */\r |
| 76 | #define CHECK_CPU_8080 \\r |
| 77 | if (chiptype == CHIP_TYPE_8080) { \\r |
| 78 | if (cpu_unit.flags & UNIT_CPU_OPSTOP) { \\r |
| 79 | reason = STOP_OPCODE; \\r |
| 80 | goto end_decode; \\r |
| 81 | } \\r |
| 82 | else { \\r |
| 83 | sim_brk_pend[0] = FALSE; \\r |
| 84 | continue; \\r |
| 85 | } \\r |
| 86 | }\r |
| 87 | \r |
| 88 | /* CHECK_CPU_Z80 must be invoked whenever a non Z80 instruction is executed */\r |
| 89 | #define CHECK_CPU_Z80 \\r |
| 90 | if (cpu_unit.flags & UNIT_CPU_OPSTOP) { \\r |
| 91 | reason = STOP_OPCODE; \\r |
| 92 | goto end_decode; \\r |
| 93 | }\r |
| 94 | \r |
| 95 | #define POP(x) { \\r |
| 96 | register uint32 y = RAM_PP(SP); \\r |
| 97 | x = y + (RAM_PP(SP) << 8); \\r |
| 98 | }\r |
| 99 | \r |
| 100 | #define JPC(cond) { \\r |
| 101 | tStates += 10; \\r |
| 102 | if (cond) { \\r |
| 103 | PCQ_ENTRY(PCX); \\r |
| 104 | PC = GET_WORD(PC); \\r |
| 105 | } \\r |
| 106 | else { \\r |
| 107 | PC += 2; \\r |
| 108 | } \\r |
| 109 | }\r |
| 110 | \r |
| 111 | #define CALLC(cond) { \\r |
| 112 | if (cond) { \\r |
| 113 | register uint32 adrr = GET_WORD(PC); \\r |
| 114 | CHECK_BREAK_WORD(SP - 2); \\r |
| 115 | PUSH(PC + 2); \\r |
| 116 | PCQ_ENTRY(PCX); \\r |
| 117 | PC = adrr; \\r |
| 118 | tStates += 17; \\r |
| 119 | } \\r |
| 120 | else { \\r |
| 121 | sim_brk_pend[0] = FALSE; \\r |
| 122 | PC += 2; \\r |
| 123 | tStates += 10; \\r |
| 124 | } \\r |
| 125 | }\r |
| 126 | \r |
| 127 | extern int32 sim_int_char;\r |
| 128 | extern int32 sio0s (const int32 port, const int32 io, const int32 data);\r |
| 129 | extern int32 sio0d (const int32 port, const int32 io, const int32 data);\r |
| 130 | extern int32 sio1s (const int32 port, const int32 io, const int32 data);\r |
| 131 | extern int32 sio1d (const int32 port, const int32 io, const int32 data);\r |
| 132 | extern int32 dsk10 (const int32 port, const int32 io, const int32 data);\r |
| 133 | extern int32 dsk11 (const int32 port, const int32 io, const int32 data);\r |
| 134 | extern int32 dsk12 (const int32 port, const int32 io, const int32 data);\r |
| 135 | extern int32 netStatus (const int32 port, const int32 io, const int32 data);\r |
| 136 | extern int32 netData (const int32 port, const int32 io, const int32 data);\r |
| 137 | extern int32 nulldev (const int32 port, const int32 io, const int32 data);\r |
| 138 | extern int32 hdsk_io (const int32 port, const int32 io, const int32 data);\r |
| 139 | extern int32 simh_dev (const int32 port, const int32 io, const int32 data);\r |
| 140 | extern int32 sr_dev (const int32 port, const int32 io, const int32 data);\r |
| 141 | extern void install_ALTAIRbootROM(void);\r |
| 142 | extern char messageBuffer[];\r |
| 143 | extern void printMessage(void);\r |
| 144 | extern void do_SIMH_sleep(void);\r |
| 145 | \r |
| 146 | extern t_stat sim_instr_nommu(void);\r |
| 147 | extern uint8 MOPT[MAXBANKSIZE];\r |
| 148 | extern t_stat sim_instr_8086(void);\r |
| 149 | extern t_stat sim_instr_8086(void);\r |
| 150 | extern void cpu8086reset(void);\r |
| 151 | \r |
| 152 | /* function prototypes */\r |
| 153 | #ifdef CPUSWITCHER\r |
| 154 | static t_stat cpu_set_switcher (UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 155 | static t_stat cpu_reset_switcher(UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 156 | static t_stat cpu_show_switcher (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 157 | static int32 switchcpu_io (const int32 port, const int32 io, const int32 data);\r |
| 158 | #endif\r |
| 159 | \r |
| 160 | static t_stat cpu_set_altairrom (UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 161 | static t_stat cpu_set_noaltairrom (UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 162 | static t_stat cpu_set_nommu (UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 163 | static t_stat cpu_set_banked (UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 164 | static t_stat cpu_set_nonbanked (UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 165 | static t_stat cpu_set_ramtype (UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 166 | static t_stat cpu_set_chiptype (UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 167 | static t_stat cpu_set_size (UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 168 | static t_stat cpu_set_memory (UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 169 | static t_stat cpu_clear_command (UNIT *uptr, int32 value, char *cptr, void *desc);\r |
| 170 | static void cpu_clear(void);\r |
| 171 | static t_stat cpu_show (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 172 | static t_stat chip_show (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 173 | static t_stat cpu_ex(t_value *vptr, t_addr addr, UNIT *uptr, int32 sw);\r |
| 174 | static t_stat cpu_dep(t_value val, t_addr addr, UNIT *uptr, int32 sw);\r |
| 175 | static t_stat cpu_reset(DEVICE *dptr);\r |
| 176 | static t_stat sim_instr_mmu(void);\r |
| 177 | static uint32 GetBYTE(register uint32 Addr);\r |
| 178 | static void PutWORD(register uint32 Addr, const register uint32 Value);\r |
| 179 | static void PutBYTE(register uint32 Addr, const register uint32 Value);\r |
| 180 | void out(const uint32 Port, const uint32 Value);\r |
| 181 | uint32 in(const uint32 Port);\r |
| 182 | void altairz80_init(void);\r |
| 183 | t_stat sim_instr(void);\r |
| 184 | t_stat install_bootrom(int32 bootrom[], int32 size, int32 addr, int32 makeROM);\r |
| 185 | uint8 GetBYTEWrapper(const uint32 Addr);\r |
| 186 | void PutBYTEWrapper(const uint32 Addr, const uint32 Value);\r |
| 187 | int32 getBankSelect(void);\r |
| 188 | void setBankSelect(const int32 b);\r |
| 189 | uint32 getCommon(void);\r |
| 190 | t_stat sim_load(FILE *fileref, char *cptr, char *fnam, int32 flag);\r |
| 191 | uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,\r |
| 192 | int32 (*routine)(const int32, const int32, const int32), uint8 unmap);\r |
| 193 | \r |
| 194 | void PutBYTEExtended(register uint32 Addr, const register uint32 Value);\r |
| 195 | uint32 GetBYTEExtended(register uint32 Addr);\r |
| 196 | \r |
| 197 | /* CPU data structures\r |
| 198 | cpu_dev CPU device descriptor\r |
| 199 | cpu_unit CPU unit descriptor\r |
| 200 | cpu_reg CPU register list\r |
| 201 | cpu_mod CPU modifiers list\r |
| 202 | */\r |
| 203 | \r |
| 204 | UNIT cpu_unit = {\r |
| 205 | UDATA (NULL, UNIT_FIX | UNIT_BINK | UNIT_CPU_ALTAIRROM |\r |
| 206 | UNIT_CPU_STOPONHALT | UNIT_CPU_MMU, MAXBANKSIZE)\r |
| 207 | };\r |
| 208 | \r |
| 209 | uint32 PCX = 0; /* external view of PC */\r |
| 210 | int32 AF_S; /* AF register */\r |
| 211 | int32 BC_S; /* BC register */\r |
| 212 | int32 DE_S; /* DE register */\r |
| 213 | int32 HL_S; /* HL register */\r |
| 214 | int32 IX_S; /* IX register */\r |
| 215 | int32 IY_S; /* IY register */\r |
| 216 | int32 PC_S = 0; /* program counter */\r |
| 217 | int32 SP_S; /* SP register */\r |
| 218 | int32 AF1_S; /* alternate AF register */\r |
| 219 | int32 BC1_S; /* alternate BC register */\r |
| 220 | int32 DE1_S; /* alternate DE register */\r |
| 221 | int32 HL1_S; /* alternate HL register */\r |
| 222 | int32 IFF_S; /* Interrupt Flip Flop */\r |
| 223 | int32 IR_S; /* Interrupt (upper) / Refresh (lower) register */\r |
| 224 | int32 AX_S; /* AX register (8086) */\r |
| 225 | int32 BX_S; /* BX register (8086) */\r |
| 226 | int32 CX_S; /* CX register (8086) */\r |
| 227 | int32 DX_S; /* DX register (8086) */\r |
| 228 | int32 CS_S; /* CS register (8086) */\r |
| 229 | int32 DS_S; /* DS register (8086) */\r |
| 230 | int32 ES_S; /* ES register (8086) */\r |
| 231 | int32 SS_S; /* SS register (8086) */\r |
| 232 | int32 DI_S; /* DI register (8086) */\r |
| 233 | int32 SI_S; /* SI register (8086) */\r |
| 234 | int32 BP_S; /* BP register (8086) */\r |
| 235 | int32 SP8086_S; /* SP register (8086) */\r |
| 236 | int32 IP_S; /* IP register (8086) */\r |
| 237 | int32 FLAGS_S; /* flags register (8086) */\r |
| 238 | int32 SR = 0; /* switch register */\r |
| 239 | static int32 bankSelect = 0; /* determines selected memory bank */\r |
| 240 | static uint32 common = 0xc000; /* addresses >= 'common' are in common memory */\r |
| 241 | static uint32 previousCapacity = MAXBANKSIZE; /* safe for previous memory capacity */\r |
| 242 | static uint32 clockFrequency = 0; /* in kHz, 0 means as fast as possible */\r |
| 243 | static uint32 sliceLength = 10; /* length of time-slice for CPU speed */\r |
| 244 | /* adjustment in milliseconds */\r |
| 245 | static uint32 executedTStates = 0; /* executed t-states */\r |
| 246 | static uint16 pcq[PCQ_SIZE] = { /* PC queue */\r |
| 247 | 0\r |
| 248 | };\r |
| 249 | static int32 pcq_p = 0; /* PC queue ptr */\r |
| 250 | static REG *pcq_r = NULL; /* PC queue reg ptr */\r |
| 251 | \r |
| 252 | /* data structure for IN/OUT instructions */\r |
| 253 | struct idev {\r |
| 254 | int32 (*routine)(const int32, const int32, const int32);\r |
| 255 | };\r |
| 256 | \r |
| 257 | #ifdef CPUSWITCHER\r |
| 258 | static int32 switcherPort = SWITCHCPU_DEFAULT;\r |
| 259 | static struct idev oldSwitcherDevice = { NULL };\r |
| 260 | #endif\r |
| 261 | \r |
| 262 | REG cpu_reg[] = {\r |
| 263 | { HRDATA (AF, AF_S, 16) },\r |
| 264 | { HRDATA (BC, BC_S, 16) },\r |
| 265 | { HRDATA (DE, DE_S, 16) },\r |
| 266 | { HRDATA (HL, HL_S, 16) },\r |
| 267 | { HRDATA (IX, IX_S, 16) },\r |
| 268 | { HRDATA (IY, IY_S, 16) },\r |
| 269 | { HRDATA (PC, PC_S, 16 + MAXBANKSLOG2) },\r |
| 270 | { HRDATA (SP, SP_S, 16) },\r |
| 271 | { HRDATA (AF1, AF1_S, 16) },\r |
| 272 | { HRDATA (BC1, BC1_S, 16) },\r |
| 273 | { HRDATA (DE1, DE1_S, 16) },\r |
| 274 | { HRDATA (HL1, HL1_S, 16) },\r |
| 275 | { GRDATA (IFF, IFF_S, 2, 2, 0) },\r |
| 276 | { FLDATA (IR, IR_S, 8) },\r |
| 277 | { HRDATA (AX, AX_S, 16) }, /* 8086 */\r |
| 278 | { GRDATA (AL, AX_S, 16, 8, 0) }, /* 8086, low 8 bits of AX */\r |
| 279 | { GRDATA (AH, AX_S, 16, 8, 8) }, /* 8086, high 8 bits of AX */\r |
| 280 | { HRDATA (BX, BX_S, 16) }, /* 8086 */\r |
| 281 | { GRDATA (BL, BX_S, 16, 8, 0) }, /* 8086, low 8 bits of BX */\r |
| 282 | { GRDATA (BH, BX_S, 16, 8, 8) }, /* 8086, high 8 bits of BX */\r |
| 283 | { HRDATA (CX, CX_S, 16) }, /* 8086 */\r |
| 284 | { GRDATA (CL, CX_S, 16, 8, 0) }, /* 8086, low 8 bits of CX */\r |
| 285 | { GRDATA (CH, CX_S, 16, 8, 8) }, /* 8086, high 8 bits of CX */\r |
| 286 | { HRDATA (DX, DX_S, 16) }, /* 8086 */\r |
| 287 | { GRDATA (DL, DX_S, 16, 8, 0) }, /* 8086, low 8 bits of DX */\r |
| 288 | { GRDATA (DH, DX_S, 16, 8, 8) }, /* 8086, high 8 bits of DX */\r |
| 289 | { HRDATA (SP86, SP8086_S, 16) }, /* 8086 */\r |
| 290 | { HRDATA (BP, BP_S, 16) }, /* 8086, Base Pointer */\r |
| 291 | { HRDATA (SI, SI_S, 16) }, /* 8086, Source Index */\r |
| 292 | { HRDATA (DI, DI_S, 16) }, /* 8086, Destination Index */\r |
| 293 | { HRDATA (CS, CS_S, 16) }, /* 8086, Code Segment */\r |
| 294 | { HRDATA (DS, DS_S, 16) }, /* 8086, Data Segment */\r |
| 295 | { HRDATA (ES, ES_S, 16) }, /* 8086, Extra Segment */\r |
| 296 | { HRDATA (SS, SS_S, 16) }, /* 8086, Stack Segment */\r |
| 297 | { HRDATA (FLAGS, FLAGS_S, 16) }, /* 8086, FLAGS */\r |
| 298 | { HRDATA (IP, IP_S, 16), REG_RO }, /* 8086, set via PC */\r |
| 299 | { FLDATA (OPSTOP, cpu_unit.flags, UNIT_CPU_V_OPSTOP), REG_HRO },\r |
| 300 | { HRDATA (SR, SR, 8) },\r |
| 301 | { HRDATA (BANK, bankSelect, MAXBANKSLOG2) },\r |
| 302 | { HRDATA (COMMON, common, 32) },\r |
| 303 | #ifdef CPUSWITCHER\r |
| 304 | { HRDATA (SWITCHERPORT, switcherPort, 8), },\r |
| 305 | #endif\r |
| 306 | { DRDATA (CLOCK, clockFrequency, 32) },\r |
| 307 | { DRDATA (SLICE, sliceLength, 16) },\r |
| 308 | { DRDATA (TSTATES, executedTStates, 32), REG_RO },\r |
| 309 | { HRDATA (CAPACITY, cpu_unit.capac, 32), REG_RO },\r |
| 310 | { HRDATA (PREVCAP, previousCapacity, 32), REG_RO },\r |
| 311 | { BRDATA (PCQ, pcq, 16, 16, PCQ_SIZE), REG_RO + REG_CIRC },\r |
| 312 | { DRDATA (PCQP, pcq_p, PCQ_SIZE_LOG2), REG_HRO },\r |
| 313 | { HRDATA (WRU, sim_int_char, 8) },\r |
| 314 | { NULL }\r |
| 315 | };\r |
| 316 | \r |
| 317 | static MTAB cpu_mod[] = {\r |
| 318 | { MTAB_XTD | MTAB_VDV, CHIP_TYPE_8080, NULL, "8080", &cpu_set_chiptype },\r |
| 319 | { MTAB_XTD | MTAB_VDV, CHIP_TYPE_Z80, NULL, "Z80", &cpu_set_chiptype },\r |
| 320 | { MTAB_XTD | MTAB_VDV, CHIP_TYPE_8086, NULL, "8086", &cpu_set_chiptype },\r |
| 321 | { UNIT_CPU_OPSTOP, UNIT_CPU_OPSTOP, "ITRAP", "ITRAP", NULL, &chip_show },\r |
| 322 | { UNIT_CPU_OPSTOP, 0, "NOITRAP", "NOITRAP", NULL, &chip_show },\r |
| 323 | { UNIT_CPU_STOPONHALT, UNIT_CPU_STOPONHALT,"STOPONHALT", "STOPONHALT", NULL },\r |
| 324 | { UNIT_CPU_STOPONHALT, 0, "LOOPONHALT", "LOOPONHALT", NULL },\r |
| 325 | { UNIT_CPU_BANKED, UNIT_CPU_BANKED, "BANKED", "BANKED", &cpu_set_banked },\r |
| 326 | { UNIT_CPU_BANKED, 0, "NONBANKED", "NONBANKED", &cpu_set_nonbanked },\r |
| 327 | { UNIT_CPU_ALTAIRROM, UNIT_CPU_ALTAIRROM, "ALTAIRROM", "ALTAIRROM", &cpu_set_altairrom },\r |
| 328 | { UNIT_CPU_ALTAIRROM, 0, "NOALTAIRROM", "NOALTAIRROM", &cpu_set_noaltairrom},\r |
| 329 | { UNIT_CPU_VERBOSE, UNIT_CPU_VERBOSE, "VERBOSE", "VERBOSE", NULL, &cpu_show },\r |
| 330 | { UNIT_CPU_VERBOSE, 0, "QUIET", "QUIET", NULL },\r |
| 331 | { MTAB_VDV, 0, NULL, "CLEARMEMORY", &cpu_clear_command },\r |
| 332 | { UNIT_CPU_MMU, UNIT_CPU_MMU, "MMU", "MMU", NULL },\r |
| 333 | { UNIT_CPU_MMU, 0, "NOMMU", "NOMMU", &cpu_set_nommu },\r |
| 334 | { MTAB_XTD | MTAB_VDV, 0, NULL, "MEMORY", &cpu_set_memory },\r |
| 335 | #ifdef CPUSWITCHER\r |
| 336 | { UNIT_CPU_SWITCHER, UNIT_CPU_SWITCHER, "SWITCHER", "SWITCHER", &cpu_set_switcher, &cpu_show_switcher },\r |
| 337 | { UNIT_CPU_SWITCHER, 0, "NOSWITCHER", "NOSWITCHER", &cpu_reset_switcher, &cpu_show_switcher },\r |
| 338 | #endif\r |
| 339 | { MTAB_XTD | MTAB_VDV, 0, NULL, "AZ80", &cpu_set_ramtype },\r |
| 340 | { MTAB_XTD | MTAB_VDV, 1, NULL, "HRAM", &cpu_set_ramtype },\r |
| 341 | { MTAB_XTD | MTAB_VDV, 2, NULL, "VRAM", &cpu_set_ramtype },\r |
| 342 | { MTAB_XTD | MTAB_VDV, 3, NULL, "CRAM", &cpu_set_ramtype },\r |
| 343 | { MTAB_VDV, 4, NULL, "4KB", &cpu_set_size },\r |
| 344 | { MTAB_VDV, 8, NULL, "8KB", &cpu_set_size },\r |
| 345 | { MTAB_VDV, 12, NULL, "12KB", &cpu_set_size },\r |
| 346 | { MTAB_VDV, 16, NULL, "16KB", &cpu_set_size },\r |
| 347 | { MTAB_VDV, 20, NULL, "20KB", &cpu_set_size },\r |
| 348 | { MTAB_VDV, 24, NULL, "24KB", &cpu_set_size },\r |
| 349 | { MTAB_VDV, 28, NULL, "28KB", &cpu_set_size },\r |
| 350 | { MTAB_VDV, 32, NULL, "32KB", &cpu_set_size },\r |
| 351 | { MTAB_VDV, 36, NULL, "36KB", &cpu_set_size },\r |
| 352 | { MTAB_VDV, 40, NULL, "40KB", &cpu_set_size },\r |
| 353 | { MTAB_VDV, 44, NULL, "44KB", &cpu_set_size },\r |
| 354 | { MTAB_VDV, 48, NULL, "48KB", &cpu_set_size },\r |
| 355 | { MTAB_VDV, 52, NULL, "52KB", &cpu_set_size },\r |
| 356 | { MTAB_VDV, 56, NULL, "56KB", &cpu_set_size },\r |
| 357 | { MTAB_VDV, 60, NULL, "60KB", &cpu_set_size },\r |
| 358 | { MTAB_VDV, 64, NULL, "64KB", &cpu_set_size },\r |
| 359 | { 0 }\r |
| 360 | };\r |
| 361 | \r |
| 362 | DEVICE cpu_dev = {\r |
| 363 | "CPU", &cpu_unit, cpu_reg, cpu_mod,\r |
| 364 | 1, 16, 16, 1, 16, 8,\r |
| 365 | &cpu_ex, &cpu_dep, &cpu_reset,\r |
| 366 | NULL, NULL, NULL,\r |
| 367 | NULL, 0, 0,\r |
| 368 | NULL, NULL, NULL\r |
| 369 | };\r |
| 370 | \r |
| 371 | /* This is the I/O configuration table. There are 255 possible\r |
| 372 | device addresses, if a device is plugged to a port it's routine\r |
| 373 | address is here, 'nulldev' means no device is available\r |
| 374 | */\r |
| 375 | static struct idev dev_table[256] = {\r |
| 376 | {&nulldev}, {&nulldev}, {&sio0d}, {&sio0s}, /* 00 */\r |
| 377 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 04 */\r |
| 378 | {&dsk10}, {&dsk11}, {&dsk12}, {&nulldev}, /* 08 */\r |
| 379 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 0C */\r |
| 380 | {&sio0s}, {&sio0d}, {&sio1s}, {&sio1d}, /* 10 */\r |
| 381 | {&sio0s}, {&sio0d}, {&sio0s}, {&sio0d}, /* 14 */\r |
| 382 | {&sio0s}, {&sio0d}, {&nulldev}, {&nulldev}, /* 18 */\r |
| 383 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 1C */\r |
| 384 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 20 */\r |
| 385 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 24 */\r |
| 386 | {&netStatus},{&netData},{&netStatus},{&netData}, /* 28 */\r |
| 387 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 2C */\r |
| 388 | {&nulldev}, {&nulldev}, {&netStatus},{&netData}, /* 30 */\r |
| 389 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 34 */\r |
| 390 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 38 */\r |
| 391 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 3C */\r |
| 392 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 40 */\r |
| 393 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 44 */\r |
| 394 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 48 */\r |
| 395 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 4C */\r |
| 396 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 50 */\r |
| 397 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 54 */\r |
| 398 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 58 */\r |
| 399 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 5C */\r |
| 400 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 60 */\r |
| 401 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 64 */\r |
| 402 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 68 */\r |
| 403 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 6C */\r |
| 404 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 70 */\r |
| 405 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 74 */\r |
| 406 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 78 */\r |
| 407 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 7C */\r |
| 408 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 80 */\r |
| 409 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 84 */\r |
| 410 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 88 */\r |
| 411 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 8C */\r |
| 412 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 90 */\r |
| 413 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 94 */\r |
| 414 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 98 */\r |
| 415 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* 9C */\r |
| 416 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* A0 */\r |
| 417 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* A4 */\r |
| 418 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* A8 */\r |
| 419 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* AC */\r |
| 420 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* B0 */\r |
| 421 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* B4 */\r |
| 422 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* B8 */\r |
| 423 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* BC */\r |
| 424 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* C0 */\r |
| 425 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* C4 */\r |
| 426 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* C8 */\r |
| 427 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* CC */\r |
| 428 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* D0 */\r |
| 429 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* D4 */\r |
| 430 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* D8 */\r |
| 431 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* DC */\r |
| 432 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* D0 */\r |
| 433 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* E4 */\r |
| 434 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* E8 */\r |
| 435 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* EC */\r |
| 436 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* F0 */\r |
| 437 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* F4 */\r |
| 438 | {&nulldev}, {&nulldev}, {&nulldev}, {&nulldev}, /* F8 */\r |
| 439 | {&nulldev}, {&hdsk_io}, {&simh_dev}, {&sr_dev} /* FC */\r |
| 440 | };\r |
| 441 | \r |
| 442 | static int32 ramtype = 0;\r |
| 443 | int32 chiptype = CHIP_TYPE_8080;\r |
| 444 | \r |
| 445 | void out(const uint32 Port, const uint32 Value) {\r |
| 446 | dev_table[Port & 0xff].routine(Port, 1, Value);\r |
| 447 | }\r |
| 448 | \r |
| 449 | uint32 in(const uint32 Port) {\r |
| 450 | return dev_table[Port & 0xff].routine(Port, 0, 0);\r |
| 451 | }\r |
| 452 | \r |
| 453 | /* the following tables precompute some common subexpressions\r |
| 454 | parityTable[i] 0..255 (number of 1's in i is odd) ? 0 : 4\r |
| 455 | incTable[i] 0..256! (i & 0xa8) | (((i & 0xff) == 0) << 6) | (((i & 0xf) == 0) << 4)\r |
| 456 | decTable[i] 0..255 (i & 0xa8) | (((i & 0xff) == 0) << 6) | (((i & 0xf) == 0xf) << 4) | 2\r |
| 457 | cbitsTable[i] 0..511 (i & 0x10) | ((i >> 8) & 1)\r |
| 458 | cbitsDup8Table[i] 0..511 (i & 0x10) | ((i >> 8) & 1) | ((i & 0xff) << 8) | (i & 0xa8) |\r |
| 459 | (((i & 0xff) == 0) << 6)\r |
| 460 | cbitsDup16Table[i] 0..511 (i & 0x10) | ((i >> 8) & 1) | (i & 0x28)\r |
| 461 | cbits2Table[i] 0..511 (i & 0x10) | ((i >> 8) & 1) | 2\r |
| 462 | rrcaTable[i] 0..255 ((i & 1) << 15) | ((i >> 1) << 8) | ((i >> 1) & 0x28) | (i & 1)\r |
| 463 | rraTable[i] 0..255 ((i >> 1) << 8) | ((i >> 1) & 0x28) | (i & 1)\r |
| 464 | addTable[i] 0..511 ((i & 0xff) << 8) | (i & 0xa8) | (((i & 0xff) == 0) << 6)\r |
| 465 | subTable[i] 0..255 ((i & 0xff) << 8) | (i & 0xa8) | (((i & 0xff) == 0) << 6) | 2\r |
| 466 | andTable[i] 0..255 (i << 8) | (i & 0xa8) | ((i == 0) << 6) | 0x10 | parityTable[i]\r |
| 467 | xororTable[i] 0..255 (i << 8) | (i & 0xa8) | ((i == 0) << 6) | parityTable[i]\r |
| 468 | rotateShiftTable[i] 0..255 (i & 0xa8) | (((i & 0xff) == 0) << 6) | parityTable[i & 0xff]\r |
| 469 | incZ80Table[i] 0..256! (i & 0xa8) | (((i & 0xff) == 0) << 6) |\r |
| 470 | (((i & 0xf) == 0) << 4) | ((i == 0x80) << 2)\r |
| 471 | decZ80Table[i] 0..255 (i & 0xa8) | (((i & 0xff) == 0) << 6) |\r |
| 472 | (((i & 0xf) == 0xf) << 4) | ((i == 0x7f) << 2) | 2\r |
| 473 | cbitsZ80Table[i] 0..511 (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) | ((i >> 8) & 1)\r |
| 474 | cbitsZ80DupTable[i] 0..511 (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) |\r |
| 475 | ((i >> 8) & 1) | (i & 0xa8)\r |
| 476 | cbits2Z80Table[i] 0..511 (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) | ((i >> 8) & 1) | 2\r |
| 477 | cbits2Z80DupTable[i] 0..511 (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) | ((i >> 8) & 1) | 2 |\r |
| 478 | (i & 0xa8)\r |
| 479 | negTable[i] 0..255 (((i & 0x0f) != 0) << 4) | ((i == 0x80) << 2) | 2 | (i != 0)\r |
| 480 | rrdrldTable[i] 0..255 (i << 8) | (i & 0xa8) | (((i & 0xff) == 0) << 6) | parityTable[i]\r |
| 481 | cpTable[i] 0..255 (i & 0x80) | (((i & 0xff) == 0) << 6)\r |
| 482 | */\r |
| 483 | \r |
| 484 | /* parityTable[i] = (number of 1's in i is odd) ? 0 : 4, i = 0..255 */\r |
| 485 | static const uint8 parityTable[256] = {\r |
| 486 | 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,\r |
| 487 | 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,\r |
| 488 | 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,\r |
| 489 | 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,\r |
| 490 | 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,\r |
| 491 | 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,\r |
| 492 | 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,\r |
| 493 | 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,\r |
| 494 | 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,\r |
| 495 | 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,\r |
| 496 | 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,\r |
| 497 | 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,\r |
| 498 | 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,\r |
| 499 | 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,\r |
| 500 | 0,4,4,0,4,0,0,4,4,0,0,4,0,4,4,0,\r |
| 501 | 4,0,0,4,0,4,4,0,0,4,4,0,4,0,0,4,\r |
| 502 | };\r |
| 503 | \r |
| 504 | /* incTable[i] = (i & 0xa8) | (((i & 0xff) == 0) << 6) | (((i & 0xf) == 0) << 4), i = 0..256 */\r |
| 505 | static const uint8 incTable[257] = {\r |
| 506 | 80, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 507 | 16, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 508 | 48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,\r |
| 509 | 48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,\r |
| 510 | 16, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 511 | 16, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 512 | 48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,\r |
| 513 | 48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,\r |
| 514 | 144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,\r |
| 515 | 144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,\r |
| 516 | 176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,\r |
| 517 | 176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,\r |
| 518 | 144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,\r |
| 519 | 144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,\r |
| 520 | 176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,\r |
| 521 | 176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168, 80\r |
| 522 | };\r |
| 523 | \r |
| 524 | /* decTable[i] = (i & 0xa8) | (((i & 0xff) == 0) << 6) | (((i & 0xf) == 0xf) << 4) | 2, i = 0..255 */\r |
| 525 | static const uint8 decTable[256] = {\r |
| 526 | 66, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,\r |
| 527 | 2, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,\r |
| 528 | 34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 58,\r |
| 529 | 34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 58,\r |
| 530 | 2, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,\r |
| 531 | 2, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,\r |
| 532 | 34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 58,\r |
| 533 | 34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 58,\r |
| 534 | 130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,\r |
| 535 | 130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,\r |
| 536 | 162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,\r |
| 537 | 162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,\r |
| 538 | 130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,\r |
| 539 | 130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,\r |
| 540 | 162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,\r |
| 541 | 162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,\r |
| 542 | };\r |
| 543 | \r |
| 544 | /* cbitsTable[i] = (i & 0x10) | ((i >> 8) & 1), i = 0..511 */\r |
| 545 | static const uint8 cbitsTable[512] = {\r |
| 546 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 547 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 548 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 549 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 550 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 551 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 552 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 553 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 554 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 555 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 556 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 557 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 558 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 559 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 560 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 561 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 562 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 563 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 564 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 565 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 566 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 567 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 568 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 569 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 570 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 571 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 572 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 573 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 574 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 575 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 576 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 577 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 578 | };\r |
| 579 | \r |
| 580 | /* cbitsDup8Table[i] = (i & 0x10) | ((i >> 8) & 1) | ((i & 0xff) << 8) | (i & 0xa8) |\r |
| 581 | (((i & 0xff) == 0) << 6), i = 0..511 */\r |
| 582 | static const uint16 cbitsDup8Table[512] = {\r |
| 583 | 0x0040,0x0100,0x0200,0x0300,0x0400,0x0500,0x0600,0x0700,\r |
| 584 | 0x0808,0x0908,0x0a08,0x0b08,0x0c08,0x0d08,0x0e08,0x0f08,\r |
| 585 | 0x1010,0x1110,0x1210,0x1310,0x1410,0x1510,0x1610,0x1710,\r |
| 586 | 0x1818,0x1918,0x1a18,0x1b18,0x1c18,0x1d18,0x1e18,0x1f18,\r |
| 587 | 0x2020,0x2120,0x2220,0x2320,0x2420,0x2520,0x2620,0x2720,\r |
| 588 | 0x2828,0x2928,0x2a28,0x2b28,0x2c28,0x2d28,0x2e28,0x2f28,\r |
| 589 | 0x3030,0x3130,0x3230,0x3330,0x3430,0x3530,0x3630,0x3730,\r |
| 590 | 0x3838,0x3938,0x3a38,0x3b38,0x3c38,0x3d38,0x3e38,0x3f38,\r |
| 591 | 0x4000,0x4100,0x4200,0x4300,0x4400,0x4500,0x4600,0x4700,\r |
| 592 | 0x4808,0x4908,0x4a08,0x4b08,0x4c08,0x4d08,0x4e08,0x4f08,\r |
| 593 | 0x5010,0x5110,0x5210,0x5310,0x5410,0x5510,0x5610,0x5710,\r |
| 594 | 0x5818,0x5918,0x5a18,0x5b18,0x5c18,0x5d18,0x5e18,0x5f18,\r |
| 595 | 0x6020,0x6120,0x6220,0x6320,0x6420,0x6520,0x6620,0x6720,\r |
| 596 | 0x6828,0x6928,0x6a28,0x6b28,0x6c28,0x6d28,0x6e28,0x6f28,\r |
| 597 | 0x7030,0x7130,0x7230,0x7330,0x7430,0x7530,0x7630,0x7730,\r |
| 598 | 0x7838,0x7938,0x7a38,0x7b38,0x7c38,0x7d38,0x7e38,0x7f38,\r |
| 599 | 0x8080,0x8180,0x8280,0x8380,0x8480,0x8580,0x8680,0x8780,\r |
| 600 | 0x8888,0x8988,0x8a88,0x8b88,0x8c88,0x8d88,0x8e88,0x8f88,\r |
| 601 | 0x9090,0x9190,0x9290,0x9390,0x9490,0x9590,0x9690,0x9790,\r |
| 602 | 0x9898,0x9998,0x9a98,0x9b98,0x9c98,0x9d98,0x9e98,0x9f98,\r |
| 603 | 0xa0a0,0xa1a0,0xa2a0,0xa3a0,0xa4a0,0xa5a0,0xa6a0,0xa7a0,\r |
| 604 | 0xa8a8,0xa9a8,0xaaa8,0xaba8,0xaca8,0xada8,0xaea8,0xafa8,\r |
| 605 | 0xb0b0,0xb1b0,0xb2b0,0xb3b0,0xb4b0,0xb5b0,0xb6b0,0xb7b0,\r |
| 606 | 0xb8b8,0xb9b8,0xbab8,0xbbb8,0xbcb8,0xbdb8,0xbeb8,0xbfb8,\r |
| 607 | 0xc080,0xc180,0xc280,0xc380,0xc480,0xc580,0xc680,0xc780,\r |
| 608 | 0xc888,0xc988,0xca88,0xcb88,0xcc88,0xcd88,0xce88,0xcf88,\r |
| 609 | 0xd090,0xd190,0xd290,0xd390,0xd490,0xd590,0xd690,0xd790,\r |
| 610 | 0xd898,0xd998,0xda98,0xdb98,0xdc98,0xdd98,0xde98,0xdf98,\r |
| 611 | 0xe0a0,0xe1a0,0xe2a0,0xe3a0,0xe4a0,0xe5a0,0xe6a0,0xe7a0,\r |
| 612 | 0xe8a8,0xe9a8,0xeaa8,0xeba8,0xeca8,0xeda8,0xeea8,0xefa8,\r |
| 613 | 0xf0b0,0xf1b0,0xf2b0,0xf3b0,0xf4b0,0xf5b0,0xf6b0,0xf7b0,\r |
| 614 | 0xf8b8,0xf9b8,0xfab8,0xfbb8,0xfcb8,0xfdb8,0xfeb8,0xffb8,\r |
| 615 | 0x0041,0x0101,0x0201,0x0301,0x0401,0x0501,0x0601,0x0701,\r |
| 616 | 0x0809,0x0909,0x0a09,0x0b09,0x0c09,0x0d09,0x0e09,0x0f09,\r |
| 617 | 0x1011,0x1111,0x1211,0x1311,0x1411,0x1511,0x1611,0x1711,\r |
| 618 | 0x1819,0x1919,0x1a19,0x1b19,0x1c19,0x1d19,0x1e19,0x1f19,\r |
| 619 | 0x2021,0x2121,0x2221,0x2321,0x2421,0x2521,0x2621,0x2721,\r |
| 620 | 0x2829,0x2929,0x2a29,0x2b29,0x2c29,0x2d29,0x2e29,0x2f29,\r |
| 621 | 0x3031,0x3131,0x3231,0x3331,0x3431,0x3531,0x3631,0x3731,\r |
| 622 | 0x3839,0x3939,0x3a39,0x3b39,0x3c39,0x3d39,0x3e39,0x3f39,\r |
| 623 | 0x4001,0x4101,0x4201,0x4301,0x4401,0x4501,0x4601,0x4701,\r |
| 624 | 0x4809,0x4909,0x4a09,0x4b09,0x4c09,0x4d09,0x4e09,0x4f09,\r |
| 625 | 0x5011,0x5111,0x5211,0x5311,0x5411,0x5511,0x5611,0x5711,\r |
| 626 | 0x5819,0x5919,0x5a19,0x5b19,0x5c19,0x5d19,0x5e19,0x5f19,\r |
| 627 | 0x6021,0x6121,0x6221,0x6321,0x6421,0x6521,0x6621,0x6721,\r |
| 628 | 0x6829,0x6929,0x6a29,0x6b29,0x6c29,0x6d29,0x6e29,0x6f29,\r |
| 629 | 0x7031,0x7131,0x7231,0x7331,0x7431,0x7531,0x7631,0x7731,\r |
| 630 | 0x7839,0x7939,0x7a39,0x7b39,0x7c39,0x7d39,0x7e39,0x7f39,\r |
| 631 | 0x8081,0x8181,0x8281,0x8381,0x8481,0x8581,0x8681,0x8781,\r |
| 632 | 0x8889,0x8989,0x8a89,0x8b89,0x8c89,0x8d89,0x8e89,0x8f89,\r |
| 633 | 0x9091,0x9191,0x9291,0x9391,0x9491,0x9591,0x9691,0x9791,\r |
| 634 | 0x9899,0x9999,0x9a99,0x9b99,0x9c99,0x9d99,0x9e99,0x9f99,\r |
| 635 | 0xa0a1,0xa1a1,0xa2a1,0xa3a1,0xa4a1,0xa5a1,0xa6a1,0xa7a1,\r |
| 636 | 0xa8a9,0xa9a9,0xaaa9,0xaba9,0xaca9,0xada9,0xaea9,0xafa9,\r |
| 637 | 0xb0b1,0xb1b1,0xb2b1,0xb3b1,0xb4b1,0xb5b1,0xb6b1,0xb7b1,\r |
| 638 | 0xb8b9,0xb9b9,0xbab9,0xbbb9,0xbcb9,0xbdb9,0xbeb9,0xbfb9,\r |
| 639 | 0xc081,0xc181,0xc281,0xc381,0xc481,0xc581,0xc681,0xc781,\r |
| 640 | 0xc889,0xc989,0xca89,0xcb89,0xcc89,0xcd89,0xce89,0xcf89,\r |
| 641 | 0xd091,0xd191,0xd291,0xd391,0xd491,0xd591,0xd691,0xd791,\r |
| 642 | 0xd899,0xd999,0xda99,0xdb99,0xdc99,0xdd99,0xde99,0xdf99,\r |
| 643 | 0xe0a1,0xe1a1,0xe2a1,0xe3a1,0xe4a1,0xe5a1,0xe6a1,0xe7a1,\r |
| 644 | 0xe8a9,0xe9a9,0xeaa9,0xeba9,0xeca9,0xeda9,0xeea9,0xefa9,\r |
| 645 | 0xf0b1,0xf1b1,0xf2b1,0xf3b1,0xf4b1,0xf5b1,0xf6b1,0xf7b1,\r |
| 646 | 0xf8b9,0xf9b9,0xfab9,0xfbb9,0xfcb9,0xfdb9,0xfeb9,0xffb9,\r |
| 647 | };\r |
| 648 | \r |
| 649 | /* cbitsDup16Table[i] = (i & 0x10) | ((i >> 8) & 1) | (i & 0x28), i = 0..511 */\r |
| 650 | static const uint8 cbitsDup16Table[512] = {\r |
| 651 | 0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 652 | 16,16,16,16,16,16,16,16,24,24,24,24,24,24,24,24,\r |
| 653 | 32,32,32,32,32,32,32,32,40,40,40,40,40,40,40,40,\r |
| 654 | 48,48,48,48,48,48,48,48,56,56,56,56,56,56,56,56,\r |
| 655 | 0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 656 | 16,16,16,16,16,16,16,16,24,24,24,24,24,24,24,24,\r |
| 657 | 32,32,32,32,32,32,32,32,40,40,40,40,40,40,40,40,\r |
| 658 | 48,48,48,48,48,48,48,48,56,56,56,56,56,56,56,56,\r |
| 659 | 0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 660 | 16,16,16,16,16,16,16,16,24,24,24,24,24,24,24,24,\r |
| 661 | 32,32,32,32,32,32,32,32,40,40,40,40,40,40,40,40,\r |
| 662 | 48,48,48,48,48,48,48,48,56,56,56,56,56,56,56,56,\r |
| 663 | 0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 664 | 16,16,16,16,16,16,16,16,24,24,24,24,24,24,24,24,\r |
| 665 | 32,32,32,32,32,32,32,32,40,40,40,40,40,40,40,40,\r |
| 666 | 48,48,48,48,48,48,48,48,56,56,56,56,56,56,56,56,\r |
| 667 | 1, 1, 1, 1, 1, 1, 1, 1, 9, 9, 9, 9, 9, 9, 9, 9,\r |
| 668 | 17,17,17,17,17,17,17,17,25,25,25,25,25,25,25,25,\r |
| 669 | 33,33,33,33,33,33,33,33,41,41,41,41,41,41,41,41,\r |
| 670 | 49,49,49,49,49,49,49,49,57,57,57,57,57,57,57,57,\r |
| 671 | 1, 1, 1, 1, 1, 1, 1, 1, 9, 9, 9, 9, 9, 9, 9, 9,\r |
| 672 | 17,17,17,17,17,17,17,17,25,25,25,25,25,25,25,25,\r |
| 673 | 33,33,33,33,33,33,33,33,41,41,41,41,41,41,41,41,\r |
| 674 | 49,49,49,49,49,49,49,49,57,57,57,57,57,57,57,57,\r |
| 675 | 1, 1, 1, 1, 1, 1, 1, 1, 9, 9, 9, 9, 9, 9, 9, 9,\r |
| 676 | 17,17,17,17,17,17,17,17,25,25,25,25,25,25,25,25,\r |
| 677 | 33,33,33,33,33,33,33,33,41,41,41,41,41,41,41,41,\r |
| 678 | 49,49,49,49,49,49,49,49,57,57,57,57,57,57,57,57,\r |
| 679 | 1, 1, 1, 1, 1, 1, 1, 1, 9, 9, 9, 9, 9, 9, 9, 9,\r |
| 680 | 17,17,17,17,17,17,17,17,25,25,25,25,25,25,25,25,\r |
| 681 | 33,33,33,33,33,33,33,33,41,41,41,41,41,41,41,41,\r |
| 682 | 49,49,49,49,49,49,49,49,57,57,57,57,57,57,57,57,\r |
| 683 | };\r |
| 684 | \r |
| 685 | /* cbits2Table[i] = (i & 0x10) | ((i >> 8) & 1) | 2, i = 0..511 */\r |
| 686 | static const uint8 cbits2Table[512] = {\r |
| 687 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 688 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 689 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 690 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 691 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 692 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 693 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 694 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 695 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 696 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 697 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 698 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 699 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 700 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 701 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 702 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 703 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 704 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 705 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 706 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 707 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 708 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 709 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 710 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 711 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 712 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 713 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 714 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 715 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 716 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 717 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 718 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 719 | };\r |
| 720 | \r |
| 721 | /* rrcaTable[i] = ((i & 1) << 15) | ((i >> 1) << 8) | ((i >> 1) & 0x28) | (i & 1), i = 0..255 */\r |
| 722 | static const uint16 rrcaTable[256] = {\r |
| 723 | 0x0000,0x8001,0x0100,0x8101,0x0200,0x8201,0x0300,0x8301,\r |
| 724 | 0x0400,0x8401,0x0500,0x8501,0x0600,0x8601,0x0700,0x8701,\r |
| 725 | 0x0808,0x8809,0x0908,0x8909,0x0a08,0x8a09,0x0b08,0x8b09,\r |
| 726 | 0x0c08,0x8c09,0x0d08,0x8d09,0x0e08,0x8e09,0x0f08,0x8f09,\r |
| 727 | 0x1000,0x9001,0x1100,0x9101,0x1200,0x9201,0x1300,0x9301,\r |
| 728 | 0x1400,0x9401,0x1500,0x9501,0x1600,0x9601,0x1700,0x9701,\r |
| 729 | 0x1808,0x9809,0x1908,0x9909,0x1a08,0x9a09,0x1b08,0x9b09,\r |
| 730 | 0x1c08,0x9c09,0x1d08,0x9d09,0x1e08,0x9e09,0x1f08,0x9f09,\r |
| 731 | 0x2020,0xa021,0x2120,0xa121,0x2220,0xa221,0x2320,0xa321,\r |
| 732 | 0x2420,0xa421,0x2520,0xa521,0x2620,0xa621,0x2720,0xa721,\r |
| 733 | 0x2828,0xa829,0x2928,0xa929,0x2a28,0xaa29,0x2b28,0xab29,\r |
| 734 | 0x2c28,0xac29,0x2d28,0xad29,0x2e28,0xae29,0x2f28,0xaf29,\r |
| 735 | 0x3020,0xb021,0x3120,0xb121,0x3220,0xb221,0x3320,0xb321,\r |
| 736 | 0x3420,0xb421,0x3520,0xb521,0x3620,0xb621,0x3720,0xb721,\r |
| 737 | 0x3828,0xb829,0x3928,0xb929,0x3a28,0xba29,0x3b28,0xbb29,\r |
| 738 | 0x3c28,0xbc29,0x3d28,0xbd29,0x3e28,0xbe29,0x3f28,0xbf29,\r |
| 739 | 0x4000,0xc001,0x4100,0xc101,0x4200,0xc201,0x4300,0xc301,\r |
| 740 | 0x4400,0xc401,0x4500,0xc501,0x4600,0xc601,0x4700,0xc701,\r |
| 741 | 0x4808,0xc809,0x4908,0xc909,0x4a08,0xca09,0x4b08,0xcb09,\r |
| 742 | 0x4c08,0xcc09,0x4d08,0xcd09,0x4e08,0xce09,0x4f08,0xcf09,\r |
| 743 | 0x5000,0xd001,0x5100,0xd101,0x5200,0xd201,0x5300,0xd301,\r |
| 744 | 0x5400,0xd401,0x5500,0xd501,0x5600,0xd601,0x5700,0xd701,\r |
| 745 | 0x5808,0xd809,0x5908,0xd909,0x5a08,0xda09,0x5b08,0xdb09,\r |
| 746 | 0x5c08,0xdc09,0x5d08,0xdd09,0x5e08,0xde09,0x5f08,0xdf09,\r |
| 747 | 0x6020,0xe021,0x6120,0xe121,0x6220,0xe221,0x6320,0xe321,\r |
| 748 | 0x6420,0xe421,0x6520,0xe521,0x6620,0xe621,0x6720,0xe721,\r |
| 749 | 0x6828,0xe829,0x6928,0xe929,0x6a28,0xea29,0x6b28,0xeb29,\r |
| 750 | 0x6c28,0xec29,0x6d28,0xed29,0x6e28,0xee29,0x6f28,0xef29,\r |
| 751 | 0x7020,0xf021,0x7120,0xf121,0x7220,0xf221,0x7320,0xf321,\r |
| 752 | 0x7420,0xf421,0x7520,0xf521,0x7620,0xf621,0x7720,0xf721,\r |
| 753 | 0x7828,0xf829,0x7928,0xf929,0x7a28,0xfa29,0x7b28,0xfb29,\r |
| 754 | 0x7c28,0xfc29,0x7d28,0xfd29,0x7e28,0xfe29,0x7f28,0xff29,\r |
| 755 | };\r |
| 756 | \r |
| 757 | /* rraTable[i] = ((i >> 1) << 8) | ((i >> 1) & 0x28) | (i & 1), i = 0..255 */\r |
| 758 | static const uint16 rraTable[256] = {\r |
| 759 | 0x0000,0x0001,0x0100,0x0101,0x0200,0x0201,0x0300,0x0301,\r |
| 760 | 0x0400,0x0401,0x0500,0x0501,0x0600,0x0601,0x0700,0x0701,\r |
| 761 | 0x0808,0x0809,0x0908,0x0909,0x0a08,0x0a09,0x0b08,0x0b09,\r |
| 762 | 0x0c08,0x0c09,0x0d08,0x0d09,0x0e08,0x0e09,0x0f08,0x0f09,\r |
| 763 | 0x1000,0x1001,0x1100,0x1101,0x1200,0x1201,0x1300,0x1301,\r |
| 764 | 0x1400,0x1401,0x1500,0x1501,0x1600,0x1601,0x1700,0x1701,\r |
| 765 | 0x1808,0x1809,0x1908,0x1909,0x1a08,0x1a09,0x1b08,0x1b09,\r |
| 766 | 0x1c08,0x1c09,0x1d08,0x1d09,0x1e08,0x1e09,0x1f08,0x1f09,\r |
| 767 | 0x2020,0x2021,0x2120,0x2121,0x2220,0x2221,0x2320,0x2321,\r |
| 768 | 0x2420,0x2421,0x2520,0x2521,0x2620,0x2621,0x2720,0x2721,\r |
| 769 | 0x2828,0x2829,0x2928,0x2929,0x2a28,0x2a29,0x2b28,0x2b29,\r |
| 770 | 0x2c28,0x2c29,0x2d28,0x2d29,0x2e28,0x2e29,0x2f28,0x2f29,\r |
| 771 | 0x3020,0x3021,0x3120,0x3121,0x3220,0x3221,0x3320,0x3321,\r |
| 772 | 0x3420,0x3421,0x3520,0x3521,0x3620,0x3621,0x3720,0x3721,\r |
| 773 | 0x3828,0x3829,0x3928,0x3929,0x3a28,0x3a29,0x3b28,0x3b29,\r |
| 774 | 0x3c28,0x3c29,0x3d28,0x3d29,0x3e28,0x3e29,0x3f28,0x3f29,\r |
| 775 | 0x4000,0x4001,0x4100,0x4101,0x4200,0x4201,0x4300,0x4301,\r |
| 776 | 0x4400,0x4401,0x4500,0x4501,0x4600,0x4601,0x4700,0x4701,\r |
| 777 | 0x4808,0x4809,0x4908,0x4909,0x4a08,0x4a09,0x4b08,0x4b09,\r |
| 778 | 0x4c08,0x4c09,0x4d08,0x4d09,0x4e08,0x4e09,0x4f08,0x4f09,\r |
| 779 | 0x5000,0x5001,0x5100,0x5101,0x5200,0x5201,0x5300,0x5301,\r |
| 780 | 0x5400,0x5401,0x5500,0x5501,0x5600,0x5601,0x5700,0x5701,\r |
| 781 | 0x5808,0x5809,0x5908,0x5909,0x5a08,0x5a09,0x5b08,0x5b09,\r |
| 782 | 0x5c08,0x5c09,0x5d08,0x5d09,0x5e08,0x5e09,0x5f08,0x5f09,\r |
| 783 | 0x6020,0x6021,0x6120,0x6121,0x6220,0x6221,0x6320,0x6321,\r |
| 784 | 0x6420,0x6421,0x6520,0x6521,0x6620,0x6621,0x6720,0x6721,\r |
| 785 | 0x6828,0x6829,0x6928,0x6929,0x6a28,0x6a29,0x6b28,0x6b29,\r |
| 786 | 0x6c28,0x6c29,0x6d28,0x6d29,0x6e28,0x6e29,0x6f28,0x6f29,\r |
| 787 | 0x7020,0x7021,0x7120,0x7121,0x7220,0x7221,0x7320,0x7321,\r |
| 788 | 0x7420,0x7421,0x7520,0x7521,0x7620,0x7621,0x7720,0x7721,\r |
| 789 | 0x7828,0x7829,0x7928,0x7929,0x7a28,0x7a29,0x7b28,0x7b29,\r |
| 790 | 0x7c28,0x7c29,0x7d28,0x7d29,0x7e28,0x7e29,0x7f28,0x7f29,\r |
| 791 | };\r |
| 792 | \r |
| 793 | /* addTable[i] = ((i & 0xff) << 8) | (i & 0xa8) | (((i & 0xff) == 0) << 6), i = 0..511 */\r |
| 794 | static const uint16 addTable[512] = {\r |
| 795 | 0x0040,0x0100,0x0200,0x0300,0x0400,0x0500,0x0600,0x0700,\r |
| 796 | 0x0808,0x0908,0x0a08,0x0b08,0x0c08,0x0d08,0x0e08,0x0f08,\r |
| 797 | 0x1000,0x1100,0x1200,0x1300,0x1400,0x1500,0x1600,0x1700,\r |
| 798 | 0x1808,0x1908,0x1a08,0x1b08,0x1c08,0x1d08,0x1e08,0x1f08,\r |
| 799 | 0x2020,0x2120,0x2220,0x2320,0x2420,0x2520,0x2620,0x2720,\r |
| 800 | 0x2828,0x2928,0x2a28,0x2b28,0x2c28,0x2d28,0x2e28,0x2f28,\r |
| 801 | 0x3020,0x3120,0x3220,0x3320,0x3420,0x3520,0x3620,0x3720,\r |
| 802 | 0x3828,0x3928,0x3a28,0x3b28,0x3c28,0x3d28,0x3e28,0x3f28,\r |
| 803 | 0x4000,0x4100,0x4200,0x4300,0x4400,0x4500,0x4600,0x4700,\r |
| 804 | 0x4808,0x4908,0x4a08,0x4b08,0x4c08,0x4d08,0x4e08,0x4f08,\r |
| 805 | 0x5000,0x5100,0x5200,0x5300,0x5400,0x5500,0x5600,0x5700,\r |
| 806 | 0x5808,0x5908,0x5a08,0x5b08,0x5c08,0x5d08,0x5e08,0x5f08,\r |
| 807 | 0x6020,0x6120,0x6220,0x6320,0x6420,0x6520,0x6620,0x6720,\r |
| 808 | 0x6828,0x6928,0x6a28,0x6b28,0x6c28,0x6d28,0x6e28,0x6f28,\r |
| 809 | 0x7020,0x7120,0x7220,0x7320,0x7420,0x7520,0x7620,0x7720,\r |
| 810 | 0x7828,0x7928,0x7a28,0x7b28,0x7c28,0x7d28,0x7e28,0x7f28,\r |
| 811 | 0x8080,0x8180,0x8280,0x8380,0x8480,0x8580,0x8680,0x8780,\r |
| 812 | 0x8888,0x8988,0x8a88,0x8b88,0x8c88,0x8d88,0x8e88,0x8f88,\r |
| 813 | 0x9080,0x9180,0x9280,0x9380,0x9480,0x9580,0x9680,0x9780,\r |
| 814 | 0x9888,0x9988,0x9a88,0x9b88,0x9c88,0x9d88,0x9e88,0x9f88,\r |
| 815 | 0xa0a0,0xa1a0,0xa2a0,0xa3a0,0xa4a0,0xa5a0,0xa6a0,0xa7a0,\r |
| 816 | 0xa8a8,0xa9a8,0xaaa8,0xaba8,0xaca8,0xada8,0xaea8,0xafa8,\r |
| 817 | 0xb0a0,0xb1a0,0xb2a0,0xb3a0,0xb4a0,0xb5a0,0xb6a0,0xb7a0,\r |
| 818 | 0xb8a8,0xb9a8,0xbaa8,0xbba8,0xbca8,0xbda8,0xbea8,0xbfa8,\r |
| 819 | 0xc080,0xc180,0xc280,0xc380,0xc480,0xc580,0xc680,0xc780,\r |
| 820 | 0xc888,0xc988,0xca88,0xcb88,0xcc88,0xcd88,0xce88,0xcf88,\r |
| 821 | 0xd080,0xd180,0xd280,0xd380,0xd480,0xd580,0xd680,0xd780,\r |
| 822 | 0xd888,0xd988,0xda88,0xdb88,0xdc88,0xdd88,0xde88,0xdf88,\r |
| 823 | 0xe0a0,0xe1a0,0xe2a0,0xe3a0,0xe4a0,0xe5a0,0xe6a0,0xe7a0,\r |
| 824 | 0xe8a8,0xe9a8,0xeaa8,0xeba8,0xeca8,0xeda8,0xeea8,0xefa8,\r |
| 825 | 0xf0a0,0xf1a0,0xf2a0,0xf3a0,0xf4a0,0xf5a0,0xf6a0,0xf7a0,\r |
| 826 | 0xf8a8,0xf9a8,0xfaa8,0xfba8,0xfca8,0xfda8,0xfea8,0xffa8,\r |
| 827 | 0x0040,0x0100,0x0200,0x0300,0x0400,0x0500,0x0600,0x0700,\r |
| 828 | 0x0808,0x0908,0x0a08,0x0b08,0x0c08,0x0d08,0x0e08,0x0f08,\r |
| 829 | 0x1000,0x1100,0x1200,0x1300,0x1400,0x1500,0x1600,0x1700,\r |
| 830 | 0x1808,0x1908,0x1a08,0x1b08,0x1c08,0x1d08,0x1e08,0x1f08,\r |
| 831 | 0x2020,0x2120,0x2220,0x2320,0x2420,0x2520,0x2620,0x2720,\r |
| 832 | 0x2828,0x2928,0x2a28,0x2b28,0x2c28,0x2d28,0x2e28,0x2f28,\r |
| 833 | 0x3020,0x3120,0x3220,0x3320,0x3420,0x3520,0x3620,0x3720,\r |
| 834 | 0x3828,0x3928,0x3a28,0x3b28,0x3c28,0x3d28,0x3e28,0x3f28,\r |
| 835 | 0x4000,0x4100,0x4200,0x4300,0x4400,0x4500,0x4600,0x4700,\r |
| 836 | 0x4808,0x4908,0x4a08,0x4b08,0x4c08,0x4d08,0x4e08,0x4f08,\r |
| 837 | 0x5000,0x5100,0x5200,0x5300,0x5400,0x5500,0x5600,0x5700,\r |
| 838 | 0x5808,0x5908,0x5a08,0x5b08,0x5c08,0x5d08,0x5e08,0x5f08,\r |
| 839 | 0x6020,0x6120,0x6220,0x6320,0x6420,0x6520,0x6620,0x6720,\r |
| 840 | 0x6828,0x6928,0x6a28,0x6b28,0x6c28,0x6d28,0x6e28,0x6f28,\r |
| 841 | 0x7020,0x7120,0x7220,0x7320,0x7420,0x7520,0x7620,0x7720,\r |
| 842 | 0x7828,0x7928,0x7a28,0x7b28,0x7c28,0x7d28,0x7e28,0x7f28,\r |
| 843 | 0x8080,0x8180,0x8280,0x8380,0x8480,0x8580,0x8680,0x8780,\r |
| 844 | 0x8888,0x8988,0x8a88,0x8b88,0x8c88,0x8d88,0x8e88,0x8f88,\r |
| 845 | 0x9080,0x9180,0x9280,0x9380,0x9480,0x9580,0x9680,0x9780,\r |
| 846 | 0x9888,0x9988,0x9a88,0x9b88,0x9c88,0x9d88,0x9e88,0x9f88,\r |
| 847 | 0xa0a0,0xa1a0,0xa2a0,0xa3a0,0xa4a0,0xa5a0,0xa6a0,0xa7a0,\r |
| 848 | 0xa8a8,0xa9a8,0xaaa8,0xaba8,0xaca8,0xada8,0xaea8,0xafa8,\r |
| 849 | 0xb0a0,0xb1a0,0xb2a0,0xb3a0,0xb4a0,0xb5a0,0xb6a0,0xb7a0,\r |
| 850 | 0xb8a8,0xb9a8,0xbaa8,0xbba8,0xbca8,0xbda8,0xbea8,0xbfa8,\r |
| 851 | 0xc080,0xc180,0xc280,0xc380,0xc480,0xc580,0xc680,0xc780,\r |
| 852 | 0xc888,0xc988,0xca88,0xcb88,0xcc88,0xcd88,0xce88,0xcf88,\r |
| 853 | 0xd080,0xd180,0xd280,0xd380,0xd480,0xd580,0xd680,0xd780,\r |
| 854 | 0xd888,0xd988,0xda88,0xdb88,0xdc88,0xdd88,0xde88,0xdf88,\r |
| 855 | 0xe0a0,0xe1a0,0xe2a0,0xe3a0,0xe4a0,0xe5a0,0xe6a0,0xe7a0,\r |
| 856 | 0xe8a8,0xe9a8,0xeaa8,0xeba8,0xeca8,0xeda8,0xeea8,0xefa8,\r |
| 857 | 0xf0a0,0xf1a0,0xf2a0,0xf3a0,0xf4a0,0xf5a0,0xf6a0,0xf7a0,\r |
| 858 | 0xf8a8,0xf9a8,0xfaa8,0xfba8,0xfca8,0xfda8,0xfea8,0xffa8,\r |
| 859 | };\r |
| 860 | \r |
| 861 | /* subTable[i] = ((i & 0xff) << 8) | (i & 0xa8) | (((i & 0xff) == 0) << 6) | 2, i = 0..255 */\r |
| 862 | static const uint16 subTable[256] = {\r |
| 863 | 0x0042,0x0102,0x0202,0x0302,0x0402,0x0502,0x0602,0x0702,\r |
| 864 | 0x080a,0x090a,0x0a0a,0x0b0a,0x0c0a,0x0d0a,0x0e0a,0x0f0a,\r |
| 865 | 0x1002,0x1102,0x1202,0x1302,0x1402,0x1502,0x1602,0x1702,\r |
| 866 | 0x180a,0x190a,0x1a0a,0x1b0a,0x1c0a,0x1d0a,0x1e0a,0x1f0a,\r |
| 867 | 0x2022,0x2122,0x2222,0x2322,0x2422,0x2522,0x2622,0x2722,\r |
| 868 | 0x282a,0x292a,0x2a2a,0x2b2a,0x2c2a,0x2d2a,0x2e2a,0x2f2a,\r |
| 869 | 0x3022,0x3122,0x3222,0x3322,0x3422,0x3522,0x3622,0x3722,\r |
| 870 | 0x382a,0x392a,0x3a2a,0x3b2a,0x3c2a,0x3d2a,0x3e2a,0x3f2a,\r |
| 871 | 0x4002,0x4102,0x4202,0x4302,0x4402,0x4502,0x4602,0x4702,\r |
| 872 | 0x480a,0x490a,0x4a0a,0x4b0a,0x4c0a,0x4d0a,0x4e0a,0x4f0a,\r |
| 873 | 0x5002,0x5102,0x5202,0x5302,0x5402,0x5502,0x5602,0x5702,\r |
| 874 | 0x580a,0x590a,0x5a0a,0x5b0a,0x5c0a,0x5d0a,0x5e0a,0x5f0a,\r |
| 875 | 0x6022,0x6122,0x6222,0x6322,0x6422,0x6522,0x6622,0x6722,\r |
| 876 | 0x682a,0x692a,0x6a2a,0x6b2a,0x6c2a,0x6d2a,0x6e2a,0x6f2a,\r |
| 877 | 0x7022,0x7122,0x7222,0x7322,0x7422,0x7522,0x7622,0x7722,\r |
| 878 | 0x782a,0x792a,0x7a2a,0x7b2a,0x7c2a,0x7d2a,0x7e2a,0x7f2a,\r |
| 879 | 0x8082,0x8182,0x8282,0x8382,0x8482,0x8582,0x8682,0x8782,\r |
| 880 | 0x888a,0x898a,0x8a8a,0x8b8a,0x8c8a,0x8d8a,0x8e8a,0x8f8a,\r |
| 881 | 0x9082,0x9182,0x9282,0x9382,0x9482,0x9582,0x9682,0x9782,\r |
| 882 | 0x988a,0x998a,0x9a8a,0x9b8a,0x9c8a,0x9d8a,0x9e8a,0x9f8a,\r |
| 883 | 0xa0a2,0xa1a2,0xa2a2,0xa3a2,0xa4a2,0xa5a2,0xa6a2,0xa7a2,\r |
| 884 | 0xa8aa,0xa9aa,0xaaaa,0xabaa,0xacaa,0xadaa,0xaeaa,0xafaa,\r |
| 885 | 0xb0a2,0xb1a2,0xb2a2,0xb3a2,0xb4a2,0xb5a2,0xb6a2,0xb7a2,\r |
| 886 | 0xb8aa,0xb9aa,0xbaaa,0xbbaa,0xbcaa,0xbdaa,0xbeaa,0xbfaa,\r |
| 887 | 0xc082,0xc182,0xc282,0xc382,0xc482,0xc582,0xc682,0xc782,\r |
| 888 | 0xc88a,0xc98a,0xca8a,0xcb8a,0xcc8a,0xcd8a,0xce8a,0xcf8a,\r |
| 889 | 0xd082,0xd182,0xd282,0xd382,0xd482,0xd582,0xd682,0xd782,\r |
| 890 | 0xd88a,0xd98a,0xda8a,0xdb8a,0xdc8a,0xdd8a,0xde8a,0xdf8a,\r |
| 891 | 0xe0a2,0xe1a2,0xe2a2,0xe3a2,0xe4a2,0xe5a2,0xe6a2,0xe7a2,\r |
| 892 | 0xe8aa,0xe9aa,0xeaaa,0xebaa,0xecaa,0xedaa,0xeeaa,0xefaa,\r |
| 893 | 0xf0a2,0xf1a2,0xf2a2,0xf3a2,0xf4a2,0xf5a2,0xf6a2,0xf7a2,\r |
| 894 | 0xf8aa,0xf9aa,0xfaaa,0xfbaa,0xfcaa,0xfdaa,0xfeaa,0xffaa,\r |
| 895 | };\r |
| 896 | \r |
| 897 | /* andTable[i] = (i << 8) | (i & 0xa8) | ((i == 0) << 6) | 0x10 | parityTable[i], i = 0..255 */\r |
| 898 | static const uint16 andTable[256] = {\r |
| 899 | 0x0054,0x0110,0x0210,0x0314,0x0410,0x0514,0x0614,0x0710,\r |
| 900 | 0x0818,0x091c,0x0a1c,0x0b18,0x0c1c,0x0d18,0x0e18,0x0f1c,\r |
| 901 | 0x1010,0x1114,0x1214,0x1310,0x1414,0x1510,0x1610,0x1714,\r |
| 902 | 0x181c,0x1918,0x1a18,0x1b1c,0x1c18,0x1d1c,0x1e1c,0x1f18,\r |
| 903 | 0x2030,0x2134,0x2234,0x2330,0x2434,0x2530,0x2630,0x2734,\r |
| 904 | 0x283c,0x2938,0x2a38,0x2b3c,0x2c38,0x2d3c,0x2e3c,0x2f38,\r |
| 905 | 0x3034,0x3130,0x3230,0x3334,0x3430,0x3534,0x3634,0x3730,\r |
| 906 | 0x3838,0x393c,0x3a3c,0x3b38,0x3c3c,0x3d38,0x3e38,0x3f3c,\r |
| 907 | 0x4010,0x4114,0x4214,0x4310,0x4414,0x4510,0x4610,0x4714,\r |
| 908 | 0x481c,0x4918,0x4a18,0x4b1c,0x4c18,0x4d1c,0x4e1c,0x4f18,\r |
| 909 | 0x5014,0x5110,0x5210,0x5314,0x5410,0x5514,0x5614,0x5710,\r |
| 910 | 0x5818,0x591c,0x5a1c,0x5b18,0x5c1c,0x5d18,0x5e18,0x5f1c,\r |
| 911 | 0x6034,0x6130,0x6230,0x6334,0x6430,0x6534,0x6634,0x6730,\r |
| 912 | 0x6838,0x693c,0x6a3c,0x6b38,0x6c3c,0x6d38,0x6e38,0x6f3c,\r |
| 913 | 0x7030,0x7134,0x7234,0x7330,0x7434,0x7530,0x7630,0x7734,\r |
| 914 | 0x783c,0x7938,0x7a38,0x7b3c,0x7c38,0x7d3c,0x7e3c,0x7f38,\r |
| 915 | 0x8090,0x8194,0x8294,0x8390,0x8494,0x8590,0x8690,0x8794,\r |
| 916 | 0x889c,0x8998,0x8a98,0x8b9c,0x8c98,0x8d9c,0x8e9c,0x8f98,\r |
| 917 | 0x9094,0x9190,0x9290,0x9394,0x9490,0x9594,0x9694,0x9790,\r |
| 918 | 0x9898,0x999c,0x9a9c,0x9b98,0x9c9c,0x9d98,0x9e98,0x9f9c,\r |
| 919 | 0xa0b4,0xa1b0,0xa2b0,0xa3b4,0xa4b0,0xa5b4,0xa6b4,0xa7b0,\r |
| 920 | 0xa8b8,0xa9bc,0xaabc,0xabb8,0xacbc,0xadb8,0xaeb8,0xafbc,\r |
| 921 | 0xb0b0,0xb1b4,0xb2b4,0xb3b0,0xb4b4,0xb5b0,0xb6b0,0xb7b4,\r |
| 922 | 0xb8bc,0xb9b8,0xbab8,0xbbbc,0xbcb8,0xbdbc,0xbebc,0xbfb8,\r |
| 923 | 0xc094,0xc190,0xc290,0xc394,0xc490,0xc594,0xc694,0xc790,\r |
| 924 | 0xc898,0xc99c,0xca9c,0xcb98,0xcc9c,0xcd98,0xce98,0xcf9c,\r |
| 925 | 0xd090,0xd194,0xd294,0xd390,0xd494,0xd590,0xd690,0xd794,\r |
| 926 | 0xd89c,0xd998,0xda98,0xdb9c,0xdc98,0xdd9c,0xde9c,0xdf98,\r |
| 927 | 0xe0b0,0xe1b4,0xe2b4,0xe3b0,0xe4b4,0xe5b0,0xe6b0,0xe7b4,\r |
| 928 | 0xe8bc,0xe9b8,0xeab8,0xebbc,0xecb8,0xedbc,0xeebc,0xefb8,\r |
| 929 | 0xf0b4,0xf1b0,0xf2b0,0xf3b4,0xf4b0,0xf5b4,0xf6b4,0xf7b0,\r |
| 930 | 0xf8b8,0xf9bc,0xfabc,0xfbb8,0xfcbc,0xfdb8,0xfeb8,0xffbc,\r |
| 931 | };\r |
| 932 | \r |
| 933 | /* xororTable[i] = (i << 8) | (i & 0xa8) | ((i == 0) << 6) | parityTable[i], i = 0..255 */\r |
| 934 | static const uint16 xororTable[256] = {\r |
| 935 | 0x0044,0x0100,0x0200,0x0304,0x0400,0x0504,0x0604,0x0700,\r |
| 936 | 0x0808,0x090c,0x0a0c,0x0b08,0x0c0c,0x0d08,0x0e08,0x0f0c,\r |
| 937 | 0x1000,0x1104,0x1204,0x1300,0x1404,0x1500,0x1600,0x1704,\r |
| 938 | 0x180c,0x1908,0x1a08,0x1b0c,0x1c08,0x1d0c,0x1e0c,0x1f08,\r |
| 939 | 0x2020,0x2124,0x2224,0x2320,0x2424,0x2520,0x2620,0x2724,\r |
| 940 | 0x282c,0x2928,0x2a28,0x2b2c,0x2c28,0x2d2c,0x2e2c,0x2f28,\r |
| 941 | 0x3024,0x3120,0x3220,0x3324,0x3420,0x3524,0x3624,0x3720,\r |
| 942 | 0x3828,0x392c,0x3a2c,0x3b28,0x3c2c,0x3d28,0x3e28,0x3f2c,\r |
| 943 | 0x4000,0x4104,0x4204,0x4300,0x4404,0x4500,0x4600,0x4704,\r |
| 944 | 0x480c,0x4908,0x4a08,0x4b0c,0x4c08,0x4d0c,0x4e0c,0x4f08,\r |
| 945 | 0x5004,0x5100,0x5200,0x5304,0x5400,0x5504,0x5604,0x5700,\r |
| 946 | 0x5808,0x590c,0x5a0c,0x5b08,0x5c0c,0x5d08,0x5e08,0x5f0c,\r |
| 947 | 0x6024,0x6120,0x6220,0x6324,0x6420,0x6524,0x6624,0x6720,\r |
| 948 | 0x6828,0x692c,0x6a2c,0x6b28,0x6c2c,0x6d28,0x6e28,0x6f2c,\r |
| 949 | 0x7020,0x7124,0x7224,0x7320,0x7424,0x7520,0x7620,0x7724,\r |
| 950 | 0x782c,0x7928,0x7a28,0x7b2c,0x7c28,0x7d2c,0x7e2c,0x7f28,\r |
| 951 | 0x8080,0x8184,0x8284,0x8380,0x8484,0x8580,0x8680,0x8784,\r |
| 952 | 0x888c,0x8988,0x8a88,0x8b8c,0x8c88,0x8d8c,0x8e8c,0x8f88,\r |
| 953 | 0x9084,0x9180,0x9280,0x9384,0x9480,0x9584,0x9684,0x9780,\r |
| 954 | 0x9888,0x998c,0x9a8c,0x9b88,0x9c8c,0x9d88,0x9e88,0x9f8c,\r |
| 955 | 0xa0a4,0xa1a0,0xa2a0,0xa3a4,0xa4a0,0xa5a4,0xa6a4,0xa7a0,\r |
| 956 | 0xa8a8,0xa9ac,0xaaac,0xaba8,0xacac,0xada8,0xaea8,0xafac,\r |
| 957 | 0xb0a0,0xb1a4,0xb2a4,0xb3a0,0xb4a4,0xb5a0,0xb6a0,0xb7a4,\r |
| 958 | 0xb8ac,0xb9a8,0xbaa8,0xbbac,0xbca8,0xbdac,0xbeac,0xbfa8,\r |
| 959 | 0xc084,0xc180,0xc280,0xc384,0xc480,0xc584,0xc684,0xc780,\r |
| 960 | 0xc888,0xc98c,0xca8c,0xcb88,0xcc8c,0xcd88,0xce88,0xcf8c,\r |
| 961 | 0xd080,0xd184,0xd284,0xd380,0xd484,0xd580,0xd680,0xd784,\r |
| 962 | 0xd88c,0xd988,0xda88,0xdb8c,0xdc88,0xdd8c,0xde8c,0xdf88,\r |
| 963 | 0xe0a0,0xe1a4,0xe2a4,0xe3a0,0xe4a4,0xe5a0,0xe6a0,0xe7a4,\r |
| 964 | 0xe8ac,0xe9a8,0xeaa8,0xebac,0xeca8,0xedac,0xeeac,0xefa8,\r |
| 965 | 0xf0a4,0xf1a0,0xf2a0,0xf3a4,0xf4a0,0xf5a4,0xf6a4,0xf7a0,\r |
| 966 | 0xf8a8,0xf9ac,0xfaac,0xfba8,0xfcac,0xfda8,0xfea8,0xffac,\r |
| 967 | };\r |
| 968 | \r |
| 969 | /* rotateShiftTable[i] = (i & 0xa8) | (((i & 0xff) == 0) << 6) | parityTable[i & 0xff], i = 0..255 */\r |
| 970 | static const uint8 rotateShiftTable[256] = {\r |
| 971 | 68, 0, 0, 4, 0, 4, 4, 0, 8, 12, 12, 8, 12, 8, 8, 12,\r |
| 972 | 0, 4, 4, 0, 4, 0, 0, 4, 12, 8, 8, 12, 8, 12, 12, 8,\r |
| 973 | 32, 36, 36, 32, 36, 32, 32, 36, 44, 40, 40, 44, 40, 44, 44, 40,\r |
| 974 | 36, 32, 32, 36, 32, 36, 36, 32, 40, 44, 44, 40, 44, 40, 40, 44,\r |
| 975 | 0, 4, 4, 0, 4, 0, 0, 4, 12, 8, 8, 12, 8, 12, 12, 8,\r |
| 976 | 4, 0, 0, 4, 0, 4, 4, 0, 8, 12, 12, 8, 12, 8, 8, 12,\r |
| 977 | 36, 32, 32, 36, 32, 36, 36, 32, 40, 44, 44, 40, 44, 40, 40, 44,\r |
| 978 | 32, 36, 36, 32, 36, 32, 32, 36, 44, 40, 40, 44, 40, 44, 44, 40,\r |
| 979 | 128,132,132,128,132,128,128,132,140,136,136,140,136,140,140,136,\r |
| 980 | 132,128,128,132,128,132,132,128,136,140,140,136,140,136,136,140,\r |
| 981 | 164,160,160,164,160,164,164,160,168,172,172,168,172,168,168,172,\r |
| 982 | 160,164,164,160,164,160,160,164,172,168,168,172,168,172,172,168,\r |
| 983 | 132,128,128,132,128,132,132,128,136,140,140,136,140,136,136,140,\r |
| 984 | 128,132,132,128,132,128,128,132,140,136,136,140,136,140,140,136,\r |
| 985 | 160,164,164,160,164,160,160,164,172,168,168,172,168,172,172,168,\r |
| 986 | 164,160,160,164,160,164,164,160,168,172,172,168,172,168,168,172,\r |
| 987 | };\r |
| 988 | \r |
| 989 | /* incZ80Table[i] = (i & 0xa8) | (((i & 0xff) == 0) << 6) |\r |
| 990 | (((i & 0xf) == 0) << 4) | ((i == 0x80) << 2), i = 0..256 */\r |
| 991 | static const uint8 incZ80Table[257] = {\r |
| 992 | 80, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 993 | 16, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 994 | 48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,\r |
| 995 | 48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,\r |
| 996 | 16, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 997 | 16, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 998 | 48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,\r |
| 999 | 48, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,\r |
| 1000 | 148,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,\r |
| 1001 | 144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,\r |
| 1002 | 176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,\r |
| 1003 | 176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,\r |
| 1004 | 144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,\r |
| 1005 | 144,128,128,128,128,128,128,128,136,136,136,136,136,136,136,136,\r |
| 1006 | 176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168,\r |
| 1007 | 176,160,160,160,160,160,160,160,168,168,168,168,168,168,168,168, 80,\r |
| 1008 | };\r |
| 1009 | \r |
| 1010 | /* decZ80Table[i] = (i & 0xa8) | (((i & 0xff) == 0) << 6) |\r |
| 1011 | (((i & 0xf) == 0xf) << 4) | ((i == 0x7f) << 2) | 2, i = 0..255 */\r |
| 1012 | static const uint8 decZ80Table[256] = {\r |
| 1013 | 66, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,\r |
| 1014 | 2, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,\r |
| 1015 | 34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 58,\r |
| 1016 | 34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 58,\r |
| 1017 | 2, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,\r |
| 1018 | 2, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 26,\r |
| 1019 | 34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 58,\r |
| 1020 | 34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 62,\r |
| 1021 | 130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,\r |
| 1022 | 130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,\r |
| 1023 | 162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,\r |
| 1024 | 162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,\r |
| 1025 | 130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,\r |
| 1026 | 130,130,130,130,130,130,130,130,138,138,138,138,138,138,138,154,\r |
| 1027 | 162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,\r |
| 1028 | 162,162,162,162,162,162,162,162,170,170,170,170,170,170,170,186,\r |
| 1029 | };\r |
| 1030 | \r |
| 1031 | /* cbitsZ80Table[i] = (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) | ((i >> 8) & 1), i = 0..511 */\r |
| 1032 | static const uint8 cbitsZ80Table[512] = {\r |
| 1033 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1034 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 1035 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1036 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 1037 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1038 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 1039 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1040 | 16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,\r |
| 1041 | 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,\r |
| 1042 | 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,\r |
| 1043 | 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,\r |
| 1044 | 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,\r |
| 1045 | 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,\r |
| 1046 | 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,\r |
| 1047 | 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,\r |
| 1048 | 20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,20,\r |
| 1049 | 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r |
| 1050 | 21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,\r |
| 1051 | 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r |
| 1052 | 21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,\r |
| 1053 | 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r |
| 1054 | 21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,\r |
| 1055 | 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,\r |
| 1056 | 21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,21,\r |
| 1057 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 1058 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 1059 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 1060 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 1061 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 1062 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 1063 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,\r |
| 1064 | 17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,17,\r |
| 1065 | };\r |
| 1066 | \r |
| 1067 | /* cbitsZ80DupTable[i] = (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) |\r |
| 1068 | ((i >> 8) & 1) | (i & 0xa8), i = 0..511 */\r |
| 1069 | static const uint8 cbitsZ80DupTable[512] = {\r |
| 1070 | 0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 1071 | 16, 16, 16, 16, 16, 16, 16, 16, 24, 24, 24, 24, 24, 24, 24, 24,\r |
| 1072 | 32, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,\r |
| 1073 | 48, 48, 48, 48, 48, 48, 48, 48, 56, 56, 56, 56, 56, 56, 56, 56,\r |
| 1074 | 0, 0, 0, 0, 0, 0, 0, 0, 8, 8, 8, 8, 8, 8, 8, 8,\r |
| 1075 | 16, 16, 16, 16, 16, 16, 16, 16, 24, 24, 24, 24, 24, 24, 24, 24,\r |
| 1076 | 32, 32, 32, 32, 32, 32, 32, 32, 40, 40, 40, 40, 40, 40, 40, 40,\r |
| 1077 | 48, 48, 48, 48, 48, 48, 48, 48, 56, 56, 56, 56, 56, 56, 56, 56,\r |
| 1078 | 132,132,132,132,132,132,132,132,140,140,140,140,140,140,140,140,\r |
| 1079 | 148,148,148,148,148,148,148,148,156,156,156,156,156,156,156,156,\r |
| 1080 | 164,164,164,164,164,164,164,164,172,172,172,172,172,172,172,172,\r |
| 1081 | 180,180,180,180,180,180,180,180,188,188,188,188,188,188,188,188,\r |
| 1082 | 132,132,132,132,132,132,132,132,140,140,140,140,140,140,140,140,\r |
| 1083 | 148,148,148,148,148,148,148,148,156,156,156,156,156,156,156,156,\r |
| 1084 | 164,164,164,164,164,164,164,164,172,172,172,172,172,172,172,172,\r |
| 1085 | 180,180,180,180,180,180,180,180,188,188,188,188,188,188,188,188,\r |
| 1086 | 5, 5, 5, 5, 5, 5, 5, 5, 13, 13, 13, 13, 13, 13, 13, 13,\r |
| 1087 | 21, 21, 21, 21, 21, 21, 21, 21, 29, 29, 29, 29, 29, 29, 29, 29,\r |
| 1088 | 37, 37, 37, 37, 37, 37, 37, 37, 45, 45, 45, 45, 45, 45, 45, 45,\r |
| 1089 | 53, 53, 53, 53, 53, 53, 53, 53, 61, 61, 61, 61, 61, 61, 61, 61,\r |
| 1090 | 5, 5, 5, 5, 5, 5, 5, 5, 13, 13, 13, 13, 13, 13, 13, 13,\r |
| 1091 | 21, 21, 21, 21, 21, 21, 21, 21, 29, 29, 29, 29, 29, 29, 29, 29,\r |
| 1092 | 37, 37, 37, 37, 37, 37, 37, 37, 45, 45, 45, 45, 45, 45, 45, 45,\r |
| 1093 | 53, 53, 53, 53, 53, 53, 53, 53, 61, 61, 61, 61, 61, 61, 61, 61,\r |
| 1094 | 129,129,129,129,129,129,129,129,137,137,137,137,137,137,137,137,\r |
| 1095 | 145,145,145,145,145,145,145,145,153,153,153,153,153,153,153,153,\r |
| 1096 | 161,161,161,161,161,161,161,161,169,169,169,169,169,169,169,169,\r |
| 1097 | 177,177,177,177,177,177,177,177,185,185,185,185,185,185,185,185,\r |
| 1098 | 129,129,129,129,129,129,129,129,137,137,137,137,137,137,137,137,\r |
| 1099 | 145,145,145,145,145,145,145,145,153,153,153,153,153,153,153,153,\r |
| 1100 | 161,161,161,161,161,161,161,161,169,169,169,169,169,169,169,169,\r |
| 1101 | 177,177,177,177,177,177,177,177,185,185,185,185,185,185,185,185,\r |
| 1102 | };\r |
| 1103 | \r |
| 1104 | /* cbits2Z80Table[i] = (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) | ((i >> 8) & 1) | 2, i = 0..511 */\r |
| 1105 | static const uint8 cbits2Z80Table[512] = {\r |
| 1106 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 1107 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 1108 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 1109 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 1110 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 1111 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 1112 | 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,\r |
| 1113 | 18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,18,\r |
| 1114 | 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r |
| 1115 | 22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,\r |
| 1116 | 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r |
| 1117 | 22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,\r |
| 1118 | 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r |
| 1119 | 22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,\r |
| 1120 | 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6, 6,\r |
| 1121 | 22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,22,\r |
| 1122 | 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r |
| 1123 | 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,\r |
| 1124 | 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r |
| 1125 | 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,\r |
| 1126 | 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r |
| 1127 | 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,\r |
| 1128 | 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,\r |
| 1129 | 23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,23,\r |
| 1130 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 1131 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1132 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 1133 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1134 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 1135 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1136 | 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,\r |
| 1137 | 19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1138 | };\r |
| 1139 | \r |
| 1140 | /* cbits2Z80DupTable[i] = (i & 0x10) | (((i >> 6) ^ (i >> 5)) & 4) | ((i >> 8) & 1) | 2 |\r |
| 1141 | (i & 0xa8), i = 0..511 */\r |
| 1142 | static const uint8 cbits2Z80DupTable[512] = {\r |
| 1143 | 2, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 10,\r |
| 1144 | 18, 18, 18, 18, 18, 18, 18, 18, 26, 26, 26, 26, 26, 26, 26, 26,\r |
| 1145 | 34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 42,\r |
| 1146 | 50, 50, 50, 50, 50, 50, 50, 50, 58, 58, 58, 58, 58, 58, 58, 58,\r |
| 1147 | 2, 2, 2, 2, 2, 2, 2, 2, 10, 10, 10, 10, 10, 10, 10, 10,\r |
| 1148 | 18, 18, 18, 18, 18, 18, 18, 18, 26, 26, 26, 26, 26, 26, 26, 26,\r |
| 1149 | 34, 34, 34, 34, 34, 34, 34, 34, 42, 42, 42, 42, 42, 42, 42, 42,\r |
| 1150 | 50, 50, 50, 50, 50, 50, 50, 50, 58, 58, 58, 58, 58, 58, 58, 58,\r |
| 1151 | 134,134,134,134,134,134,134,134,142,142,142,142,142,142,142,142,\r |
| 1152 | 150,150,150,150,150,150,150,150,158,158,158,158,158,158,158,158,\r |
| 1153 | 166,166,166,166,166,166,166,166,174,174,174,174,174,174,174,174,\r |
| 1154 | 182,182,182,182,182,182,182,182,190,190,190,190,190,190,190,190,\r |
| 1155 | 134,134,134,134,134,134,134,134,142,142,142,142,142,142,142,142,\r |
| 1156 | 150,150,150,150,150,150,150,150,158,158,158,158,158,158,158,158,\r |
| 1157 | 166,166,166,166,166,166,166,166,174,174,174,174,174,174,174,174,\r |
| 1158 | 182,182,182,182,182,182,182,182,190,190,190,190,190,190,190,190,\r |
| 1159 | 7, 7, 7, 7, 7, 7, 7, 7, 15, 15, 15, 15, 15, 15, 15, 15,\r |
| 1160 | 23, 23, 23, 23, 23, 23, 23, 23, 31, 31, 31, 31, 31, 31, 31, 31,\r |
| 1161 | 39, 39, 39, 39, 39, 39, 39, 39, 47, 47, 47, 47, 47, 47, 47, 47,\r |
| 1162 | 55, 55, 55, 55, 55, 55, 55, 55, 63, 63, 63, 63, 63, 63, 63, 63,\r |
| 1163 | 7, 7, 7, 7, 7, 7, 7, 7, 15, 15, 15, 15, 15, 15, 15, 15,\r |
| 1164 | 23, 23, 23, 23, 23, 23, 23, 23, 31, 31, 31, 31, 31, 31, 31, 31,\r |
| 1165 | 39, 39, 39, 39, 39, 39, 39, 39, 47, 47, 47, 47, 47, 47, 47, 47,\r |
| 1166 | 55, 55, 55, 55, 55, 55, 55, 55, 63, 63, 63, 63, 63, 63, 63, 63,\r |
| 1167 | 131,131,131,131,131,131,131,131,139,139,139,139,139,139,139,139,\r |
| 1168 | 147,147,147,147,147,147,147,147,155,155,155,155,155,155,155,155,\r |
| 1169 | 163,163,163,163,163,163,163,163,171,171,171,171,171,171,171,171,\r |
| 1170 | 179,179,179,179,179,179,179,179,187,187,187,187,187,187,187,187,\r |
| 1171 | 131,131,131,131,131,131,131,131,139,139,139,139,139,139,139,139,\r |
| 1172 | 147,147,147,147,147,147,147,147,155,155,155,155,155,155,155,155,\r |
| 1173 | 163,163,163,163,163,163,163,163,171,171,171,171,171,171,171,171,\r |
| 1174 | 179,179,179,179,179,179,179,179,187,187,187,187,187,187,187,187,\r |
| 1175 | };\r |
| 1176 | \r |
| 1177 | /* negTable[i] = (((i & 0x0f) != 0) << 4) | ((i == 0x80) << 2) | 2 | (i != 0), i = 0..255 */\r |
| 1178 | static const uint8 negTable[256] = {\r |
| 1179 | 2,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1180 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1181 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1182 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1183 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1184 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1185 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1186 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1187 | 7,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1188 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1189 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1190 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1191 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1192 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1193 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1194 | 3,19,19,19,19,19,19,19,19,19,19,19,19,19,19,19,\r |
| 1195 | };\r |
| 1196 | \r |
| 1197 | /* rrdrldTable[i] = (i << 8) | (i & 0xa8) | (((i & 0xff) == 0) << 6) | parityTable[i], i = 0..255 */\r |
| 1198 | static const uint16 rrdrldTable[256] = {\r |
| 1199 | 0x0044,0x0100,0x0200,0x0304,0x0400,0x0504,0x0604,0x0700,\r |
| 1200 | 0x0808,0x090c,0x0a0c,0x0b08,0x0c0c,0x0d08,0x0e08,0x0f0c,\r |
| 1201 | 0x1000,0x1104,0x1204,0x1300,0x1404,0x1500,0x1600,0x1704,\r |
| 1202 | 0x180c,0x1908,0x1a08,0x1b0c,0x1c08,0x1d0c,0x1e0c,0x1f08,\r |
| 1203 | 0x2020,0x2124,0x2224,0x2320,0x2424,0x2520,0x2620,0x2724,\r |
| 1204 | 0x282c,0x2928,0x2a28,0x2b2c,0x2c28,0x2d2c,0x2e2c,0x2f28,\r |
| 1205 | 0x3024,0x3120,0x3220,0x3324,0x3420,0x3524,0x3624,0x3720,\r |
| 1206 | 0x3828,0x392c,0x3a2c,0x3b28,0x3c2c,0x3d28,0x3e28,0x3f2c,\r |
| 1207 | 0x4000,0x4104,0x4204,0x4300,0x4404,0x4500,0x4600,0x4704,\r |
| 1208 | 0x480c,0x4908,0x4a08,0x4b0c,0x4c08,0x4d0c,0x4e0c,0x4f08,\r |
| 1209 | 0x5004,0x5100,0x5200,0x5304,0x5400,0x5504,0x5604,0x5700,\r |
| 1210 | 0x5808,0x590c,0x5a0c,0x5b08,0x5c0c,0x5d08,0x5e08,0x5f0c,\r |
| 1211 | 0x6024,0x6120,0x6220,0x6324,0x6420,0x6524,0x6624,0x6720,\r |
| 1212 | 0x6828,0x692c,0x6a2c,0x6b28,0x6c2c,0x6d28,0x6e28,0x6f2c,\r |
| 1213 | 0x7020,0x7124,0x7224,0x7320,0x7424,0x7520,0x7620,0x7724,\r |
| 1214 | 0x782c,0x7928,0x7a28,0x7b2c,0x7c28,0x7d2c,0x7e2c,0x7f28,\r |
| 1215 | 0x8080,0x8184,0x8284,0x8380,0x8484,0x8580,0x8680,0x8784,\r |
| 1216 | 0x888c,0x8988,0x8a88,0x8b8c,0x8c88,0x8d8c,0x8e8c,0x8f88,\r |
| 1217 | 0x9084,0x9180,0x9280,0x9384,0x9480,0x9584,0x9684,0x9780,\r |
| 1218 | 0x9888,0x998c,0x9a8c,0x9b88,0x9c8c,0x9d88,0x9e88,0x9f8c,\r |
| 1219 | 0xa0a4,0xa1a0,0xa2a0,0xa3a4,0xa4a0,0xa5a4,0xa6a4,0xa7a0,\r |
| 1220 | 0xa8a8,0xa9ac,0xaaac,0xaba8,0xacac,0xada8,0xaea8,0xafac,\r |
| 1221 | 0xb0a0,0xb1a4,0xb2a4,0xb3a0,0xb4a4,0xb5a0,0xb6a0,0xb7a4,\r |
| 1222 | 0xb8ac,0xb9a8,0xbaa8,0xbbac,0xbca8,0xbdac,0xbeac,0xbfa8,\r |
| 1223 | 0xc084,0xc180,0xc280,0xc384,0xc480,0xc584,0xc684,0xc780,\r |
| 1224 | 0xc888,0xc98c,0xca8c,0xcb88,0xcc8c,0xcd88,0xce88,0xcf8c,\r |
| 1225 | 0xd080,0xd184,0xd284,0xd380,0xd484,0xd580,0xd680,0xd784,\r |
| 1226 | 0xd88c,0xd988,0xda88,0xdb8c,0xdc88,0xdd8c,0xde8c,0xdf88,\r |
| 1227 | 0xe0a0,0xe1a4,0xe2a4,0xe3a0,0xe4a4,0xe5a0,0xe6a0,0xe7a4,\r |
| 1228 | 0xe8ac,0xe9a8,0xeaa8,0xebac,0xeca8,0xedac,0xeeac,0xefa8,\r |
| 1229 | 0xf0a4,0xf1a0,0xf2a0,0xf3a4,0xf4a0,0xf5a4,0xf6a4,0xf7a0,\r |
| 1230 | 0xf8a8,0xf9ac,0xfaac,0xfba8,0xfcac,0xfda8,0xfea8,0xffac,\r |
| 1231 | };\r |
| 1232 | \r |
| 1233 | /* cpTable[i] = (i & 0x80) | (((i & 0xff) == 0) << 6), i = 0..255 */\r |
| 1234 | static const uint8 cpTable[256] = {\r |
| 1235 | 64, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1236 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1237 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1238 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1239 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1240 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1241 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1242 | 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,\r |
| 1243 | 128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,\r |
| 1244 | 128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,\r |
| 1245 | 128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,\r |
| 1246 | 128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,\r |
| 1247 | 128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,\r |
| 1248 | 128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,\r |
| 1249 | 128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,\r |
| 1250 | 128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,128,\r |
| 1251 | };\r |
| 1252 | \r |
| 1253 | /* remove comments to generate table contents and define globally NEED_SIM_VM_INIT\r |
| 1254 | static void altairz80_init(void);\r |
| 1255 | void (*sim_vm_init) (void) = &altairz80_init;\r |
| 1256 | static void altairz80_init(void) {\r |
| 1257 | */\r |
| 1258 | /* parityTable */\r |
| 1259 | /*\r |
| 1260 | uint32 i, v;\r |
| 1261 | for (i = 0; i < 256; i++) {\r |
| 1262 | v = ((i & 1) + ((i & 2) >> 1) + ((i & 4) >> 2) + ((i & 8) >> 3) +\r |
| 1263 | ((i & 16) >> 4) + ((i & 32) >> 5) + ((i & 64) >> 6) + ((i & 128) >> 7)) % 2 ? 0 : 4;\r |
| 1264 | printf("%1d,", v);\r |
| 1265 | if ( ((i+1) & 0xf) == 0) {\r |
| 1266 | printf("\n");\r |
| 1267 | }\r |
| 1268 | }\r |
| 1269 | */\r |
| 1270 | /* incTable */\r |
| 1271 | /*\r |
| 1272 | uint32 temp, v;\r |
| 1273 | for (temp = 0; temp <= 256; temp++) {\r |
| 1274 | v = (temp & 0xa8) | (((temp & 0xff) == 0) << 6) | (((temp & 0xf) == 0) << 4);\r |
| 1275 | printf("%3d,", v);\r |
| 1276 | if ( ((temp+1) & 0xf) == 0) {\r |
| 1277 | printf("\n");\r |
| 1278 | }\r |
| 1279 | }\r |
| 1280 | */\r |
| 1281 | /* decTable */\r |
| 1282 | /*\r |
| 1283 | uint32 temp, v;\r |
| 1284 | for (temp = 0; temp < 256; temp++) {\r |
| 1285 | v = (temp & 0xa8) | (((temp & 0xff) == 0) << 6) | (((temp & 0xf) == 0xf) << 4) | 2;\r |
| 1286 | printf("%3d,", v);\r |
| 1287 | if ( ((temp+1) & 0xf) == 0) {\r |
| 1288 | printf("\n");\r |
| 1289 | }\r |
| 1290 | }\r |
| 1291 | */\r |
| 1292 | /* cbitsTable */\r |
| 1293 | /*\r |
| 1294 | uint32 cbits, v;\r |
| 1295 | for (cbits = 0; cbits < 512; cbits++) {\r |
| 1296 | v = (cbits & 0x10) | ((cbits >> 8) & 1);\r |
| 1297 | printf("%2d,", v);\r |
| 1298 | if ( ((cbits+1) & 0xf) == 0) {\r |
| 1299 | printf("\n");\r |
| 1300 | }\r |
| 1301 | }\r |
| 1302 | */\r |
| 1303 | /* cbitsDup8Table */\r |
| 1304 | /*\r |
| 1305 | uint32 cbits, v;\r |
| 1306 | for (cbits = 0; cbits < 512; cbits++) {\r |
| 1307 | v = (cbits & 0x10) | ((cbits >> 8) & 1) | ((cbits & 0xff) << 8) | (cbits & 0xa8) | (((cbits & 0xff) == 0) << 6);\r |
| 1308 | printf("0x%04x,", v);\r |
| 1309 | if ( ((cbits+1) & 0x7) == 0) {\r |
| 1310 | printf("\n");\r |
| 1311 | }\r |
| 1312 | }\r |
| 1313 | */\r |
| 1314 | /* cbitsDup16Table */\r |
| 1315 | /*\r |
| 1316 | uint32 cbits, v;\r |
| 1317 | for (cbits = 0; cbits < 512; cbits++) {\r |
| 1318 | v = (cbits & 0x10) | ((cbits >> 8) & 1) | (cbits & 0x28);\r |
| 1319 | printf("%2d,", v);\r |
| 1320 | if ( ((cbits+1) & 0xf) == 0) {\r |
| 1321 | printf("\n");\r |
| 1322 | }\r |
| 1323 | }\r |
| 1324 | */\r |
| 1325 | /* cbits2Table */\r |
| 1326 | /*\r |
| 1327 | uint32 cbits, v;\r |
| 1328 | for (cbits = 0; cbits < 512; cbits++) {\r |
| 1329 | v = (cbits & 0x10) | ((cbits >> 8) & 1) | 2;\r |
| 1330 | printf("%2d,", v);\r |
| 1331 | if ( ((cbits+1) & 0xf) == 0) {\r |
| 1332 | printf("\n");\r |
| 1333 | }\r |
| 1334 | }\r |
| 1335 | */\r |
| 1336 | /* rrcaTable */\r |
| 1337 | /*\r |
| 1338 | uint32 temp, sum, v;\r |
| 1339 | for (temp = 0; temp < 256; temp++) {\r |
| 1340 | sum = temp >> 1;\r |
| 1341 | v = ((temp & 1) << 15) | (sum << 8) | (sum & 0x28) | (temp & 1);\r |
| 1342 | printf("0x%04x,", v);\r |
| 1343 | if ( ((temp+1) & 0x7) == 0) {\r |
| 1344 | printf("\n");\r |
| 1345 | }\r |
| 1346 | }\r |
| 1347 | */\r |
| 1348 | /* rraTable */\r |
| 1349 | /*\r |
| 1350 | uint32 temp, sum, v;\r |
| 1351 | for (temp = 0; temp < 256; temp++) {\r |
| 1352 | sum = temp >> 1;\r |
| 1353 | v = (sum << 8) | (sum & 0x28) | (temp & 1);\r |
| 1354 | printf("0x%04x,", v);\r |
| 1355 | if ( ((temp+1) & 0x7) == 0) {\r |
| 1356 | printf("\n");\r |
| 1357 | }\r |
| 1358 | }\r |
| 1359 | */\r |
| 1360 | /* addTable */\r |
| 1361 | /*\r |
| 1362 | uint32 sum, v;\r |
| 1363 | for (sum = 0; sum < 512; sum++) {\r |
| 1364 | v = ((sum & 0xff) << 8) | (sum & 0xa8) | (((sum & 0xff) == 0) << 6);\r |
| 1365 | printf("0x%04x,", v);\r |
| 1366 | if ( ((sum+1) & 0x7) == 0) {\r |
| 1367 | printf("\n");\r |
| 1368 | }\r |
| 1369 | }\r |
| 1370 | */\r |
| 1371 | /* subTable */\r |
| 1372 | /*\r |
| 1373 | uint32 sum, v;\r |
| 1374 | for (sum = 0; sum < 256; sum++) {\r |
| 1375 | v = ((sum & 0xff) << 8) | (sum & 0xa8) | (((sum & 0xff) == 0) << 6) | 2;\r |
| 1376 | printf("0x%04x,", v);\r |
| 1377 | if ( ((sum+1) & 0x7) == 0) {\r |
| 1378 | printf("\n");\r |
| 1379 | }\r |
| 1380 | }\r |
| 1381 | */\r |
| 1382 | /* andTable */\r |
| 1383 | /*\r |
| 1384 | uint32 sum, v;\r |
| 1385 | for (sum = 0; sum < 256; sum++) {\r |
| 1386 | v = (sum << 8) | (sum & 0xa8) | ((sum == 0) << 6) | 0x10 | parityTable[sum];\r |
| 1387 | printf("0x%04x,", v);\r |
| 1388 | if ( ((sum+1) & 0x7) == 0) {\r |
| 1389 | printf("\n");\r |
| 1390 | }\r |
| 1391 | }\r |
| 1392 | */\r |
| 1393 | /* xororTable */\r |
| 1394 | /*\r |
| 1395 | uint32 sum, v;\r |
| 1396 | for (sum = 0; sum < 256; sum++) {\r |
| 1397 | v = (sum << 8) | (sum & 0xa8) | ((sum == 0) << 6) | parityTable[sum];\r |
| 1398 | printf("0x%04x,", v);\r |
| 1399 | if ( ((sum+1) & 0x7) == 0) {\r |
| 1400 | printf("\n");\r |
| 1401 | }\r |
| 1402 | }\r |
| 1403 | */\r |
| 1404 | /* rotateShiftTable */\r |
| 1405 | /*\r |
| 1406 | uint32 temp, v;\r |
| 1407 | for (temp = 0; temp < 256; temp++) {\r |
| 1408 | v = (temp & 0xa8) | (((temp & 0xff) == 0) << 6) | PARITY(temp);\r |
| 1409 | printf("%3d,", v);\r |
| 1410 | if ( ((temp+1) & 0xf) == 0) {\r |
| 1411 | printf("\n");\r |
| 1412 | }\r |
| 1413 | }\r |
| 1414 | */\r |
| 1415 | /* incZ80Table */\r |
| 1416 | /*\r |
| 1417 | uint32 temp, v;\r |
| 1418 | for (temp = 0; temp < 256; temp++) {\r |
| 1419 | v = (temp & 0xa8) | (((temp & 0xff) == 0) << 6) |\r |
| 1420 | (((temp & 0xf) == 0) << 4) | ((temp == 0x80) << 2);\r |
| 1421 | printf("%3d,", v);\r |
| 1422 | if ( ((temp+1) & 0xf) == 0) {\r |
| 1423 | printf("\n");\r |
| 1424 | }\r |
| 1425 | }\r |
| 1426 | */\r |
| 1427 | /* decZ80Table */\r |
| 1428 | /*\r |
| 1429 | uint32 temp, v;\r |
| 1430 | for (temp = 0; temp < 256; temp++) {\r |
| 1431 | v = (temp & 0xa8) | (((temp & 0xff) == 0) << 6) |\r |
| 1432 | (((temp & 0xf) == 0xf) << 4) | ((temp == 0x7f) << 2) | 2;\r |
| 1433 | printf("%3d,", v);\r |
| 1434 | if ( ((temp+1) & 0xf) == 0) {\r |
| 1435 | printf("\n");\r |
| 1436 | }\r |
| 1437 | }\r |
| 1438 | */\r |
| 1439 | /* cbitsZ80Table */\r |
| 1440 | /*\r |
| 1441 | uint32 cbits, v;\r |
| 1442 | for (cbits = 0; cbits < 512; cbits++) {\r |
| 1443 | v = (cbits & 0x10) | (((cbits >> 6) ^ (cbits >> 5)) & 4) |\r |
| 1444 | ((cbits >> 8) & 1);\r |
| 1445 | printf("%2d,", v);\r |
| 1446 | if ( ((cbits+1) & 0xf) == 0) {\r |
| 1447 | printf("\n");\r |
| 1448 | }\r |
| 1449 | }\r |
| 1450 | */\r |
| 1451 | /* cbitsZ80DupTable */\r |
| 1452 | /*\r |
| 1453 | uint32 cbits, v;\r |
| 1454 | for (cbits = 0; cbits < 512; cbits++) {\r |
| 1455 | v = (cbits & 0x10) | (((cbits >> 6) ^ (cbits >> 5)) & 4) |\r |
| 1456 | ((cbits >> 8) & 1) | (cbits & 0xa8);\r |
| 1457 | printf("%3d,", v);\r |
| 1458 | if ( ((cbits+1) & 0xf) == 0) {\r |
| 1459 | printf("\n");\r |
| 1460 | }\r |
| 1461 | }\r |
| 1462 | */\r |
| 1463 | /* cbits2Z80Table */\r |
| 1464 | /*\r |
| 1465 | uint32 cbits, v;\r |
| 1466 | for (cbits = 0; cbits < 512; cbits++) {\r |
| 1467 | v = (((cbits >> 6) ^ (cbits >> 5)) & 4) | (cbits & 0x10) | 2 | ((cbits >> 8) & 1);\r |
| 1468 | printf("%2d,", v);\r |
| 1469 | if ( ((cbits+1) & 0xf) == 0) {\r |
| 1470 | printf("\n");\r |
| 1471 | }\r |
| 1472 | }\r |
| 1473 | */\r |
| 1474 | /* cbits2Z80DupTable */\r |
| 1475 | /*\r |
| 1476 | uint32 cbits, v;\r |
| 1477 | for (cbits = 0; cbits < 512; cbits++) {\r |
| 1478 | v = (((cbits >> 6) ^ (cbits >> 5)) & 4) | (cbits & 0x10) | 2 | ((cbits >> 8) & 1) |\r |
| 1479 | (cbits & 0xa8);\r |
| 1480 | printf("%3d,", v);\r |
| 1481 | if ( ((cbits+1) & 0xf) == 0) {\r |
| 1482 | printf("\n");\r |
| 1483 | }\r |
| 1484 | }\r |
| 1485 | */\r |
| 1486 | /* negTable */\r |
| 1487 | /*\r |
| 1488 | uint32 temp, v;\r |
| 1489 | for (temp = 0; temp < 256; temp++) {\r |
| 1490 | v = (((temp & 0x0f) != 0) << 4) | ((temp == 0x80) << 2) | 2 | (temp != 0);\r |
| 1491 | printf("%2d,", v);\r |
| 1492 | if ( ((temp+1) & 0xf) == 0) {\r |
| 1493 | printf("\n");\r |
| 1494 | }\r |
| 1495 | }\r |
| 1496 | */\r |
| 1497 | /* rrdrldTable */\r |
| 1498 | /*\r |
| 1499 | uint32 acu, v;\r |
| 1500 | for (acu = 0; acu < 256; acu++) {\r |
| 1501 | v = (acu << 8) | (acu & 0xa8) | (((acu & 0xff) == 0) << 6) | parityTable[acu];\r |
| 1502 | printf("0x%04x,", v);\r |
| 1503 | if ( ((acu+1) & 0x7) == 0) {\r |
| 1504 | printf("\n");\r |
| 1505 | }\r |
| 1506 | }\r |
| 1507 | */\r |
| 1508 | /* cpTable */\r |
| 1509 | /*\r |
| 1510 | uint32 sum, v;\r |
| 1511 | for (sum = 0; sum < 256; sum++) {\r |
| 1512 | v = (sum & 0x80) | (((sum & 0xff) == 0) << 6);\r |
| 1513 | printf("%3d,", v);\r |
| 1514 | if ( ((sum+1) & 0xf) == 0) {\r |
| 1515 | printf("\n");\r |
| 1516 | }\r |
| 1517 | }\r |
| 1518 | */\r |
| 1519 | /* remove comments to generate table contents\r |
| 1520 | }\r |
| 1521 | */\r |
| 1522 | \r |
| 1523 | /* Memory management */\r |
| 1524 | \r |
| 1525 | #define LOG2PAGESIZE 8\r |
| 1526 | #define PAGESIZE (1 << LOG2PAGESIZE)\r |
| 1527 | \r |
| 1528 | static uint8 M[MAXMEMORY]; /* RAM which is present */\r |
| 1529 | \r |
| 1530 | struct mdev { /* Structure to describe a 2^LOG2PAGESIZE byte page of address space */\r |
| 1531 | /* There are four cases\r |
| 1532 | isRAM isEmpty routine code\r |
| 1533 | TRUE FALSE NULL W page is random access memory (RAM)\r |
| 1534 | FALSE TRUE NULL U no memory at this location\r |
| 1535 | FALSE FALSE NULL R page is read only memory (ROM)\r |
| 1536 | FALSE FALSE not NULL M page is mapped to memory mapped I/O routine\r |
| 1537 | other combinations are undefined!\r |
| 1538 | */\r |
| 1539 | uint32 isRAM;\r |
| 1540 | uint32 isEmpty;\r |
| 1541 | int32 (*routine)(const int32, const int32, const int32);\r |
| 1542 | };\r |
| 1543 | \r |
| 1544 | typedef struct mdev MDEV;\r |
| 1545 | \r |
| 1546 | static MDEV ROM_PAGE = {FALSE, FALSE, NULL}; /* this makes a page ROM */\r |
| 1547 | static MDEV RAM_PAGE = {TRUE, FALSE, NULL}; /* this makes a page RAM */\r |
| 1548 | static MDEV EMPTY_PAGE = {FALSE, TRUE, NULL}; /* this is non-existing memory */\r |
| 1549 | static MDEV mmu_table[MAXMEMORY >> LOG2PAGESIZE];\r |
| 1550 | \r |
| 1551 | /* Memory and I/O Resource Mapping and Unmapping routine. */\r |
| 1552 | uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,\r |
| 1553 | int32 (*routine)(const int32, const int32, const int32), uint8 unmap) {\r |
| 1554 | uint32 page, i, addr;\r |
| 1555 | if (resource_type == RESOURCE_TYPE_MEMORY) {\r |
| 1556 | for (i = 0; i < (size >> LOG2PAGESIZE); i++) {\r |
| 1557 | addr = (baseaddr & 0xfff00) + (i << LOG2PAGESIZE);\r |
| 1558 | if ((cpu_unit.flags & UNIT_CPU_BANKED) && (addr < common))\r |
| 1559 | addr |= bankSelect << MAXBANKSIZELOG2;\r |
| 1560 | page = addr >> LOG2PAGESIZE;\r |
| 1561 | if (cpu_unit.flags & UNIT_CPU_VERBOSE)\r |
| 1562 | printf("%s memory 0x%05x, handler=%p\n", unmap ? "Unmapping" : " Mapping",\r |
| 1563 | addr, routine);\r |
| 1564 | if (unmap) {\r |
| 1565 | if (mmu_table[page].routine == routine) /* unmap only if it was mapped */\r |
| 1566 | if (MEMORYSIZE < MAXBANKSIZE)\r |
| 1567 | if (addr < MEMORYSIZE)\r |
| 1568 | mmu_table[page] = RAM_PAGE;\r |
| 1569 | else\r |
| 1570 | mmu_table[page] = EMPTY_PAGE;\r |
| 1571 | else\r |
| 1572 | mmu_table[page] = RAM_PAGE;\r |
| 1573 | }\r |
| 1574 | else {\r |
| 1575 | mmu_table[page] = ROM_PAGE;\r |
| 1576 | mmu_table[page].routine = routine;\r |
| 1577 | }\r |
| 1578 | }\r |
| 1579 | } else if (resource_type == RESOURCE_TYPE_IO) {\r |
| 1580 | for (i = baseaddr; i < baseaddr + size; i++)\r |
| 1581 | if (unmap) {\r |
| 1582 | if (dev_table[i & 0xff].routine == routine) {\r |
| 1583 | if (cpu_unit.flags & UNIT_CPU_VERBOSE)\r |
| 1584 | printf("Unmapping IO %04x, handler=%p\n", i, routine);\r |
| 1585 | dev_table[i & 0xff].routine = &nulldev;\r |
| 1586 | }\r |
| 1587 | }\r |
| 1588 | else {\r |
| 1589 | if (cpu_unit.flags & UNIT_CPU_VERBOSE)\r |
| 1590 | printf(" Mapping IO %04x, handler=%p\n", i, routine);\r |
| 1591 | dev_table[i & 0xff].routine = routine;\r |
| 1592 | }\r |
| 1593 | } else {\r |
| 1594 | printf("%s: cannot map unknown resource type %d\n", __FUNCTION__, resource_type);\r |
| 1595 | return -1;\r |
| 1596 | }\r |
| 1597 | return 0;\r |
| 1598 | }\r |
| 1599 | \r |
| 1600 | static void PutBYTE(register uint32 Addr, const register uint32 Value) {\r |
| 1601 | MDEV m;\r |
| 1602 | \r |
| 1603 | Addr &= ADDRMASK; /* registers are NOT guaranteed to be always 16-bit values */\r |
| 1604 | if ((cpu_unit.flags & UNIT_CPU_BANKED) && (Addr < common))\r |
| 1605 | Addr |= bankSelect << MAXBANKSIZELOG2;\r |
| 1606 | m = mmu_table[Addr >> LOG2PAGESIZE];\r |
| 1607 | \r |
| 1608 | if (m.isRAM) M[Addr] = Value;\r |
| 1609 | else if (m.routine) m.routine(Addr, 1, Value);\r |
| 1610 | else if (cpu_unit.flags & UNIT_CPU_VERBOSE) {\r |
| 1611 | if (m.isEmpty) {\r |
| 1612 | MESSAGE_2("Attempt to write to non existing memory " ADDRESS_FORMAT ".", Addr);\r |
| 1613 | }\r |
| 1614 | else {\r |
| 1615 | MESSAGE_2("Attempt to write to ROM " ADDRESS_FORMAT ".", Addr);\r |
| 1616 | }\r |
| 1617 | }\r |
| 1618 | }\r |
| 1619 | \r |
| 1620 | void PutBYTEExtended(register uint32 Addr, const register uint32 Value) {\r |
| 1621 | MDEV m;\r |
| 1622 | \r |
| 1623 | Addr &= ADDRMASKEXTENDED;\r |
| 1624 | m = mmu_table[Addr >> LOG2PAGESIZE];\r |
| 1625 | \r |
| 1626 | if (m.isRAM) M[Addr] = Value;\r |
| 1627 | else if (m.routine) m.routine(Addr, 1, Value);\r |
| 1628 | else if (cpu_unit.flags & UNIT_CPU_VERBOSE) {\r |
| 1629 | if (m.isEmpty) {\r |
| 1630 | MESSAGE_2("Attempt to write to non existing memory " ADDRESS_FORMAT ".", Addr);\r |
| 1631 | }\r |
| 1632 | else {\r |
| 1633 | MESSAGE_2("Attempt to write to ROM " ADDRESS_FORMAT ".", Addr);\r |
| 1634 | }\r |
| 1635 | }\r |
| 1636 | }\r |
| 1637 | \r |
| 1638 | static void PutWORD(register uint32 Addr, const register uint32 Value) {\r |
| 1639 | PutBYTE(Addr, Value);\r |
| 1640 | PutBYTE(Addr + 1, Value >> 8);\r |
| 1641 | }\r |
| 1642 | \r |
| 1643 | static uint32 GetBYTE(register uint32 Addr) {\r |
| 1644 | MDEV m;\r |
| 1645 | \r |
| 1646 | Addr &= ADDRMASK; /* registers are NOT guaranteed to be always 16-bit values */\r |
| 1647 | if ((cpu_unit.flags & UNIT_CPU_BANKED) && (Addr < common))\r |
| 1648 | Addr |= bankSelect << MAXBANKSIZELOG2;\r |
| 1649 | m = mmu_table[Addr >> LOG2PAGESIZE];\r |
| 1650 | \r |
| 1651 | if (m.isRAM) return M[Addr]; /* RAM */\r |
| 1652 | if (m.routine) return m.routine(Addr, 0, 0); /* memory mapped I/O */\r |
| 1653 | if (m.isEmpty) {\r |
| 1654 | if (cpu_unit.flags & UNIT_CPU_VERBOSE) {\r |
| 1655 | MESSAGE_2("Attempt to read from non existing memory " ADDRESS_FORMAT ".", Addr);\r |
| 1656 | }\r |
| 1657 | return 0xff;\r |
| 1658 | }\r |
| 1659 | return M[Addr]; /* ROM */\r |
| 1660 | }\r |
| 1661 | \r |
| 1662 | uint32 GetBYTEExtended(register uint32 Addr) {\r |
| 1663 | MDEV m;\r |
| 1664 | \r |
| 1665 | Addr &= ADDRMASKEXTENDED;\r |
| 1666 | m = mmu_table[Addr >> LOG2PAGESIZE];\r |
| 1667 | \r |
| 1668 | if (m.isRAM) return M[Addr];\r |
| 1669 | if (m.routine) return m.routine(Addr, 0, 0);\r |
| 1670 | if (m.isEmpty) {\r |
| 1671 | if (cpu_unit.flags & UNIT_CPU_VERBOSE) {\r |
| 1672 | MESSAGE_2("Attempt to read from non existing memory " ADDRESS_FORMAT ".", Addr);\r |
| 1673 | }\r |
| 1674 | return 0xff;\r |
| 1675 | }\r |
| 1676 | return M[Addr];\r |
| 1677 | }\r |
| 1678 | \r |
| 1679 | int32 getBankSelect(void) {\r |
| 1680 | return bankSelect;\r |
| 1681 | }\r |
| 1682 | \r |
| 1683 | void setBankSelect(const int32 b) {\r |
| 1684 | bankSelect = b;\r |
| 1685 | }\r |
| 1686 | \r |
| 1687 | uint32 getCommon(void) {\r |
| 1688 | return common;\r |
| 1689 | }\r |
| 1690 | \r |
| 1691 | /* memory access during a simulation */\r |
| 1692 | uint8 GetBYTEWrapper(const uint32 Addr) {\r |
| 1693 | if (chiptype == CHIP_TYPE_8086)\r |
| 1694 | return GetBYTEExtended(Addr);\r |
| 1695 | else if (cpu_unit.flags & UNIT_CPU_MMU)\r |
| 1696 | return GetBYTE(Addr);\r |
| 1697 | else\r |
| 1698 | return MOPT[Addr & ADDRMASK];\r |
| 1699 | }\r |
| 1700 | \r |
| 1701 | /* memory access during a simulation */\r |
| 1702 | void PutBYTEWrapper(const uint32 Addr, const uint32 Value) {\r |
| 1703 | if (chiptype == CHIP_TYPE_8086)\r |
| 1704 | PutBYTEExtended(Addr, Value);\r |
| 1705 | else if (cpu_unit.flags & UNIT_CPU_MMU)\r |
| 1706 | PutBYTE(Addr, Value);\r |
| 1707 | else\r |
| 1708 | MOPT[Addr & ADDRMASK] = Value & 0xff;\r |
| 1709 | }\r |
| 1710 | \r |
| 1711 | #define RAM_PP(Addr) GetBYTE(Addr++)\r |
| 1712 | #define RAM_MM(Addr) GetBYTE(Addr--)\r |
| 1713 | #define GET_WORD(Addr) (GetBYTE(Addr) | (GetBYTE(Addr + 1) << 8))\r |
| 1714 | #define PUT_BYTE_PP(a,v) PutBYTE(a++, v)\r |
| 1715 | #define PUT_BYTE_MM(a,v) PutBYTE(a--, v)\r |
| 1716 | #define MM_PUT_BYTE(a,v) PutBYTE(--a, v)\r |
| 1717 | \r |
| 1718 | #define MASK_BRK (TRUE + 1)\r |
| 1719 | \r |
| 1720 | /* this is a modified version of sim_brk_test with two differences:\r |
| 1721 | 1) is does not set sim_brk_pend to FALSE (this is left to the instruction decode)\r |
| 1722 | 2) it returns MASK_BRK if a breakpoint is found but should be ignored\r |
| 1723 | */\r |
| 1724 | static int32 sim_brk_lookup (const t_addr loc, const int32 btyp) {\r |
| 1725 | extern t_bool sim_brk_pend[SIM_BKPT_N_SPC];\r |
| 1726 | extern t_addr sim_brk_ploc[SIM_BKPT_N_SPC];\r |
| 1727 | extern char *sim_brk_act;\r |
| 1728 | BRKTAB *bp;\r |
| 1729 | if ((bp = sim_brk_fnd (loc)) && /* entry in table? */\r |
| 1730 | (btyp & bp -> typ) && /* type match? */\r |
| 1731 | (!sim_brk_pend[0] || (loc != sim_brk_ploc[0])) && /* new location? */\r |
| 1732 | (--(bp -> cnt) <= 0)) { /* count reach 0? */\r |
| 1733 | bp -> cnt = 0; /* reset count */\r |
| 1734 | sim_brk_ploc[0] = loc; /* save location */\r |
| 1735 | sim_brk_act = bp -> act; /* set up actions */\r |
| 1736 | sim_brk_pend[0] = TRUE; /* don't do twice */\r |
| 1737 | return TRUE;\r |
| 1738 | }\r |
| 1739 | return (sim_brk_pend[0] && (loc == sim_brk_ploc[0])) ? MASK_BRK : FALSE;\r |
| 1740 | }\r |
| 1741 | \r |
| 1742 | static void prepareMemoryAccessMessage(t_addr loc) {\r |
| 1743 | extern char memoryAccessMessage[];\r |
| 1744 | sprintf(memoryAccessMessage, "Memory access breakpoint [%04xh]", loc);\r |
| 1745 | }\r |
| 1746 | \r |
| 1747 | #define PUSH(x) { \\r |
| 1748 | MM_PUT_BYTE(SP, (x) >> 8); \\r |
| 1749 | MM_PUT_BYTE(SP, x); \\r |
| 1750 | }\r |
| 1751 | \r |
| 1752 | #define CHECK_BREAK_BYTE(a) \\r |
| 1753 | if (sim_brk_summ && sim_brk_test((a) & 0xffff, SWMASK('M'))) { \\r |
| 1754 | reason = STOP_MEM; \\r |
| 1755 | prepareMemoryAccessMessage((a) & 0xffff); \\r |
| 1756 | goto end_decode; \\r |
| 1757 | }\r |
| 1758 | \r |
| 1759 | #define CHECK_BREAK_TWO_BYTES_EXTENDED(a1, a2, iCode) \\r |
| 1760 | if (sim_brk_summ) { \\r |
| 1761 | br1 = sim_brk_lookup((a1) & 0xffff, SWMASK('M')); \\r |
| 1762 | br2 = br1 ? FALSE : sim_brk_lookup((a2) & 0xffff, SWMASK('M'));\\r |
| 1763 | if ((br1 == MASK_BRK) || (br2 == MASK_BRK)) { \\r |
| 1764 | sim_brk_pend[0] = FALSE; \\r |
| 1765 | } \\r |
| 1766 | else if (br1 || br2) { \\r |
| 1767 | reason = STOP_MEM; \\r |
| 1768 | if (br1) { \\r |
| 1769 | prepareMemoryAccessMessage((a1) & 0xffff); \\r |
| 1770 | } \\r |
| 1771 | else { \\r |
| 1772 | prepareMemoryAccessMessage((a2) & 0xffff); \\r |
| 1773 | } \\r |
| 1774 | iCode; \\r |
| 1775 | goto end_decode; \\r |
| 1776 | } \\r |
| 1777 | else { \\r |
| 1778 | sim_brk_pend[0] = FALSE; \\r |
| 1779 | } \\r |
| 1780 | }\r |
| 1781 | \r |
| 1782 | #define CHECK_BREAK_TWO_BYTES(a1, a2) CHECK_BREAK_TWO_BYTES_EXTENDED(a1, a2,;)\r |
| 1783 | \r |
| 1784 | #define CHECK_BREAK_WORD(a) CHECK_BREAK_TWO_BYTES(a, (a + 1))\r |
| 1785 | \r |
| 1786 | #define HALTINSTRUCTION 0x76\r |
| 1787 | \r |
| 1788 | /* Macros for the IN/OUT instructions INI/INIR/IND/INDR/OUTI/OTIR/OUTD/OTDR\r |
| 1789 | \r |
| 1790 | Pre condition\r |
| 1791 | temp == value of register B at entry of the instruction\r |
| 1792 | acu == value of transferred byte (IN or OUT)\r |
| 1793 | Post condition\r |
| 1794 | F is set correctly\r |
| 1795 | \r |
| 1796 | Use INOUTFLAGS_ZERO(x) for INIR/INDR/OTIR/OTDR where\r |
| 1797 | x == (C + 1) & 0xff for INIR\r |
| 1798 | x == L for OTIR and OTDR\r |
| 1799 | x == (C - 1) & 0xff for INDR\r |
| 1800 | Use INOUTFLAGS_NONZERO(x) for INI/IND/OUTI/OUTD where\r |
| 1801 | x == (C + 1) & 0xff for INI\r |
| 1802 | x == L for OUTI and OUTD\r |
| 1803 | x == (C - 1) & 0xff for IND\r |
| 1804 | */\r |
| 1805 | #define INOUTFLAGS(syxz, x) \\r |
| 1806 | AF = (AF & 0xff00) | (syxz) | /* SF, YF, XF, ZF */ \\r |
| 1807 | ((acu & 0x80) >> 6) | /* NF */ \\r |
| 1808 | ((acu + (x)) > 0xff ? (FLAG_C | FLAG_H) : 0) | /* CF, HF */ \\r |
| 1809 | parityTable[((acu + (x)) & 7) ^ temp] /* PF */\r |
| 1810 | \r |
| 1811 | #define INOUTFLAGS_ZERO(x) INOUTFLAGS(FLAG_Z, x)\r |
| 1812 | #define INOUTFLAGS_NONZERO(x) \\r |
| 1813 | INOUTFLAGS((HIGH_REGISTER(BC) & 0xa8) | ((HIGH_REGISTER(BC) == 0) << 6), x)\r |
| 1814 | \r |
| 1815 | t_stat sim_instr (void) {\r |
| 1816 | uint32 i;\r |
| 1817 | t_stat result;\r |
| 1818 | if (chiptype == CHIP_TYPE_8086) return sim_instr_8086();\r |
| 1819 | if (cpu_unit.flags & UNIT_CPU_MMU) return sim_instr_mmu();\r |
| 1820 | for (i = 0; i < MAXBANKSIZE; i++) MOPT[i] = M[i];\r |
| 1821 | result = sim_instr_nommu();\r |
| 1822 | for (i = 0; i < MAXBANKSIZE; i++) M[i] = MOPT[i];\r |
| 1823 | return result;\r |
| 1824 | }\r |
| 1825 | \r |
| 1826 | static t_stat sim_instr_mmu (void) {\r |
| 1827 | extern int32 sim_interval;\r |
| 1828 | extern t_bool sim_brk_pend[SIM_BKPT_N_SPC];\r |
| 1829 | extern int32 timerInterrupt;\r |
| 1830 | extern int32 timerInterruptHandler;\r |
| 1831 | extern int32 keyboardInterrupt;\r |
| 1832 | extern uint32 keyboardInterruptHandler;\r |
| 1833 | extern uint32 sim_os_msec(void);\r |
| 1834 | extern const t_bool rtc_avail;\r |
| 1835 | extern uint32 sim_brk_summ;\r |
| 1836 | int32 reason = 0;\r |
| 1837 | register uint32 specialProcessing;\r |
| 1838 | register uint32 AF;\r |
| 1839 | register uint32 BC;\r |
| 1840 | register uint32 DE;\r |
| 1841 | register uint32 HL;\r |
| 1842 | register uint32 PC;\r |
| 1843 | register uint32 SP;\r |
| 1844 | register uint32 IX;\r |
| 1845 | register uint32 IY;\r |
| 1846 | register uint32 temp = 0;\r |
| 1847 | register uint32 acu = 0;\r |
| 1848 | register uint32 sum;\r |
| 1849 | register uint32 cbits;\r |
| 1850 | register uint32 op;\r |
| 1851 | register uint32 adr;\r |
| 1852 | /* tStates contains the number of t-states executed. One t-state is executed\r |
| 1853 | in one microsecond on a 1MHz CPU. tStates is used for real-time simulations. */\r |
| 1854 | register uint32 tStates;\r |
| 1855 | uint32 tStatesInSlice; /* number of t-states in 10 mSec time-slice */\r |
| 1856 | uint32 startTime, now;\r |
| 1857 | int32 br1, br2, tStateModifier = FALSE;\r |
| 1858 | \r |
| 1859 | AF = AF_S;\r |
| 1860 | BC = BC_S;\r |
| 1861 | DE = DE_S;\r |
| 1862 | HL = HL_S;\r |
| 1863 | PC = PC_S & ADDRMASK;\r |
| 1864 | SP = SP_S;\r |
| 1865 | IX = IX_S;\r |
| 1866 | IY = IY_S;\r |
| 1867 | specialProcessing = clockFrequency | timerInterrupt | keyboardInterrupt | sim_brk_summ;\r |
| 1868 | tStates = 0;\r |
| 1869 | if (rtc_avail) {\r |
| 1870 | startTime = sim_os_msec();\r |
| 1871 | tStatesInSlice = sliceLength*clockFrequency;\r |
| 1872 | }\r |
| 1873 | else { /* make sure that sim_os_msec() is not called later */\r |
| 1874 | clockFrequency = startTime = tStatesInSlice = 0;\r |
| 1875 | }\r |
| 1876 | \r |
| 1877 | /* main instruction fetch/decode loop */\r |
| 1878 | while (TRUE) { /* loop until halted */\r |
| 1879 | if (sim_interval <= 0) { /* check clock queue */\r |
| 1880 | #if !UNIX_PLATFORM\r |
| 1881 | if ((reason = sim_os_poll_kbd()) == SCPE_STOP) { /* poll on platforms without reliable signalling */\r |
| 1882 | break;\r |
| 1883 | }\r |
| 1884 | #endif\r |
| 1885 | if ( (reason = sim_process_event()) ) break;\r |
| 1886 | else\r |
| 1887 | specialProcessing = clockFrequency | timerInterrupt | keyboardInterrupt | sim_brk_summ;\r |
| 1888 | }\r |
| 1889 | \r |
| 1890 | if (specialProcessing) { /* quick check for special processing */\r |
| 1891 | if (clockFrequency && (tStates >= tStatesInSlice)) {\r |
| 1892 | /* clockFrequency != 0 implies that real time clock is available */\r |
| 1893 | startTime += sliceLength;\r |
| 1894 | tStates -= tStatesInSlice;\r |
| 1895 | if (startTime > (now = sim_os_msec())) {\r |
| 1896 | #if defined (_WIN32)\r |
| 1897 | Sleep(startTime - now);\r |
| 1898 | #else\r |
| 1899 | usleep(1000 * (startTime - now));\r |
| 1900 | #endif\r |
| 1901 | }\r |
| 1902 | }\r |
| 1903 | \r |
| 1904 | if (timerInterrupt && (IFF_S & 1)) {\r |
| 1905 | timerInterrupt = FALSE;\r |
| 1906 | specialProcessing = clockFrequency | sim_brk_summ;\r |
| 1907 | IFF_S = 0; /* disable interrupts */\r |
| 1908 | CHECK_BREAK_TWO_BYTES_EXTENDED(SP - 2, SP - 1, (timerInterrupt = TRUE, IFF_S |= 1));\r |
| 1909 | if ((GetBYTE(PC) == HALTINSTRUCTION) && ((cpu_unit.flags & UNIT_CPU_STOPONHALT) == 0)) {\r |
| 1910 | PUSH(PC + 1);\r |
| 1911 | PCQ_ENTRY(PC);\r |
| 1912 | }\r |
| 1913 | else {\r |
| 1914 | PUSH(PC);\r |
| 1915 | PCQ_ENTRY(PC - 1);\r |
| 1916 | }\r |
| 1917 | PC = timerInterruptHandler & ADDRMASK;\r |
| 1918 | }\r |
| 1919 | \r |
| 1920 | if (keyboardInterrupt && (IFF_S & 1)) {\r |
| 1921 | keyboardInterrupt = FALSE;\r |
| 1922 | specialProcessing = clockFrequency | sim_brk_summ;\r |
| 1923 | IFF_S = 0; /* disable interrupts */\r |
| 1924 | CHECK_BREAK_TWO_BYTES_EXTENDED(SP - 2, SP - 1, (keyboardInterrupt = TRUE, IFF_S |= 1));\r |
| 1925 | if ((GetBYTE(PC) == HALTINSTRUCTION) && ((cpu_unit.flags & UNIT_CPU_STOPONHALT) == 0)) {\r |
| 1926 | PUSH(PC + 1);\r |
| 1927 | PCQ_ENTRY(PC);\r |
| 1928 | }\r |
| 1929 | else {\r |
| 1930 | PUSH(PC);\r |
| 1931 | PCQ_ENTRY(PC - 1);\r |
| 1932 | }\r |
| 1933 | PC = keyboardInterruptHandler & ADDRMASK;\r |
| 1934 | }\r |
| 1935 | \r |
| 1936 | if (sim_brk_summ) {\r |
| 1937 | if (sim_brk_lookup(PC, SWMASK('E')) == TRUE) { /* breakpoint? */\r |
| 1938 | reason = STOP_IBKPT; /* stop simulation */\r |
| 1939 | break;\r |
| 1940 | }\r |
| 1941 | if (sim_brk_test(GetBYTE(PC), (1u << SIM_BKPT_V_SPC) | SWMASK('I'))) { /* instruction breakpoint? */\r |
| 1942 | reason = STOP_IBKPT; /* stop simulation */\r |
| 1943 | break;\r |
| 1944 | }\r |
| 1945 | }\r |
| 1946 | }\r |
| 1947 | \r |
| 1948 | PCX = PC;\r |
| 1949 | sim_interval--;\r |
| 1950 | \r |
| 1951 | /* make sure that each instructions properly sets sim_brk_pend:\r |
| 1952 | 1) Either directly to FALSE if no memory access takes place or\r |
| 1953 | 2) through a call to a Check... routine\r |
| 1954 | */\r |
| 1955 | switch(RAM_PP(PC)) {\r |
| 1956 | \r |
| 1957 | case 0x00: /* NOP */\r |
| 1958 | tStates += 4;\r |
| 1959 | sim_brk_pend[0] = FALSE;\r |
| 1960 | break;\r |
| 1961 | \r |
| 1962 | case 0x01: /* LD BC,nnnn */\r |
| 1963 | tStates += 10;\r |
| 1964 | sim_brk_pend[0] = FALSE;\r |
| 1965 | BC = GET_WORD(PC);\r |
| 1966 | PC += 2;\r |
| 1967 | break;\r |
| 1968 | \r |
| 1969 | case 0x02: /* LD (BC),A */\r |
| 1970 | tStates += 7;\r |
| 1971 | CHECK_BREAK_BYTE(BC)\r |
| 1972 | PutBYTE(BC, HIGH_REGISTER(AF));\r |
| 1973 | break;\r |
| 1974 | \r |
| 1975 | case 0x03: /* INC BC */\r |
| 1976 | tStates += 6;\r |
| 1977 | sim_brk_pend[0] = FALSE;\r |
| 1978 | ++BC;\r |
| 1979 | break;\r |
| 1980 | \r |
| 1981 | case 0x04: /* INC B */\r |
| 1982 | tStates += 4;\r |
| 1983 | sim_brk_pend[0] = FALSE;\r |
| 1984 | BC += 0x100;\r |
| 1985 | temp = HIGH_REGISTER(BC);\r |
| 1986 | AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80); /* SET_PV2 uses temp */\r |
| 1987 | break;\r |
| 1988 | \r |
| 1989 | case 0x05: /* DEC B */\r |
| 1990 | tStates += 4;\r |
| 1991 | sim_brk_pend[0] = FALSE;\r |
| 1992 | BC -= 0x100;\r |
| 1993 | temp = HIGH_REGISTER(BC);\r |
| 1994 | AF = (AF & ~0xfe) | decTable[temp] | SET_PV2(0x7f); /* SET_PV2 uses temp */\r |
| 1995 | break;\r |
| 1996 | \r |
| 1997 | case 0x06: /* LD B,nn */\r |
| 1998 | tStates += 7;\r |
| 1999 | sim_brk_pend[0] = FALSE;\r |
| 2000 | SET_HIGH_REGISTER(BC, RAM_PP(PC));\r |
| 2001 | break;\r |
| 2002 | \r |
| 2003 | case 0x07: /* RLCA */\r |
| 2004 | tStates += 4;\r |
| 2005 | sim_brk_pend[0] = FALSE;\r |
| 2006 | AF = ((AF >> 7) & 0x0128) | ((AF << 1) & ~0x1ff) |\r |
| 2007 | (AF & 0xc4) | ((AF >> 15) & 1);\r |
| 2008 | break;\r |
| 2009 | \r |
| 2010 | case 0x08: /* EX AF,AF' */\r |
| 2011 | tStates += 4;\r |
| 2012 | sim_brk_pend[0] = FALSE;\r |
| 2013 | CHECK_CPU_8080;\r |
| 2014 | temp = AF;\r |
| 2015 | AF = AF1_S;\r |
| 2016 | AF1_S = temp;\r |
| 2017 | break;\r |
| 2018 | \r |
| 2019 | case 0x09: /* ADD HL,BC */\r |
| 2020 | tStates += 11;\r |
| 2021 | sim_brk_pend[0] = FALSE;\r |
| 2022 | HL &= ADDRMASK;\r |
| 2023 | BC &= ADDRMASK;\r |
| 2024 | sum = HL + BC;\r |
| 2025 | AF = (AF & ~0x3b) | ((sum >> 8) & 0x28) | cbitsTable[(HL ^ BC ^ sum) >> 8];\r |
| 2026 | HL = sum;\r |
| 2027 | break;\r |
| 2028 | \r |
| 2029 | case 0x0a: /* LD A,(BC) */\r |
| 2030 | tStates += 7;\r |
| 2031 | CHECK_BREAK_BYTE(BC)\r |
| 2032 | SET_HIGH_REGISTER(AF, GetBYTE(BC));\r |
| 2033 | break;\r |
| 2034 | \r |
| 2035 | case 0x0b: /* DEC BC */\r |
| 2036 | tStates += 6;\r |
| 2037 | sim_brk_pend[0] = FALSE;\r |
| 2038 | --BC;\r |
| 2039 | break;\r |
| 2040 | \r |
| 2041 | case 0x0c: /* INC C */\r |
| 2042 | tStates += 4;\r |
| 2043 | sim_brk_pend[0] = FALSE;\r |
| 2044 | temp = LOW_REGISTER(BC) + 1;\r |
| 2045 | SET_LOW_REGISTER(BC, temp);\r |
| 2046 | AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80);\r |
| 2047 | break;\r |
| 2048 | \r |
| 2049 | case 0x0d: /* DEC C */\r |
| 2050 | tStates += 4;\r |
| 2051 | sim_brk_pend[0] = FALSE;\r |
| 2052 | temp = LOW_REGISTER(BC) - 1;\r |
| 2053 | SET_LOW_REGISTER(BC, temp);\r |
| 2054 | AF = (AF & ~0xfe) | decTable[temp & 0xff] | SET_PV2(0x7f);\r |
| 2055 | break;\r |
| 2056 | \r |
| 2057 | case 0x0e: /* LD C,nn */\r |
| 2058 | tStates += 7;\r |
| 2059 | sim_brk_pend[0] = FALSE;\r |
| 2060 | SET_LOW_REGISTER(BC, RAM_PP(PC));\r |
| 2061 | break;\r |
| 2062 | \r |
| 2063 | case 0x0f: /* RRCA */\r |
| 2064 | tStates += 4;\r |
| 2065 | sim_brk_pend[0] = FALSE;\r |
| 2066 | AF = (AF & 0xc4) | rrcaTable[HIGH_REGISTER(AF)];\r |
| 2067 | break;\r |
| 2068 | \r |
| 2069 | case 0x10: /* DJNZ dd */\r |
| 2070 | sim_brk_pend[0] = FALSE;\r |
| 2071 | CHECK_CPU_8080;\r |
| 2072 | if ((BC -= 0x100) & 0xff00) {\r |
| 2073 | PCQ_ENTRY(PCX);\r |
| 2074 | PC += (int8) GetBYTE(PC) + 1;\r |
| 2075 | tStates += 13;\r |
| 2076 | }\r |
| 2077 | else {\r |
| 2078 | PC++;\r |
| 2079 | tStates += 8;\r |
| 2080 | }\r |
| 2081 | break;\r |
| 2082 | \r |
| 2083 | case 0x11: /* LD DE,nnnn */\r |
| 2084 | tStates += 10;\r |
| 2085 | sim_brk_pend[0] = FALSE;\r |
| 2086 | DE = GET_WORD(PC);\r |
| 2087 | PC += 2;\r |
| 2088 | break;\r |
| 2089 | \r |
| 2090 | case 0x12: /* LD (DE),A */\r |
| 2091 | tStates += 7;\r |
| 2092 | CHECK_BREAK_BYTE(DE)\r |
| 2093 | PutBYTE(DE, HIGH_REGISTER(AF));\r |
| 2094 | break;\r |
| 2095 | \r |
| 2096 | case 0x13: /* INC DE */\r |
| 2097 | tStates += 6;\r |
| 2098 | sim_brk_pend[0] = FALSE;\r |
| 2099 | ++DE;\r |
| 2100 | break;\r |
| 2101 | \r |
| 2102 | case 0x14: /* INC D */\r |
| 2103 | tStates += 4;\r |
| 2104 | sim_brk_pend[0] = FALSE;\r |
| 2105 | DE += 0x100;\r |
| 2106 | temp = HIGH_REGISTER(DE);\r |
| 2107 | AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80); /* SET_PV2 uses temp */\r |
| 2108 | break;\r |
| 2109 | \r |
| 2110 | case 0x15: /* DEC D */\r |
| 2111 | tStates += 4;\r |
| 2112 | sim_brk_pend[0] = FALSE;\r |
| 2113 | DE -= 0x100;\r |
| 2114 | temp = HIGH_REGISTER(DE);\r |
| 2115 | AF = (AF & ~0xfe) | decTable[temp] | SET_PV2(0x7f); /* SET_PV2 uses temp */\r |
| 2116 | break;\r |
| 2117 | \r |
| 2118 | case 0x16: /* LD D,nn */\r |
| 2119 | tStates += 7;\r |
| 2120 | sim_brk_pend[0] = FALSE;\r |
| 2121 | SET_HIGH_REGISTER(DE, RAM_PP(PC));\r |
| 2122 | break;\r |
| 2123 | \r |
| 2124 | case 0x17: /* RLA */\r |
| 2125 | tStates += 4;\r |
| 2126 | sim_brk_pend[0] = FALSE;\r |
| 2127 | AF = ((AF << 8) & 0x0100) | ((AF >> 7) & 0x28) | ((AF << 1) & ~0x01ff) |\r |
| 2128 | (AF & 0xc4) | ((AF >> 15) & 1);\r |
| 2129 | break;\r |
| 2130 | \r |
| 2131 | case 0x18: /* JR dd */\r |
| 2132 | tStates += 12;\r |
| 2133 | sim_brk_pend[0] = FALSE;\r |
| 2134 | CHECK_CPU_8080;\r |
| 2135 | PCQ_ENTRY(PCX);\r |
| 2136 | PC += (int8) GetBYTE(PC) + 1;\r |
| 2137 | break;\r |
| 2138 | \r |
| 2139 | case 0x19: /* ADD HL,DE */\r |
| 2140 | tStates += 11;\r |
| 2141 | sim_brk_pend[0] = FALSE;\r |
| 2142 | HL &= ADDRMASK;\r |
| 2143 | DE &= ADDRMASK;\r |
| 2144 | sum = HL + DE;\r |
| 2145 | AF = (AF & ~0x3b) | ((sum >> 8) & 0x28) | cbitsTable[(HL ^ DE ^ sum) >> 8];\r |
| 2146 | HL = sum;\r |
| 2147 | break;\r |
| 2148 | \r |
| 2149 | case 0x1a: /* LD A,(DE) */\r |
| 2150 | tStates += 7;\r |
| 2151 | CHECK_BREAK_BYTE(DE)\r |
| 2152 | SET_HIGH_REGISTER(AF, GetBYTE(DE));\r |
| 2153 | break;\r |
| 2154 | \r |
| 2155 | case 0x1b: /* DEC DE */\r |
| 2156 | tStates += 6;\r |
| 2157 | sim_brk_pend[0] = FALSE;\r |
| 2158 | --DE;\r |
| 2159 | break;\r |
| 2160 | \r |
| 2161 | case 0x1c: /* INC E */\r |
| 2162 | tStates += 4;\r |
| 2163 | sim_brk_pend[0] = FALSE;\r |
| 2164 | temp = LOW_REGISTER(DE) + 1;\r |
| 2165 | SET_LOW_REGISTER(DE, temp);\r |
| 2166 | AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80);\r |
| 2167 | break;\r |
| 2168 | \r |
| 2169 | case 0x1d: /* DEC E */\r |
| 2170 | tStates += 4;\r |
| 2171 | sim_brk_pend[0] = FALSE;\r |
| 2172 | temp = LOW_REGISTER(DE) - 1;\r |
| 2173 | SET_LOW_REGISTER(DE, temp);\r |
| 2174 | AF = (AF & ~0xfe) | decTable[temp & 0xff] | SET_PV2(0x7f);\r |
| 2175 | break;\r |
| 2176 | \r |
| 2177 | case 0x1e: /* LD E,nn */\r |
| 2178 | tStates += 7;\r |
| 2179 | sim_brk_pend[0] = FALSE;\r |
| 2180 | SET_LOW_REGISTER(DE, RAM_PP(PC));\r |
| 2181 | break;\r |
| 2182 | \r |
| 2183 | case 0x1f: /* RRA */\r |
| 2184 | tStates += 4;\r |
| 2185 | sim_brk_pend[0] = FALSE;\r |
| 2186 | AF = ((AF & 1) << 15) | (AF & 0xc4) | rraTable[HIGH_REGISTER(AF)];\r |
| 2187 | break;\r |
| 2188 | \r |
| 2189 | case 0x20: /* JR NZ,dd */\r |
| 2190 | sim_brk_pend[0] = FALSE;\r |
| 2191 | CHECK_CPU_8080;\r |
| 2192 | if (TSTFLAG(Z)) {\r |
| 2193 | PC++;\r |
| 2194 | tStates += 7;\r |
| 2195 | }\r |
| 2196 | else {\r |
| 2197 | PCQ_ENTRY(PCX);\r |
| 2198 | PC += (int8) GetBYTE(PC) + 1;\r |
| 2199 | tStates += 12;\r |
| 2200 | }\r |
| 2201 | break;\r |
| 2202 | \r |
| 2203 | case 0x21: /* LD HL,nnnn */\r |
| 2204 | tStates += 10;\r |
| 2205 | sim_brk_pend[0] = FALSE;\r |
| 2206 | HL = GET_WORD(PC);\r |
| 2207 | PC += 2;\r |
| 2208 | break;\r |
| 2209 | \r |
| 2210 | case 0x22: /* LD (nnnn),HL */\r |
| 2211 | tStates += 16;\r |
| 2212 | temp = GET_WORD(PC);\r |
| 2213 | CHECK_BREAK_WORD(temp);\r |
| 2214 | PutWORD(temp, HL);\r |
| 2215 | PC += 2;\r |
| 2216 | break;\r |
| 2217 | \r |
| 2218 | case 0x23: /* INC HL */\r |
| 2219 | tStates += 6;\r |
| 2220 | sim_brk_pend[0] = FALSE;\r |
| 2221 | ++HL;\r |
| 2222 | break;\r |
| 2223 | \r |
| 2224 | case 0x24: /* INC H */\r |
| 2225 | tStates += 4;\r |
| 2226 | sim_brk_pend[0] = FALSE;\r |
| 2227 | HL += 0x100;\r |
| 2228 | temp = HIGH_REGISTER(HL);\r |
| 2229 | AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80); /* SET_PV2 uses temp */\r |
| 2230 | break;\r |
| 2231 | \r |
| 2232 | case 0x25: /* DEC H */\r |
| 2233 | tStates += 4;\r |
| 2234 | sim_brk_pend[0] = FALSE;\r |
| 2235 | HL -= 0x100;\r |
| 2236 | temp = HIGH_REGISTER(HL);\r |
| 2237 | AF = (AF & ~0xfe) | decTable[temp] | SET_PV2(0x7f); /* SET_PV2 uses temp */\r |
| 2238 | break;\r |
| 2239 | \r |
| 2240 | case 0x26: /* LD H,nn */\r |
| 2241 | tStates += 7;\r |
| 2242 | sim_brk_pend[0] = FALSE;\r |
| 2243 | SET_HIGH_REGISTER(HL, RAM_PP(PC));\r |
| 2244 | break;\r |
| 2245 | \r |
| 2246 | case 0x27: /* DAA */\r |
| 2247 | tStates += 4;\r |
| 2248 | sim_brk_pend[0] = FALSE;\r |
| 2249 | acu = HIGH_REGISTER(AF);\r |
| 2250 | temp = LOW_DIGIT(acu);\r |
| 2251 | cbits = TSTFLAG(C);\r |
| 2252 | if (TSTFLAG(N)) { /* last operation was a subtract */\r |
| 2253 | int hd = cbits || acu > 0x99;\r |
| 2254 | if (TSTFLAG(H) || (temp > 9)) { /* adjust low digit */\r |
| 2255 | if (temp > 5) {\r |
| 2256 | SETFLAG(H, 0);\r |
| 2257 | }\r |
| 2258 | acu -= 6;\r |
| 2259 | acu &= 0xff;\r |
| 2260 | }\r |
| 2261 | if (hd) acu -= 0x160; /* adjust high digit */\r |
| 2262 | }\r |
| 2263 | else { /* last operation was an add */\r |
| 2264 | if (TSTFLAG(H) || (temp > 9)) { /* adjust low digit */\r |
| 2265 | SETFLAG(H, (temp > 9));\r |
| 2266 | acu += 6;\r |
| 2267 | }\r |
| 2268 | if (cbits || ((acu & 0x1f0) > 0x90)) acu += 0x60; /* adjust high digit */\r |
| 2269 | }\r |
| 2270 | AF = (AF & 0x12) | rrdrldTable[acu & 0xff] | ((acu >> 8) & 1) | cbits;\r |
| 2271 | break;\r |
| 2272 | \r |
| 2273 | case 0x28: /* JR Z,dd */\r |
| 2274 | sim_brk_pend[0] = FALSE;\r |
| 2275 | CHECK_CPU_8080;\r |
| 2276 | if (TSTFLAG(Z)) {\r |
| 2277 | PCQ_ENTRY(PCX);\r |
| 2278 | PC += (int8) GetBYTE(PC) + 1;\r |
| 2279 | tStates += 12;\r |
| 2280 | }\r |
| 2281 | else {\r |
| 2282 | PC++;\r |
| 2283 | tStates += 7;\r |
| 2284 | }\r |
| 2285 | break;\r |
| 2286 | \r |
| 2287 | case 0x29: /* ADD HL,HL */\r |
| 2288 | tStates += 11;\r |
| 2289 | sim_brk_pend[0] = FALSE;\r |
| 2290 | HL &= ADDRMASK;\r |
| 2291 | sum = HL + HL;\r |
| 2292 | AF = (AF & ~0x3b) | cbitsDup16Table[sum >> 8];\r |
| 2293 | HL = sum;\r |
| 2294 | break;\r |
| 2295 | \r |
| 2296 | case 0x2a: /* LD HL,(nnnn) */\r |
| 2297 | tStates += 16;\r |
| 2298 | temp = GET_WORD(PC);\r |
| 2299 | CHECK_BREAK_WORD(temp);\r |
| 2300 | HL = GET_WORD(temp);\r |
| 2301 | PC += 2;\r |
| 2302 | break;\r |
| 2303 | \r |
| 2304 | case 0x2b: /* DEC HL */\r |
| 2305 | tStates += 6;\r |
| 2306 | sim_brk_pend[0] = FALSE;\r |
| 2307 | --HL;\r |
| 2308 | break;\r |
| 2309 | \r |
| 2310 | case 0x2c: /* INC L */\r |
| 2311 | tStates += 4;\r |
| 2312 | sim_brk_pend[0] = FALSE;\r |
| 2313 | temp = LOW_REGISTER(HL) + 1;\r |
| 2314 | SET_LOW_REGISTER(HL, temp);\r |
| 2315 | AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80);\r |
| 2316 | break;\r |
| 2317 | \r |
| 2318 | case 0x2d: /* DEC L */\r |
| 2319 | tStates += 4;\r |
| 2320 | sim_brk_pend[0] = FALSE;\r |
| 2321 | temp = LOW_REGISTER(HL) - 1;\r |
| 2322 | SET_LOW_REGISTER(HL, temp);\r |
| 2323 | AF = (AF & ~0xfe) | decTable[temp & 0xff] | SET_PV2(0x7f);\r |
| 2324 | break;\r |
| 2325 | \r |
| 2326 | case 0x2e: /* LD L,nn */\r |
| 2327 | tStates += 7;\r |
| 2328 | sim_brk_pend[0] = FALSE;\r |
| 2329 | SET_LOW_REGISTER(HL, RAM_PP(PC));\r |
| 2330 | break;\r |
| 2331 | \r |
| 2332 | case 0x2f: /* CPL */\r |
| 2333 | tStates += 4;\r |
| 2334 | sim_brk_pend[0] = FALSE;\r |
| 2335 | AF = (~AF & ~0xff) | (AF & 0xc5) | ((~AF >> 8) & 0x28) | 0x12;\r |
| 2336 | break;\r |
| 2337 | \r |
| 2338 | case 0x30: /* JR NC,dd */\r |
| 2339 | sim_brk_pend[0] = FALSE;\r |
| 2340 | CHECK_CPU_8080;\r |
| 2341 | if (TSTFLAG(C)) {\r |
| 2342 | PC++;\r |
| 2343 | tStates += 7;\r |
| 2344 | }\r |
| 2345 | else {\r |
| 2346 | PCQ_ENTRY(PCX);\r |
| 2347 | PC += (int8) GetBYTE(PC) + 1;\r |
| 2348 | tStates += 12;\r |
| 2349 | }\r |
| 2350 | break;\r |
| 2351 | \r |
| 2352 | case 0x31: /* LD SP,nnnn */\r |
| 2353 | tStates += 10;\r |
| 2354 | sim_brk_pend[0] = FALSE;\r |
| 2355 | SP = GET_WORD(PC);\r |
| 2356 | PC += 2;\r |
| 2357 | break;\r |
| 2358 | \r |
| 2359 | case 0x32: /* LD (nnnn),A */\r |
| 2360 | tStates += 13;\r |
| 2361 | temp = GET_WORD(PC);\r |
| 2362 | CHECK_BREAK_BYTE(temp);\r |
| 2363 | PutBYTE(temp, HIGH_REGISTER(AF));\r |
| 2364 | PC += 2;\r |
| 2365 | break;\r |
| 2366 | \r |
| 2367 | case 0x33: /* INC SP */\r |
| 2368 | tStates += 6;\r |
| 2369 | sim_brk_pend[0] = FALSE;\r |
| 2370 | ++SP;\r |
| 2371 | break;\r |
| 2372 | \r |
| 2373 | case 0x34: /* INC (HL) */\r |
| 2374 | tStates += 11;\r |
| 2375 | CHECK_BREAK_BYTE(HL);\r |
| 2376 | temp = GetBYTE(HL) + 1;\r |
| 2377 | PutBYTE(HL, temp);\r |
| 2378 | AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80);\r |
| 2379 | break;\r |
| 2380 | \r |
| 2381 | case 0x35: /* DEC (HL) */\r |
| 2382 | tStates += 11;\r |
| 2383 | CHECK_BREAK_BYTE(HL);\r |
| 2384 | temp = GetBYTE(HL) - 1;\r |
| 2385 | PutBYTE(HL, temp);\r |
| 2386 | AF = (AF & ~0xfe) | decTable[temp & 0xff] | SET_PV2(0x7f);\r |
| 2387 | break;\r |
| 2388 | \r |
| 2389 | case 0x36: /* LD (HL),nn */\r |
| 2390 | tStates += 10;\r |
| 2391 | CHECK_BREAK_BYTE(HL);\r |
| 2392 | PutBYTE(HL, RAM_PP(PC));\r |
| 2393 | break;\r |
| 2394 | \r |
| 2395 | case 0x37: /* SCF */\r |
| 2396 | tStates += 4;\r |
| 2397 | sim_brk_pend[0] = FALSE;\r |
| 2398 | AF = (AF & ~0x3b) | ((AF >> 8) & 0x28) | 1;\r |
| 2399 | break;\r |
| 2400 | \r |
| 2401 | case 0x38: /* JR C,dd */\r |
| 2402 | sim_brk_pend[0] = FALSE;\r |
| 2403 | CHECK_CPU_8080;\r |
| 2404 | if (TSTFLAG(C)) {\r |
| 2405 | PCQ_ENTRY(PCX);\r |
| 2406 | PC += (int8) GetBYTE(PC) + 1;\r |
| 2407 | tStates += 12;\r |
| 2408 | }\r |
| 2409 | else {\r |
| 2410 | PC++;\r |
| 2411 | tStates += 7;\r |
| 2412 | }\r |
| 2413 | break;\r |
| 2414 | \r |
| 2415 | case 0x39: /* ADD HL,SP */\r |
| 2416 | tStates += 11;\r |
| 2417 | sim_brk_pend[0] = FALSE;\r |
| 2418 | HL &= ADDRMASK;\r |
| 2419 | SP &= ADDRMASK;\r |
| 2420 | sum = HL + SP;\r |
| 2421 | AF = (AF & ~0x3b) | ((sum >> 8) & 0x28) | cbitsTable[(HL ^ SP ^ sum) >> 8];\r |
| 2422 | HL = sum;\r |
| 2423 | break;\r |
| 2424 | \r |
| 2425 | case 0x3a: /* LD A,(nnnn) */\r |
| 2426 | tStates += 13;\r |
| 2427 | temp = GET_WORD(PC);\r |
| 2428 | CHECK_BREAK_BYTE(temp);\r |
| 2429 | SET_HIGH_REGISTER(AF, GetBYTE(temp));\r |
| 2430 | PC += 2;\r |
| 2431 | break;\r |
| 2432 | \r |
| 2433 | case 0x3b: /* DEC SP */\r |
| 2434 | tStates += 6;\r |
| 2435 | sim_brk_pend[0] = FALSE;\r |
| 2436 | --SP;\r |
| 2437 | break;\r |
| 2438 | \r |
| 2439 | case 0x3c: /* INC A */\r |
| 2440 | tStates += 4;\r |
| 2441 | sim_brk_pend[0] = FALSE;\r |
| 2442 | AF += 0x100;\r |
| 2443 | temp = HIGH_REGISTER(AF);\r |
| 2444 | AF = (AF & ~0xfe) | incTable[temp] | SET_PV2(0x80); /* SET_PV2 uses temp */\r |
| 2445 | break;\r |
| 2446 | \r |
| 2447 | case 0x3d: /* DEC A */\r |
| 2448 | tStates += 4;\r |
| 2449 | sim_brk_pend[0] = FALSE;\r |
| 2450 | AF -= 0x100;\r |
| 2451 | temp = HIGH_REGISTER(AF);\r |
| 2452 | AF = (AF & ~0xfe) | decTable[temp] | SET_PV2(0x7f); /* SET_PV2 uses temp */\r |
| 2453 | break;\r |
| 2454 | \r |
| 2455 | case 0x3e: /* LD A,nn */\r |
| 2456 | tStates += 7;\r |
| 2457 | sim_brk_pend[0] = FALSE;\r |
| 2458 | SET_HIGH_REGISTER(AF, RAM_PP(PC));\r |
| 2459 | break;\r |
| 2460 | \r |
| 2461 | case 0x3f: /* CCF */\r |
| 2462 | tStates += 4;\r |
| 2463 | sim_brk_pend[0] = FALSE;\r |
| 2464 | AF = (AF & ~0x3b) | ((AF >> 8) & 0x28) | ((AF & 1) << 4) | (~AF & 1);\r |
| 2465 | break;\r |
| 2466 | \r |
| 2467 | case 0x40: /* LD B,B */\r |
| 2468 | tStates += 4;\r |
| 2469 | sim_brk_pend[0] = FALSE; /* nop */\r |
| 2470 | break;\r |
| 2471 | \r |
| 2472 | case 0x41: /* LD B,C */\r |
| 2473 | tStates += 4;\r |
| 2474 | sim_brk_pend[0] = FALSE;\r |
| 2475 | BC = (BC & 0xff) | ((BC & 0xff) << 8);\r |
| 2476 | break;\r |
| 2477 | \r |
| 2478 | case 0x42: /* LD B,D */\r |
| 2479 | tStates += 4;\r |
| 2480 | sim_brk_pend[0] = FALSE;\r |
| 2481 | BC = (BC & 0xff) | (DE & ~0xff);\r |
| 2482 | break;\r |
| 2483 | \r |
| 2484 | case 0x43: /* LD B,E */\r |
| 2485 | tStates += 4;\r |
| 2486 | sim_brk_pend[0] = FALSE;\r |
| 2487 | BC = (BC & 0xff) | ((DE & 0xff) << 8);\r |
| 2488 | break;\r |
| 2489 | \r |
| 2490 | case 0x44: /* LD B,H */\r |
| 2491 | tStates += 4;\r |
| 2492 | sim_brk_pend[0] = FALSE;\r |
| 2493 | BC = (BC & 0xff) | (HL & ~0xff);\r |
| 2494 | break;\r |
| 2495 | \r |
| 2496 | case 0x45: /* LD B,L */\r |
| 2497 | tStates += 4;\r |
| 2498 | sim_brk_pend[0] = FALSE;\r |
| 2499 | BC = (BC & 0xff) | ((HL & 0xff) << 8);\r |
| 2500 | break;\r |
| 2501 | \r |
| 2502 | case 0x46: /* LD B,(HL) */\r |
| 2503 | tStates += 7;\r |
| 2504 | CHECK_BREAK_BYTE(HL);\r |
| 2505 | SET_HIGH_REGISTER(BC, GetBYTE(HL));\r |
| 2506 | break;\r |
| 2507 | \r |
| 2508 | case 0x47: /* LD B,A */\r |
| 2509 | tStates += 4;\r |
| 2510 | sim_brk_pend[0] = FALSE;\r |
| 2511 | BC = (BC & 0xff) | (AF & ~0xff);\r |
| 2512 | break;\r |
| 2513 | \r |
| 2514 | case 0x48: /* LD C,B */\r |
| 2515 | tStates += 4;\r |
| 2516 | sim_brk_pend[0] = FALSE;\r |
| 2517 | BC = (BC & ~0xff) | ((BC >> 8) & 0xff);\r |
| 2518 | break;\r |
| 2519 | \r |
| 2520 | case 0x49: /* LD C,C */\r |
| 2521 | tStates += 4;\r |
| 2522 | sim_brk_pend[0] = FALSE; /* nop */\r |
| 2523 | break;\r |
| 2524 | \r |
| 2525 | case 0x4a: /* LD C,D */\r |
| 2526 | tStates += 4;\r |
| 2527 | sim_brk_pend[0] = FALSE;\r |
| 2528 | BC = (BC & ~0xff) | ((DE >> 8) & 0xff);\r |
| 2529 | break;\r |
| 2530 | \r |
| 2531 | case 0x4b: /* LD C,E */\r |
| 2532 | tStates += 4;\r |
| 2533 | sim_brk_pend[0] = FALSE;\r |
| 2534 | BC = (BC & ~0xff) | (DE & 0xff);\r |
| 2535 | break;\r |
| 2536 | \r |
| 2537 | case 0x4c: /* LD C,H */\r |
| 2538 | tStates += 4;\r |
| 2539 | sim_brk_pend[0] = FALSE;\r |
| 2540 | BC = (BC & ~0xff) | ((HL >> 8) & 0xff);\r |
| 2541 | break;\r |
| 2542 | \r |
| 2543 | case 0x4d: /* LD C,L */\r |
| 2544 | tStates += 4;\r |
| 2545 | sim_brk_pend[0] = FALSE;\r |
| 2546 | BC = (BC & ~0xff) | (HL & 0xff);\r |
| 2547 | break;\r |
| 2548 | \r |
| 2549 | case 0x4e: /* LD C,(HL) */\r |
| 2550 | tStates += 7;\r |
| 2551 | CHECK_BREAK_BYTE(HL);\r |
| 2552 | SET_LOW_REGISTER(BC, GetBYTE(HL));\r |
| 2553 | break;\r |
| 2554 | \r |
| 2555 | case 0x4f: /* LD C,A */\r |
| 2556 | tStates += 4;\r |
| 2557 | sim_brk_pend[0] = FALSE;\r |
| 2558 | BC = (BC & ~0xff) | ((AF >> 8) & 0xff);\r |
| 2559 | break;\r |
| 2560 | \r |
| 2561 | case 0x50: /* LD D,B */\r |
| 2562 | tStates += 4;\r |
| 2563 | sim_brk_pend[0] = FALSE;\r |
| 2564 | DE = (DE & 0xff) | (BC & ~0xff);\r |
| 2565 | break;\r |
| 2566 | \r |
| 2567 | case 0x51: /* LD D,C */\r |
| 2568 | tStates += 4;\r |
| 2569 | sim_brk_pend[0] = FALSE;\r |
| 2570 | DE = (DE & 0xff) | ((BC & 0xff) << 8);\r |
| 2571 | break;\r |
| 2572 | \r |
| 2573 | case 0x52: /* LD D,D */\r |
| 2574 | tStates += 4;\r |
| 2575 | sim_brk_pend[0] = FALSE; /* nop */\r |
| 2576 | break;\r |
| 2577 | \r |
| 2578 | case 0x53: /* LD D,E */\r |
| 2579 | tStates += 4;\r |
| 2580 | sim_brk_pend[0] = FALSE;\r |
| 2581 | DE = (DE & 0xff) | ((DE & 0xff) << 8);\r |
| 2582 | break;\r |
| 2583 | \r |
| 2584 | case 0x54: /* LD D,H */\r |
| 2585 | tStates += 4;\r |
| 2586 | sim_brk_pend[0] = FALSE;\r |
| 2587 | DE = (DE & 0xff) | (HL & ~0xff);\r |
| 2588 | break;\r |
| 2589 | \r |
| 2590 | case 0x55: /* LD D,L */\r |
| 2591 | tStates += 4;\r |
| 2592 | sim_brk_pend[0] = FALSE;\r |
| 2593 | DE = (DE & 0xff) | ((HL & 0xff) << 8);\r |
| 2594 | break;\r |
| 2595 | \r |
| 2596 | case 0x56: /* LD D,(HL) */\r |
| 2597 | tStates += 7;\r |
| 2598 | CHECK_BREAK_BYTE(HL);\r |
| 2599 | SET_HIGH_REGISTER(DE, GetBYTE(HL));\r |
| 2600 | break;\r |
| 2601 | \r |
| 2602 | case 0x57: /* LD D,A */\r |
| 2603 | tStates += 4;\r |
| 2604 | sim_brk_pend[0] = FALSE;\r |
| 2605 | DE = (DE & 0xff) | (AF & ~0xff);\r |
| 2606 | break;\r |
| 2607 | \r |
| 2608 | case 0x58: /* LD E,B */\r |
| 2609 | tStates += 4;\r |
| 2610 | sim_brk_pend[0] = FALSE;\r |
| 2611 | DE = (DE & ~0xff) | ((BC >> 8) & 0xff);\r |
| 2612 | break;\r |
| 2613 | \r |
| 2614 | case 0x59: /* LD E,C */\r |
| 2615 | tStates += 4;\r |
| 2616 | sim_brk_pend[0] = FALSE;\r |
| 2617 | DE = (DE & ~0xff) | (BC & 0xff);\r |
| 2618 | break;\r |
| 2619 | \r |
| 2620 | case 0x5a: /* LD E,D */\r |
| 2621 | tStates += 4;\r |
| 2622 | sim_brk_pend[0] = FALSE;\r |
| 2623 | DE = (DE & ~0xff) | ((DE >> 8) & 0xff);\r |
| 2624 | break;\r |
| 2625 | \r |
| 2626 | case 0x5b: /* LD E,E */\r |
| 2627 | tStates += 4;\r |
| 2628 | sim_brk_pend[0] = FALSE; /* nop */\r |
| 2629 | break;\r |
| 2630 | \r |
| 2631 | case 0x5c: /* LD E,H */\r |
| 2632 | tStates += 4;\r |
| 2633 | sim_brk_pend[0] = FALSE;\r |
| 2634 | DE = (DE & ~0xff) | ((HL >> 8) & 0xff);\r |
| 2635 | break;\r |
| 2636 | \r |
| 2637 | case 0x5d: /* LD E,L */\r |
| 2638 | tStates += 4;\r |
| 2639 | sim_brk_pend[0] = FALSE;\r |
| 2640 | DE = (DE & ~0xff) | (HL & 0xff);\r |
| 2641 | break;\r |
| 2642 | \r |
| 2643 | case 0x5e: /* LD E,(HL) */\r |
| 2644 | tStates += 7;\r |
| 2645 | CHECK_BREAK_BYTE(HL);\r |
| 2646 | SET_LOW_REGISTER(DE, GetBYTE(HL));\r |
| 2647 | break;\r |
| 2648 | \r |
| 2649 | case 0x5f: /* LD E,A */\r |
| 2650 | tStates += 4;\r |
| 2651 | sim_brk_pend[0] = FALSE;\r |
| 2652 | DE = (DE & ~0xff) | ((AF >> 8) & 0xff);\r |
| 2653 | break;\r |
| 2654 | \r |
| 2655 | case 0x60: /* LD H,B */\r |
| 2656 | tStates += 4;\r |
| 2657 | sim_brk_pend[0] = FALSE;\r |
| 2658 | HL = (HL & 0xff) | (BC & ~0xff);\r |
| 2659 | break;\r |
| 2660 | \r |
| 2661 | case 0x61: /* LD H,C */\r |
| 2662 | tStates += 4;\r |
| 2663 | sim_brk_pend[0] = FALSE;\r |
| 2664 | HL = (HL & 0xff) | ((BC & 0xff) << 8);\r |
| 2665 | break;\r |
| 2666 | \r |
| 2667 | case 0x62: /* LD H,D */\r |
| 2668 | tStates += 4;\r |
| 2669 | sim_brk_pend[0] = FALSE;\r |
| 2670 | HL = (HL & 0xff) | (DE & ~0xff);\r |
| 2671 | break;\r |
| 2672 | \r |
| 2673 | case 0x63: /* LD H,E */\r |
| 2674 | tStates += 4;\r |
| 2675 | sim_brk_pend[0] = FALSE;\r |
| 2676 | HL = (HL & 0xff) | ((DE & 0xff) << 8);\r |
| 2677 | break;\r |
| 2678 | \r |
| 2679 | case 0x64: /* LD H,H */\r |
| 2680 | tStates += 4;\r |
| 2681 | sim_brk_pend[0] = FALSE; /* nop */\r |
| 2682 | break;\r |
| 2683 | \r |
| 2684 | case 0x65: /* LD H,L */\r |
| 2685 | tStates += 4;\r |
| 2686 | sim_brk_pend[0] = FALSE;\r |
| 2687 | HL = (HL & 0xff) | ((HL & 0xff) << 8);\r |
| 2688 | break;\r |
| 2689 | \r |
| 2690 | case 0x66: /* LD H,(HL) */\r |
| 2691 | tStates += 7;\r |
| 2692 | CHECK_BREAK_BYTE(HL);\r |
| 2693 | SET_HIGH_REGISTER(HL, GetBYTE(HL));\r |
| 2694 | break;\r |
| 2695 | \r |
| 2696 | case 0x67: /* LD H,A */\r |
| 2697 | tStates += 4;\r |
| 2698 | sim_brk_pend[0] = FALSE;\r |
| 2699 | HL = (HL & 0xff) | (AF & ~0xff);\r |
| 2700 | break;\r |
| 2701 | \r |
| 2702 | case 0x68: /* LD L,B */\r |
| 2703 | tStates += 4;\r |
| 2704 | sim_brk_pend[0] = FALSE;\r |
| 2705 | HL = (HL & ~0xff) | ((BC >> 8) & 0xff);\r |
| 2706 | break;\r |
| 2707 | \r |
| 2708 | case 0x69: /* LD L,C */\r |
| 2709 | tStates += 4;\r |
| 2710 | sim_brk_pend[0] = FALSE;\r |
| 2711 | HL = (HL & ~0xff) | (BC & 0xff);\r |
| 2712 | break;\r |
| 2713 | \r |
| 2714 | case 0x6a: /* LD L,D */\r |
| 2715 | tStates += 4;\r |
| 2716 | sim_brk_pend[0] = FALSE;\r |
| 2717 | HL = (HL & ~0xff) | ((DE >> 8) & 0xff);\r |
| 2718 | break;\r |
| 2719 | \r |
| 2720 | case 0x6b: /* LD L,E */\r |
| 2721 | tStates += 4;\r |
| 2722 | sim_brk_pend[0] = FALSE;\r |
| 2723 | HL = (HL & ~0xff) | (DE & 0xff);\r |
| 2724 | break;\r |
| 2725 | \r |
| 2726 | case 0x6c: /* LD L,H */\r |
| 2727 | tStates += 4;\r |
| 2728 | sim_brk_pend[0] = FALSE;\r |
| 2729 | HL = (HL & ~0xff) | ((HL >> 8) & 0xff);\r |
| 2730 | break;\r |
| 2731 | \r |
| 2732 | case 0x6d: /* LD L,L */\r |
| 2733 | tStates += 4;\r |
| 2734 | sim_brk_pend[0] = FALSE; /* nop */\r |
| 2735 | break;\r |
| 2736 | \r |
| 2737 | case 0x6e: /* LD L,(HL) */\r |
| 2738 | tStates += 7;\r |
| 2739 | CHECK_BREAK_BYTE(HL);\r |
| 2740 | SET_LOW_REGISTER(HL, GetBYTE(HL));\r |
| 2741 | break;\r |
| 2742 | \r |
| 2743 | case 0x6f: /* LD L,A */\r |
| 2744 | tStates += 4;\r |
| 2745 | sim_brk_pend[0] = FALSE;\r |
| 2746 | HL = (HL & ~0xff) | ((AF >> 8) & 0xff);\r |
| 2747 | break;\r |
| 2748 | \r |
| 2749 | case 0x70: /* LD (HL),B */\r |
| 2750 | tStates += 7;\r |
| 2751 | CHECK_BREAK_BYTE(HL);\r |
| 2752 | PutBYTE(HL, HIGH_REGISTER(BC));\r |
| 2753 | break;\r |
| 2754 | \r |
| 2755 | case 0x71: /* LD (HL),C */\r |
| 2756 | tStates += 7;\r |
| 2757 | CHECK_BREAK_BYTE(HL);\r |
| 2758 | PutBYTE(HL, LOW_REGISTER(BC));\r |
| 2759 | break;\r |
| 2760 | \r |
| 2761 | case 0x72: /* LD (HL),D */\r |
| 2762 | tStates += 7;\r |
| 2763 | CHECK_BREAK_BYTE(HL);\r |
| 2764 | PutBYTE(HL, HIGH_REGISTER(DE));\r |
| 2765 | break;\r |
| 2766 | \r |
| 2767 | case 0x73: /* LD (HL),E */\r |
| 2768 | tStates += 7;\r |
| 2769 | CHECK_BREAK_BYTE(HL);\r |
| 2770 | PutBYTE(HL, LOW_REGISTER(DE));\r |
| 2771 | break;\r |
| 2772 | \r |
| 2773 | case 0x74: /* LD (HL),H */\r |
| 2774 | tStates += 7;\r |
| 2775 | CHECK_BREAK_BYTE(HL);\r |
| 2776 | PutBYTE(HL, HIGH_REGISTER(HL));\r |
| 2777 | break;\r |
| 2778 | \r |
| 2779 | case 0x75: /* LD (HL),L */\r |
| 2780 | tStates += 7;\r |
| 2781 | CHECK_BREAK_BYTE(HL);\r |
| 2782 | PutBYTE(HL, LOW_REGISTER(HL));\r |
| 2783 | break;\r |
| 2784 | \r |
| 2785 | case HALTINSTRUCTION: /* HALT */\r |
| 2786 | tStates += 4;\r |
| 2787 | sim_brk_pend[0] = FALSE;\r |
| 2788 | PC--;\r |
| 2789 | if (cpu_unit.flags & UNIT_CPU_STOPONHALT) {\r |
| 2790 | reason = STOP_HALT;\r |
| 2791 | goto end_decode;\r |
| 2792 | }\r |
| 2793 | sim_interval = 0;\r |
| 2794 | do_SIMH_sleep(); /* reduce CPU load in busy wait */\r |
| 2795 | break;\r |
| 2796 | \r |
| 2797 | case 0x77: /* LD (HL),A */\r |
| 2798 | tStates += 7;\r |
| 2799 | CHECK_BREAK_BYTE(HL);\r |
| 2800 | PutBYTE(HL, HIGH_REGISTER(AF));\r |
| 2801 | break;\r |
| 2802 | \r |
| 2803 | case 0x78: /* LD A,B */\r |
| 2804 | tStates += 4;\r |
| 2805 | sim_brk_pend[0] = FALSE;\r |
| 2806 | AF = (AF & 0xff) | (BC & ~0xff);\r |
| 2807 | break;\r |
| 2808 | \r |
| 2809 | case 0x79: /* LD A,C */\r |
| 2810 | tStates += 4;\r |
| 2811 | sim_brk_pend[0] = FALSE;\r |
| 2812 | AF = (AF & 0xff) | ((BC & 0xff) << 8);\r |
| 2813 | break;\r |
| 2814 | \r |
| 2815 | case 0x7a: /* LD A,D */\r |
| 2816 | tStates += 4;\r |
| 2817 | sim_brk_pend[0] = FALSE;\r |
| 2818 | AF = (AF & 0xff) | (DE & ~0xff);\r |
| 2819 | break;\r |
| 2820 | \r |
| 2821 | case 0x7b: /* LD A,E */\r |
| 2822 | tStates += 4;\r |
| 2823 | sim_brk_pend[0] = FALSE;\r |
| 2824 | AF = (AF & 0xff) | ((DE & 0xff) << 8);\r |
| 2825 | break;\r |
| 2826 | \r |
| 2827 | case 0x7c: /* LD A,H */\r |
| 2828 | tStates += 4;\r |
| 2829 | sim_brk_pend[0] = FALSE;\r |
| 2830 | AF = (AF & 0xff) | (HL & ~0xff);\r |
| 2831 | break;\r |
| 2832 | \r |
| 2833 | case 0x7d: /* LD A,L */\r |
| 2834 | tStates += 4;\r |
| 2835 | sim_brk_pend[0] = FALSE;\r |
| 2836 | AF = (AF & 0xff) | ((HL & 0xff) << 8);\r |
| 2837 | break;\r |
| 2838 | \r |
| 2839 | case 0x7e: /* LD A,(HL) */\r |
| 2840 | tStates += 7;\r |
| 2841 | CHECK_BREAK_BYTE(HL);\r |
| 2842 | SET_HIGH_REGISTER(AF, GetBYTE(HL));\r |
| 2843 | break;\r |
| 2844 | \r |
| 2845 | case 0x7f: /* LD A,A */\r |
| 2846 | tStates += 4;\r |
| 2847 | sim_brk_pend[0] = FALSE; /* nop */\r |
| 2848 | break;\r |
| 2849 | \r |
| 2850 | case 0x80: /* ADD A,B */\r |
| 2851 | tStates += 4;\r |
| 2852 | sim_brk_pend[0] = FALSE;\r |
| 2853 | temp = HIGH_REGISTER(BC);\r |
| 2854 | acu = HIGH_REGISTER(AF);\r |
| 2855 | sum = acu + temp;\r |
| 2856 | cbits = acu ^ temp ^ sum;\r |
| 2857 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2858 | break;\r |
| 2859 | \r |
| 2860 | case 0x81: /* ADD A,C */\r |
| 2861 | tStates += 4;\r |
| 2862 | sim_brk_pend[0] = FALSE;\r |
| 2863 | temp = LOW_REGISTER(BC);\r |
| 2864 | acu = HIGH_REGISTER(AF);\r |
| 2865 | sum = acu + temp;\r |
| 2866 | cbits = acu ^ temp ^ sum;\r |
| 2867 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2868 | break;\r |
| 2869 | \r |
| 2870 | case 0x82: /* ADD A,D */\r |
| 2871 | tStates += 4;\r |
| 2872 | sim_brk_pend[0] = FALSE;\r |
| 2873 | temp = HIGH_REGISTER(DE);\r |
| 2874 | acu = HIGH_REGISTER(AF);\r |
| 2875 | sum = acu + temp;\r |
| 2876 | cbits = acu ^ temp ^ sum;\r |
| 2877 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2878 | break;\r |
| 2879 | \r |
| 2880 | case 0x83: /* ADD A,E */\r |
| 2881 | tStates += 4;\r |
| 2882 | sim_brk_pend[0] = FALSE;\r |
| 2883 | temp = LOW_REGISTER(DE);\r |
| 2884 | acu = HIGH_REGISTER(AF);\r |
| 2885 | sum = acu + temp;\r |
| 2886 | cbits = acu ^ temp ^ sum;\r |
| 2887 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2888 | break;\r |
| 2889 | \r |
| 2890 | case 0x84: /* ADD A,H */\r |
| 2891 | tStates += 4;\r |
| 2892 | sim_brk_pend[0] = FALSE;\r |
| 2893 | temp = HIGH_REGISTER(HL);\r |
| 2894 | acu = HIGH_REGISTER(AF);\r |
| 2895 | sum = acu + temp;\r |
| 2896 | cbits = acu ^ temp ^ sum;\r |
| 2897 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2898 | break;\r |
| 2899 | \r |
| 2900 | case 0x85: /* ADD A,L */\r |
| 2901 | tStates += 4;\r |
| 2902 | sim_brk_pend[0] = FALSE;\r |
| 2903 | temp = LOW_REGISTER(HL);\r |
| 2904 | acu = HIGH_REGISTER(AF);\r |
| 2905 | sum = acu + temp;\r |
| 2906 | cbits = acu ^ temp ^ sum;\r |
| 2907 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2908 | break;\r |
| 2909 | \r |
| 2910 | case 0x86: /* ADD A,(HL) */\r |
| 2911 | tStates += 7;\r |
| 2912 | CHECK_BREAK_BYTE(HL);\r |
| 2913 | temp = GetBYTE(HL);\r |
| 2914 | acu = HIGH_REGISTER(AF);\r |
| 2915 | sum = acu + temp;\r |
| 2916 | cbits = acu ^ temp ^ sum;\r |
| 2917 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2918 | break;\r |
| 2919 | \r |
| 2920 | case 0x87: /* ADD A,A */\r |
| 2921 | tStates += 4;\r |
| 2922 | sim_brk_pend[0] = FALSE;\r |
| 2923 | cbits = 2 * HIGH_REGISTER(AF);\r |
| 2924 | AF = cbitsDup8Table[cbits] | (SET_PVS(cbits));\r |
| 2925 | break;\r |
| 2926 | \r |
| 2927 | case 0x88: /* ADC A,B */\r |
| 2928 | tStates += 4;\r |
| 2929 | sim_brk_pend[0] = FALSE;\r |
| 2930 | temp = HIGH_REGISTER(BC);\r |
| 2931 | acu = HIGH_REGISTER(AF);\r |
| 2932 | sum = acu + temp + TSTFLAG(C);\r |
| 2933 | cbits = acu ^ temp ^ sum;\r |
| 2934 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2935 | break;\r |
| 2936 | \r |
| 2937 | case 0x89: /* ADC A,C */\r |
| 2938 | tStates += 4;\r |
| 2939 | sim_brk_pend[0] = FALSE;\r |
| 2940 | temp = LOW_REGISTER(BC);\r |
| 2941 | acu = HIGH_REGISTER(AF);\r |
| 2942 | sum = acu + temp + TSTFLAG(C);\r |
| 2943 | cbits = acu ^ temp ^ sum;\r |
| 2944 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2945 | break;\r |
| 2946 | \r |
| 2947 | case 0x8a: /* ADC A,D */\r |
| 2948 | tStates += 4;\r |
| 2949 | sim_brk_pend[0] = FALSE;\r |
| 2950 | temp = HIGH_REGISTER(DE);\r |
| 2951 | acu = HIGH_REGISTER(AF);\r |
| 2952 | sum = acu + temp + TSTFLAG(C);\r |
| 2953 | cbits = acu ^ temp ^ sum;\r |
| 2954 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2955 | break;\r |
| 2956 | \r |
| 2957 | case 0x8b: /* ADC A,E */\r |
| 2958 | tStates += 4;\r |
| 2959 | sim_brk_pend[0] = FALSE;\r |
| 2960 | temp = LOW_REGISTER(DE);\r |
| 2961 | acu = HIGH_REGISTER(AF);\r |
| 2962 | sum = acu + temp + TSTFLAG(C);\r |
| 2963 | cbits = acu ^ temp ^ sum;\r |
| 2964 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2965 | break;\r |
| 2966 | \r |
| 2967 | case 0x8c: /* ADC A,H */\r |
| 2968 | tStates += 4;\r |
| 2969 | sim_brk_pend[0] = FALSE;\r |
| 2970 | temp = HIGH_REGISTER(HL);\r |
| 2971 | acu = HIGH_REGISTER(AF);\r |
| 2972 | sum = acu + temp + TSTFLAG(C);\r |
| 2973 | cbits = acu ^ temp ^ sum;\r |
| 2974 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2975 | break;\r |
| 2976 | \r |
| 2977 | case 0x8d: /* ADC A,L */\r |
| 2978 | tStates += 4;\r |
| 2979 | sim_brk_pend[0] = FALSE;\r |
| 2980 | temp = LOW_REGISTER(HL);\r |
| 2981 | acu = HIGH_REGISTER(AF);\r |
| 2982 | sum = acu + temp + TSTFLAG(C);\r |
| 2983 | cbits = acu ^ temp ^ sum;\r |
| 2984 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2985 | break;\r |
| 2986 | \r |
| 2987 | case 0x8e: /* ADC A,(HL) */\r |
| 2988 | tStates += 7;\r |
| 2989 | CHECK_BREAK_BYTE(HL);\r |
| 2990 | temp = GetBYTE(HL);\r |
| 2991 | acu = HIGH_REGISTER(AF);\r |
| 2992 | sum = acu + temp + TSTFLAG(C);\r |
| 2993 | cbits = acu ^ temp ^ sum;\r |
| 2994 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 2995 | break;\r |
| 2996 | \r |
| 2997 | case 0x8f: /* ADC A,A */\r |
| 2998 | tStates += 4;\r |
| 2999 | sim_brk_pend[0] = FALSE;\r |
| 3000 | cbits = 2 * HIGH_REGISTER(AF) + TSTFLAG(C);\r |
| 3001 | AF = cbitsDup8Table[cbits] | (SET_PVS(cbits));\r |
| 3002 | break;\r |
| 3003 | \r |
| 3004 | case 0x90: /* SUB B */\r |
| 3005 | tStates += 4;\r |
| 3006 | sim_brk_pend[0] = FALSE;\r |
| 3007 | temp = HIGH_REGISTER(BC);\r |
| 3008 | acu = HIGH_REGISTER(AF);\r |
| 3009 | sum = acu - temp;\r |
| 3010 | cbits = acu ^ temp ^ sum;\r |
| 3011 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3012 | break;\r |
| 3013 | \r |
| 3014 | case 0x91: /* SUB C */\r |
| 3015 | tStates += 4;\r |
| 3016 | sim_brk_pend[0] = FALSE;\r |
| 3017 | temp = LOW_REGISTER(BC);\r |
| 3018 | acu = HIGH_REGISTER(AF);\r |
| 3019 | sum = acu - temp;\r |
| 3020 | cbits = acu ^ temp ^ sum;\r |
| 3021 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3022 | break;\r |
| 3023 | \r |
| 3024 | case 0x92: /* SUB D */\r |
| 3025 | tStates += 4;\r |
| 3026 | sim_brk_pend[0] = FALSE;\r |
| 3027 | temp = HIGH_REGISTER(DE);\r |
| 3028 | acu = HIGH_REGISTER(AF);\r |
| 3029 | sum = acu - temp;\r |
| 3030 | cbits = acu ^ temp ^ sum;\r |
| 3031 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3032 | break;\r |
| 3033 | \r |
| 3034 | case 0x93: /* SUB E */\r |
| 3035 | tStates += 4;\r |
| 3036 | sim_brk_pend[0] = FALSE;\r |
| 3037 | temp = LOW_REGISTER(DE);\r |
| 3038 | acu = HIGH_REGISTER(AF);\r |
| 3039 | sum = acu - temp;\r |
| 3040 | cbits = acu ^ temp ^ sum;\r |
| 3041 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3042 | break;\r |
| 3043 | \r |
| 3044 | case 0x94: /* SUB H */\r |
| 3045 | tStates += 4;\r |
| 3046 | sim_brk_pend[0] = FALSE;\r |
| 3047 | temp = HIGH_REGISTER(HL);\r |
| 3048 | acu = HIGH_REGISTER(AF);\r |
| 3049 | sum = acu - temp;\r |
| 3050 | cbits = acu ^ temp ^ sum;\r |
| 3051 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3052 | break;\r |
| 3053 | \r |
| 3054 | case 0x95: /* SUB L */\r |
| 3055 | tStates += 4;\r |
| 3056 | sim_brk_pend[0] = FALSE;\r |
| 3057 | temp = LOW_REGISTER(HL);\r |
| 3058 | acu = HIGH_REGISTER(AF);\r |
| 3059 | sum = acu - temp;\r |
| 3060 | cbits = acu ^ temp ^ sum;\r |
| 3061 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3062 | break;\r |
| 3063 | \r |
| 3064 | case 0x96: /* SUB (HL) */\r |
| 3065 | tStates += 7;\r |
| 3066 | CHECK_BREAK_BYTE(HL);\r |
| 3067 | temp = GetBYTE(HL);\r |
| 3068 | acu = HIGH_REGISTER(AF);\r |
| 3069 | sum = acu - temp;\r |
| 3070 | cbits = acu ^ temp ^ sum;\r |
| 3071 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3072 | break;\r |
| 3073 | \r |
| 3074 | case 0x97: /* SUB A */\r |
| 3075 | tStates += 4;\r |
| 3076 | sim_brk_pend[0] = FALSE;\r |
| 3077 | AF = (chiptype == CHIP_TYPE_Z80) ? 0x42 : 0x46;\r |
| 3078 | break;\r |
| 3079 | \r |
| 3080 | case 0x98: /* SBC A,B */\r |
| 3081 | tStates += 4;\r |
| 3082 | sim_brk_pend[0] = FALSE;\r |
| 3083 | temp = HIGH_REGISTER(BC);\r |
| 3084 | acu = HIGH_REGISTER(AF);\r |
| 3085 | sum = acu - temp - TSTFLAG(C);\r |
| 3086 | cbits = acu ^ temp ^ sum;\r |
| 3087 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3088 | break;\r |
| 3089 | \r |
| 3090 | case 0x99: /* SBC A,C */\r |
| 3091 | tStates += 4;\r |
| 3092 | sim_brk_pend[0] = FALSE;\r |
| 3093 | temp = LOW_REGISTER(BC);\r |
| 3094 | acu = HIGH_REGISTER(AF);\r |
| 3095 | sum = acu - temp - TSTFLAG(C);\r |
| 3096 | cbits = acu ^ temp ^ sum;\r |
| 3097 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3098 | break;\r |
| 3099 | \r |
| 3100 | case 0x9a: /* SBC A,D */\r |
| 3101 | tStates += 4;\r |
| 3102 | sim_brk_pend[0] = FALSE;\r |
| 3103 | temp = HIGH_REGISTER(DE);\r |
| 3104 | acu = HIGH_REGISTER(AF);\r |
| 3105 | sum = acu - temp - TSTFLAG(C);\r |
| 3106 | cbits = acu ^ temp ^ sum;\r |
| 3107 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3108 | break;\r |
| 3109 | \r |
| 3110 | case 0x9b: /* SBC A,E */\r |
| 3111 | tStates += 4;\r |
| 3112 | sim_brk_pend[0] = FALSE;\r |
| 3113 | temp = LOW_REGISTER(DE);\r |
| 3114 | acu = HIGH_REGISTER(AF);\r |
| 3115 | sum = acu - temp - TSTFLAG(C);\r |
| 3116 | cbits = acu ^ temp ^ sum;\r |
| 3117 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3118 | break;\r |
| 3119 | \r |
| 3120 | case 0x9c: /* SBC A,H */\r |
| 3121 | tStates += 4;\r |
| 3122 | sim_brk_pend[0] = FALSE;\r |
| 3123 | temp = HIGH_REGISTER(HL);\r |
| 3124 | acu = HIGH_REGISTER(AF);\r |
| 3125 | sum = acu - temp - TSTFLAG(C);\r |
| 3126 | cbits = acu ^ temp ^ sum;\r |
| 3127 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3128 | break;\r |
| 3129 | \r |
| 3130 | case 0x9d: /* SBC A,L */\r |
| 3131 | tStates += 4;\r |
| 3132 | sim_brk_pend[0] = FALSE;\r |
| 3133 | temp = LOW_REGISTER(HL);\r |
| 3134 | acu = HIGH_REGISTER(AF);\r |
| 3135 | sum = acu - temp - TSTFLAG(C);\r |
| 3136 | cbits = acu ^ temp ^ sum;\r |
| 3137 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3138 | break;\r |
| 3139 | \r |
| 3140 | case 0x9e: /* SBC A,(HL) */\r |
| 3141 | tStates += 7;\r |
| 3142 | CHECK_BREAK_BYTE(HL);\r |
| 3143 | temp = GetBYTE(HL);\r |
| 3144 | acu = HIGH_REGISTER(AF);\r |
| 3145 | sum = acu - temp - TSTFLAG(C);\r |
| 3146 | cbits = acu ^ temp ^ sum;\r |
| 3147 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3148 | break;\r |
| 3149 | \r |
| 3150 | case 0x9f: /* SBC A,A */\r |
| 3151 | tStates += 4;\r |
| 3152 | sim_brk_pend[0] = FALSE;\r |
| 3153 | cbits = -TSTFLAG(C);\r |
| 3154 | AF = subTable[cbits & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PVS(cbits));\r |
| 3155 | break;\r |
| 3156 | \r |
| 3157 | case 0xa0: /* AND B */\r |
| 3158 | tStates += 4;\r |
| 3159 | sim_brk_pend[0] = FALSE;\r |
| 3160 | AF = andTable[((AF & BC) >> 8) & 0xff];\r |
| 3161 | break;\r |
| 3162 | \r |
| 3163 | case 0xa1: /* AND C */\r |
| 3164 | tStates += 4;\r |
| 3165 | sim_brk_pend[0] = FALSE;\r |
| 3166 | AF = andTable[((AF >> 8) & BC) & 0xff];\r |
| 3167 | break;\r |
| 3168 | \r |
| 3169 | case 0xa2: /* AND D */\r |
| 3170 | tStates += 4;\r |
| 3171 | sim_brk_pend[0] = FALSE;\r |
| 3172 | AF = andTable[((AF & DE) >> 8) & 0xff];\r |
| 3173 | break;\r |
| 3174 | \r |
| 3175 | case 0xa3: /* AND E */\r |
| 3176 | tStates += 4;\r |
| 3177 | sim_brk_pend[0] = FALSE;\r |
| 3178 | AF = andTable[((AF >> 8) & DE) & 0xff];\r |
| 3179 | break;\r |
| 3180 | \r |
| 3181 | case 0xa4: /* AND H */\r |
| 3182 | tStates += 4;\r |
| 3183 | sim_brk_pend[0] = FALSE;\r |
| 3184 | AF = andTable[((AF & HL) >> 8) & 0xff];\r |
| 3185 | break;\r |
| 3186 | \r |
| 3187 | case 0xa5: /* AND L */\r |
| 3188 | tStates += 4;\r |
| 3189 | sim_brk_pend[0] = FALSE;\r |
| 3190 | AF = andTable[((AF >> 8) & HL) & 0xff];\r |
| 3191 | break;\r |
| 3192 | \r |
| 3193 | case 0xa6: /* AND (HL) */\r |
| 3194 | tStates += 7;\r |
| 3195 | CHECK_BREAK_BYTE(HL);\r |
| 3196 | AF = andTable[((AF >> 8) & GetBYTE(HL)) & 0xff];\r |
| 3197 | break;\r |
| 3198 | \r |
| 3199 | case 0xa7: /* AND A */\r |
| 3200 | tStates += 4;\r |
| 3201 | sim_brk_pend[0] = FALSE;\r |
| 3202 | AF = andTable[(AF >> 8) & 0xff];\r |
| 3203 | break;\r |
| 3204 | \r |
| 3205 | case 0xa8: /* XOR B */\r |
| 3206 | tStates += 4;\r |
| 3207 | sim_brk_pend[0] = FALSE;\r |
| 3208 | AF = xororTable[((AF ^ BC) >> 8) & 0xff];\r |
| 3209 | break;\r |
| 3210 | \r |
| 3211 | case 0xa9: /* XOR C */\r |
| 3212 | tStates += 4;\r |
| 3213 | sim_brk_pend[0] = FALSE;\r |
| 3214 | AF = xororTable[((AF >> 8) ^ BC) & 0xff];\r |
| 3215 | break;\r |
| 3216 | \r |
| 3217 | case 0xaa: /* XOR D */\r |
| 3218 | tStates += 4;\r |
| 3219 | sim_brk_pend[0] = FALSE;\r |
| 3220 | AF = xororTable[((AF ^ DE) >> 8) & 0xff];\r |
| 3221 | break;\r |
| 3222 | \r |
| 3223 | case 0xab: /* XOR E */\r |
| 3224 | tStates += 4;\r |
| 3225 | sim_brk_pend[0] = FALSE;\r |
| 3226 | AF = xororTable[((AF >> 8) ^ DE) & 0xff];\r |
| 3227 | break;\r |
| 3228 | \r |
| 3229 | case 0xac: /* XOR H */\r |
| 3230 | tStates += 4;\r |
| 3231 | sim_brk_pend[0] = FALSE;\r |
| 3232 | AF = xororTable[((AF ^ HL) >> 8) & 0xff];\r |
| 3233 | break;\r |
| 3234 | \r |
| 3235 | case 0xad: /* XOR L */\r |
| 3236 | tStates += 4;\r |
| 3237 | sim_brk_pend[0] = FALSE;\r |
| 3238 | AF = xororTable[((AF >> 8) ^ HL) & 0xff];\r |
| 3239 | break;\r |
| 3240 | \r |
| 3241 | case 0xae: /* XOR (HL) */\r |
| 3242 | tStates += 7;\r |
| 3243 | CHECK_BREAK_BYTE(HL);\r |
| 3244 | AF = xororTable[((AF >> 8) ^ GetBYTE(HL)) & 0xff];\r |
| 3245 | break;\r |
| 3246 | \r |
| 3247 | case 0xaf: /* XOR A */\r |
| 3248 | tStates += 4;\r |
| 3249 | sim_brk_pend[0] = FALSE;\r |
| 3250 | AF = 0x44;\r |
| 3251 | break;\r |
| 3252 | \r |
| 3253 | case 0xb0: /* OR B */\r |
| 3254 | tStates += 4;\r |
| 3255 | sim_brk_pend[0] = FALSE;\r |
| 3256 | AF = xororTable[((AF | BC) >> 8) & 0xff];\r |
| 3257 | break;\r |
| 3258 | \r |
| 3259 | case 0xb1: /* OR C */\r |
| 3260 | tStates += 4;\r |
| 3261 | sim_brk_pend[0] = FALSE;\r |
| 3262 | AF = xororTable[((AF >> 8) | BC) & 0xff];\r |
| 3263 | break;\r |
| 3264 | \r |
| 3265 | case 0xb2: /* OR D */\r |
| 3266 | tStates += 4;\r |
| 3267 | sim_brk_pend[0] = FALSE;\r |
| 3268 | AF = xororTable[((AF | DE) >> 8) & 0xff];\r |
| 3269 | break;\r |
| 3270 | \r |
| 3271 | case 0xb3: /* OR E */\r |
| 3272 | tStates += 4;\r |
| 3273 | sim_brk_pend[0] = FALSE;\r |
| 3274 | AF = xororTable[((AF >> 8) | DE) & 0xff];\r |
| 3275 | break;\r |
| 3276 | \r |
| 3277 | case 0xb4: /* OR H */\r |
| 3278 | tStates += 4;\r |
| 3279 | sim_brk_pend[0] = FALSE;\r |
| 3280 | AF = xororTable[((AF | HL) >> 8) & 0xff];\r |
| 3281 | break;\r |
| 3282 | \r |
| 3283 | case 0xb5: /* OR L */\r |
| 3284 | tStates += 4;\r |
| 3285 | sim_brk_pend[0] = FALSE;\r |
| 3286 | AF = xororTable[((AF >> 8) | HL) & 0xff];\r |
| 3287 | break;\r |
| 3288 | \r |
| 3289 | case 0xb6: /* OR (HL) */\r |
| 3290 | tStates += 7;\r |
| 3291 | CHECK_BREAK_BYTE(HL);\r |
| 3292 | AF = xororTable[((AF >> 8) | GetBYTE(HL)) & 0xff];\r |
| 3293 | break;\r |
| 3294 | \r |
| 3295 | case 0xb7: /* OR A */\r |
| 3296 | tStates += 4;\r |
| 3297 | sim_brk_pend[0] = FALSE;\r |
| 3298 | AF = xororTable[(AF >> 8) & 0xff];\r |
| 3299 | break;\r |
| 3300 | \r |
| 3301 | case 0xb8: /* CP B */\r |
| 3302 | tStates += 4;\r |
| 3303 | sim_brk_pend[0] = FALSE;\r |
| 3304 | temp = HIGH_REGISTER(BC);\r |
| 3305 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 3306 | acu = HIGH_REGISTER(AF);\r |
| 3307 | sum = acu - temp;\r |
| 3308 | cbits = acu ^ temp ^ sum;\r |
| 3309 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 3310 | (SET_PV) | cbits2Table[cbits & 0x1ff];\r |
| 3311 | break;\r |
| 3312 | \r |
| 3313 | case 0xb9: /* CP C */\r |
| 3314 | tStates += 4;\r |
| 3315 | sim_brk_pend[0] = FALSE;\r |
| 3316 | temp = LOW_REGISTER(BC);\r |
| 3317 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 3318 | acu = HIGH_REGISTER(AF);\r |
| 3319 | sum = acu - temp;\r |
| 3320 | cbits = acu ^ temp ^ sum;\r |
| 3321 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 3322 | (SET_PV) | cbits2Table[cbits & 0x1ff];\r |
| 3323 | break;\r |
| 3324 | \r |
| 3325 | case 0xba: /* CP D */\r |
| 3326 | tStates += 4;\r |
| 3327 | sim_brk_pend[0] = FALSE;\r |
| 3328 | temp = HIGH_REGISTER(DE);\r |
| 3329 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 3330 | acu = HIGH_REGISTER(AF);\r |
| 3331 | sum = acu - temp;\r |
| 3332 | cbits = acu ^ temp ^ sum;\r |
| 3333 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 3334 | (SET_PV) | cbits2Table[cbits & 0x1ff];\r |
| 3335 | break;\r |
| 3336 | \r |
| 3337 | case 0xbb: /* CP E */\r |
| 3338 | tStates += 4;\r |
| 3339 | sim_brk_pend[0] = FALSE;\r |
| 3340 | temp = LOW_REGISTER(DE);\r |
| 3341 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 3342 | acu = HIGH_REGISTER(AF);\r |
| 3343 | sum = acu - temp;\r |
| 3344 | cbits = acu ^ temp ^ sum;\r |
| 3345 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 3346 | (SET_PV) | cbits2Table[cbits & 0x1ff];\r |
| 3347 | break;\r |
| 3348 | \r |
| 3349 | case 0xbc: /* CP H */\r |
| 3350 | tStates += 4;\r |
| 3351 | sim_brk_pend[0] = FALSE;\r |
| 3352 | temp = HIGH_REGISTER(HL);\r |
| 3353 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 3354 | acu = HIGH_REGISTER(AF);\r |
| 3355 | sum = acu - temp;\r |
| 3356 | cbits = acu ^ temp ^ sum;\r |
| 3357 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 3358 | (SET_PV) | cbits2Table[cbits & 0x1ff];\r |
| 3359 | break;\r |
| 3360 | \r |
| 3361 | case 0xbd: /* CP L */\r |
| 3362 | tStates += 4;\r |
| 3363 | sim_brk_pend[0] = FALSE;\r |
| 3364 | temp = LOW_REGISTER(HL);\r |
| 3365 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 3366 | acu = HIGH_REGISTER(AF);\r |
| 3367 | sum = acu - temp;\r |
| 3368 | cbits = acu ^ temp ^ sum;\r |
| 3369 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 3370 | (SET_PV) | cbits2Table[cbits & 0x1ff];\r |
| 3371 | break;\r |
| 3372 | \r |
| 3373 | case 0xbe: /* CP (HL) */\r |
| 3374 | tStates += 7;\r |
| 3375 | CHECK_BREAK_BYTE(HL);\r |
| 3376 | temp = GetBYTE(HL);\r |
| 3377 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 3378 | acu = HIGH_REGISTER(AF);\r |
| 3379 | sum = acu - temp;\r |
| 3380 | cbits = acu ^ temp ^ sum;\r |
| 3381 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 3382 | (SET_PV) | cbits2Table[cbits & 0x1ff];\r |
| 3383 | break;\r |
| 3384 | \r |
| 3385 | case 0xbf: /* CP A */\r |
| 3386 | tStates += 4;\r |
| 3387 | sim_brk_pend[0] = FALSE;\r |
| 3388 | SET_LOW_REGISTER(AF, (HIGH_REGISTER(AF) & 0x28) | (chiptype == CHIP_TYPE_Z80 ? 0x42 : 0x46));\r |
| 3389 | break;\r |
| 3390 | \r |
| 3391 | case 0xc0: /* RET NZ */\r |
| 3392 | if (TSTFLAG(Z)) {\r |
| 3393 | sim_brk_pend[0] = FALSE;\r |
| 3394 | tStates += 5;\r |
| 3395 | }\r |
| 3396 | else {\r |
| 3397 | CHECK_BREAK_WORD(SP);\r |
| 3398 | PCQ_ENTRY(PCX);\r |
| 3399 | POP(PC);\r |
| 3400 | tStates += 11;\r |
| 3401 | }\r |
| 3402 | break;\r |
| 3403 | \r |
| 3404 | case 0xc1: /* POP BC */\r |
| 3405 | tStates += 10;\r |
| 3406 | CHECK_BREAK_WORD(SP);\r |
| 3407 | POP(BC);\r |
| 3408 | break;\r |
| 3409 | \r |
| 3410 | case 0xc2: /* JP NZ,nnnn */\r |
| 3411 | sim_brk_pend[0] = FALSE;\r |
| 3412 | JPC(!TSTFLAG(Z)); /* also updates tStates */\r |
| 3413 | break;\r |
| 3414 | \r |
| 3415 | case 0xc3: /* JP nnnn */\r |
| 3416 | sim_brk_pend[0] = FALSE;\r |
| 3417 | JPC(1); /* also updates tStates */\r |
| 3418 | break;\r |
| 3419 | \r |
| 3420 | case 0xc4: /* CALL NZ,nnnn */\r |
| 3421 | CALLC(!TSTFLAG(Z)); /* also updates tStates */\r |
| 3422 | break;\r |
| 3423 | \r |
| 3424 | case 0xc5: /* PUSH BC */\r |
| 3425 | tStates += 11;\r |
| 3426 | CHECK_BREAK_WORD(SP - 2);\r |
| 3427 | PUSH(BC);\r |
| 3428 | break;\r |
| 3429 | \r |
| 3430 | case 0xc6: /* ADD A,nn */\r |
| 3431 | tStates += 7;\r |
| 3432 | sim_brk_pend[0] = FALSE;\r |
| 3433 | temp = RAM_PP(PC);\r |
| 3434 | acu = HIGH_REGISTER(AF);\r |
| 3435 | sum = acu + temp;\r |
| 3436 | cbits = acu ^ temp ^ sum;\r |
| 3437 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 3438 | break;\r |
| 3439 | \r |
| 3440 | case 0xc7: /* RST 0 */\r |
| 3441 | tStates += 11;\r |
| 3442 | CHECK_BREAK_WORD(SP - 2);\r |
| 3443 | PUSH(PC);\r |
| 3444 | PCQ_ENTRY(PCX);\r |
| 3445 | PC = 0;\r |
| 3446 | break;\r |
| 3447 | \r |
| 3448 | case 0xc8: /* RET Z */\r |
| 3449 | if (TSTFLAG(Z)) {\r |
| 3450 | CHECK_BREAK_WORD(SP);\r |
| 3451 | PCQ_ENTRY(PCX);\r |
| 3452 | POP(PC);\r |
| 3453 | tStates += 11;\r |
| 3454 | }\r |
| 3455 | else {\r |
| 3456 | sim_brk_pend[0] = FALSE;\r |
| 3457 | tStates += 5;\r |
| 3458 | }\r |
| 3459 | break;\r |
| 3460 | \r |
| 3461 | case 0xc9: /* RET */\r |
| 3462 | tStates += 10;\r |
| 3463 | CHECK_BREAK_WORD(SP);\r |
| 3464 | PCQ_ENTRY(PCX);\r |
| 3465 | POP(PC);\r |
| 3466 | break;\r |
| 3467 | \r |
| 3468 | case 0xca: /* JP Z,nnnn */\r |
| 3469 | sim_brk_pend[0] = FALSE;\r |
| 3470 | JPC(TSTFLAG(Z)); /* also updates tStates */\r |
| 3471 | break;\r |
| 3472 | \r |
| 3473 | case 0xcb: /* CB prefix */\r |
| 3474 | CHECK_CPU_8080;\r |
| 3475 | adr = HL;\r |
| 3476 | switch ((op = GetBYTE(PC)) & 7) {\r |
| 3477 | \r |
| 3478 | case 0:\r |
| 3479 | sim_brk_pend[0] = tStateModifier = FALSE;\r |
| 3480 | ++PC;\r |
| 3481 | acu = HIGH_REGISTER(BC);\r |
| 3482 | tStates += 8;\r |
| 3483 | break;\r |
| 3484 | \r |
| 3485 | case 1:\r |
| 3486 | sim_brk_pend[0] = tStateModifier = FALSE;\r |
| 3487 | ++PC;\r |
| 3488 | acu = LOW_REGISTER(BC);\r |
| 3489 | tStates += 8;\r |
| 3490 | break;\r |
| 3491 | \r |
| 3492 | case 2:\r |
| 3493 | sim_brk_pend[0] = tStateModifier = FALSE;\r |
| 3494 | ++PC;\r |
| 3495 | acu = HIGH_REGISTER(DE);\r |
| 3496 | tStates += 8;\r |
| 3497 | break;\r |
| 3498 | \r |
| 3499 | case 3:\r |
| 3500 | sim_brk_pend[0] = tStateModifier = FALSE;\r |
| 3501 | ++PC;\r |
| 3502 | acu = LOW_REGISTER(DE);\r |
| 3503 | tStates += 8;\r |
| 3504 | break;\r |
| 3505 | \r |
| 3506 | case 4:\r |
| 3507 | sim_brk_pend[0] = tStateModifier = FALSE;\r |
| 3508 | ++PC;\r |
| 3509 | acu = HIGH_REGISTER(HL);\r |
| 3510 | tStates += 8;\r |
| 3511 | break;\r |
| 3512 | \r |
| 3513 | case 5:\r |
| 3514 | sim_brk_pend[0] = tStateModifier = FALSE;\r |
| 3515 | ++PC;\r |
| 3516 | acu = LOW_REGISTER(HL);\r |
| 3517 | tStates += 8;\r |
| 3518 | break;\r |
| 3519 | \r |
| 3520 | case 6:\r |
| 3521 | CHECK_BREAK_BYTE(adr);\r |
| 3522 | ++PC;\r |
| 3523 | acu = GetBYTE(adr);\r |
| 3524 | tStateModifier = TRUE;\r |
| 3525 | tStates += 15;\r |
| 3526 | break;\r |
| 3527 | \r |
| 3528 | case 7:\r |
| 3529 | sim_brk_pend[0] = tStateModifier = FALSE;\r |
| 3530 | ++PC;\r |
| 3531 | acu = HIGH_REGISTER(AF);\r |
| 3532 | tStates += 8;\r |
| 3533 | break;\r |
| 3534 | }\r |
| 3535 | switch (op & 0xc0) {\r |
| 3536 | \r |
| 3537 | case 0x00: /* shift/rotate */\r |
| 3538 | switch (op & 0x38) {\r |
| 3539 | \r |
| 3540 | case 0x00: /* RLC */\r |
| 3541 | temp = (acu << 1) | (acu >> 7);\r |
| 3542 | cbits = temp & 1;\r |
| 3543 | goto cbshflg1;\r |
| 3544 | \r |
| 3545 | case 0x08: /* RRC */\r |
| 3546 | temp = (acu >> 1) | (acu << 7);\r |
| 3547 | cbits = temp & 0x80;\r |
| 3548 | goto cbshflg1;\r |
| 3549 | \r |
| 3550 | case 0x10: /* RL */\r |
| 3551 | temp = (acu << 1) | TSTFLAG(C);\r |
| 3552 | cbits = acu & 0x80;\r |
| 3553 | goto cbshflg1;\r |
| 3554 | \r |
| 3555 | case 0x18: /* RR */\r |
| 3556 | temp = (acu >> 1) | (TSTFLAG(C) << 7);\r |
| 3557 | cbits = acu & 1;\r |
| 3558 | goto cbshflg1;\r |
| 3559 | \r |
| 3560 | case 0x20: /* SLA */\r |
| 3561 | temp = acu << 1;\r |
| 3562 | cbits = acu & 0x80;\r |
| 3563 | goto cbshflg1;\r |
| 3564 | \r |
| 3565 | case 0x28: /* SRA */\r |
| 3566 | temp = (acu >> 1) | (acu & 0x80);\r |
| 3567 | cbits = acu & 1;\r |
| 3568 | goto cbshflg1;\r |
| 3569 | \r |
| 3570 | case 0x30: /* SLIA */\r |
| 3571 | temp = (acu << 1) | 1;\r |
| 3572 | cbits = acu & 0x80;\r |
| 3573 | goto cbshflg1;\r |
| 3574 | \r |
| 3575 | case 0x38: /* SRL */\r |
| 3576 | temp = acu >> 1;\r |
| 3577 | cbits = acu & 1;\r |
| 3578 | cbshflg1:\r |
| 3579 | AF = (AF & ~0xff) | rotateShiftTable[temp & 0xff] | !!cbits;\r |
| 3580 | /* !!cbits == 0 if cbits == 0 !!cbits == 1 if cbits > 0 */\r |
| 3581 | }\r |
| 3582 | break;\r |
| 3583 | \r |
| 3584 | case 0x40: /* BIT */\r |
| 3585 | if (tStateModifier) tStates -= 3;\r |
| 3586 | if (acu & (1 << ((op >> 3) & 7)))\r |
| 3587 | AF = (AF & ~0xfe) | 0x10 | (((op & 0x38) == 0x38) << 7);\r |
| 3588 | else AF = (AF & ~0xfe) | 0x54;\r |
| 3589 | if ((op & 7) != 6) AF |= (acu & 0x28);\r |
| 3590 | temp = acu;\r |
| 3591 | break;\r |
| 3592 | \r |
| 3593 | case 0x80: /* RES */\r |
| 3594 | temp = acu & ~(1 << ((op >> 3) & 7));\r |
| 3595 | break;\r |
| 3596 | \r |
| 3597 | case 0xc0: /* SET */\r |
| 3598 | temp = acu | (1 << ((op >> 3) & 7));\r |
| 3599 | break;\r |
| 3600 | }\r |
| 3601 | \r |
| 3602 | switch (op & 7) {\r |
| 3603 | \r |
| 3604 | case 0:\r |
| 3605 | SET_HIGH_REGISTER(BC, temp);\r |
| 3606 | break;\r |
| 3607 | \r |
| 3608 | case 1:\r |
| 3609 | SET_LOW_REGISTER(BC, temp);\r |
| 3610 | break;\r |
| 3611 | \r |
| 3612 | case 2:\r |
| 3613 | SET_HIGH_REGISTER(DE, temp);\r |
| 3614 | break;\r |
| 3615 | \r |
| 3616 | case 3:\r |
| 3617 | SET_LOW_REGISTER(DE, temp);\r |
| 3618 | break;\r |
| 3619 | \r |
| 3620 | case 4:\r |
| 3621 | SET_HIGH_REGISTER(HL, temp);\r |
| 3622 | break;\r |
| 3623 | \r |
| 3624 | case 5:\r |
| 3625 | SET_LOW_REGISTER(HL, temp);\r |
| 3626 | break;\r |
| 3627 | \r |
| 3628 | case 6:\r |
| 3629 | PutBYTE(adr, temp);\r |
| 3630 | break;\r |
| 3631 | \r |
| 3632 | case 7:\r |
| 3633 | SET_HIGH_REGISTER(AF, temp);\r |
| 3634 | break;\r |
| 3635 | }\r |
| 3636 | break;\r |
| 3637 | \r |
| 3638 | case 0xcc: /* CALL Z,nnnn */\r |
| 3639 | CALLC(TSTFLAG(Z)); /* also updates tStates */\r |
| 3640 | break;\r |
| 3641 | \r |
| 3642 | case 0xcd: /* CALL nnnn */\r |
| 3643 | CALLC(1); /* also updates tStates */\r |
| 3644 | break;\r |
| 3645 | \r |
| 3646 | case 0xce: /* ADC A,nn */\r |
| 3647 | tStates += 7;\r |
| 3648 | sim_brk_pend[0] = FALSE;\r |
| 3649 | temp = RAM_PP(PC);\r |
| 3650 | acu = HIGH_REGISTER(AF);\r |
| 3651 | sum = acu + temp + TSTFLAG(C);\r |
| 3652 | cbits = acu ^ temp ^ sum;\r |
| 3653 | AF = addTable[sum] | cbitsTable[cbits] | (SET_PV);\r |
| 3654 | break;\r |
| 3655 | \r |
| 3656 | case 0xcf: /* RST 8 */\r |
| 3657 | tStates += 11;\r |
| 3658 | CHECK_BREAK_WORD(SP - 2);\r |
| 3659 | PUSH(PC);\r |
| 3660 | PCQ_ENTRY(PCX);\r |
| 3661 | PC = 8;\r |
| 3662 | break;\r |
| 3663 | \r |
| 3664 | case 0xd0: /* RET NC */\r |
| 3665 | if (TSTFLAG(C)) {\r |
| 3666 | sim_brk_pend[0] = FALSE;\r |
| 3667 | tStates += 5;\r |
| 3668 | }\r |
| 3669 | else {\r |
| 3670 | CHECK_BREAK_WORD(SP);\r |
| 3671 | PCQ_ENTRY(PCX);\r |
| 3672 | POP(PC);\r |
| 3673 | tStates += 11;\r |
| 3674 | }\r |
| 3675 | break;\r |
| 3676 | \r |
| 3677 | case 0xd1: /* POP DE */\r |
| 3678 | tStates += 10;\r |
| 3679 | CHECK_BREAK_WORD(SP);\r |
| 3680 | POP(DE);\r |
| 3681 | break;\r |
| 3682 | \r |
| 3683 | case 0xd2: /* JP NC,nnnn */\r |
| 3684 | sim_brk_pend[0] = FALSE;\r |
| 3685 | JPC(!TSTFLAG(C)); /* also updates tStates */\r |
| 3686 | break;\r |
| 3687 | \r |
| 3688 | case 0xd3: /* OUT (nn),A */\r |
| 3689 | tStates += 11;\r |
| 3690 | sim_brk_pend[0] = FALSE;\r |
| 3691 | out(RAM_PP(PC), HIGH_REGISTER(AF));\r |
| 3692 | break;\r |
| 3693 | \r |
| 3694 | case 0xd4: /* CALL NC,nnnn */\r |
| 3695 | CALLC(!TSTFLAG(C)); /* also updates tStates */\r |
| 3696 | break;\r |
| 3697 | \r |
| 3698 | case 0xd5: /* PUSH DE */\r |
| 3699 | tStates += 11;\r |
| 3700 | CHECK_BREAK_WORD(SP - 2);\r |
| 3701 | PUSH(DE);\r |
| 3702 | break;\r |
| 3703 | \r |
| 3704 | case 0xd6: /* SUB nn */\r |
| 3705 | tStates += 7;\r |
| 3706 | sim_brk_pend[0] = FALSE;\r |
| 3707 | temp = RAM_PP(PC);\r |
| 3708 | acu = HIGH_REGISTER(AF);\r |
| 3709 | sum = acu - temp;\r |
| 3710 | cbits = acu ^ temp ^ sum;\r |
| 3711 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 3712 | break;\r |
| 3713 | \r |
| 3714 | case 0xd7: /* RST 10H */\r |
| 3715 | tStates += 11;\r |
| 3716 | CHECK_BREAK_WORD(SP - 2);\r |
| 3717 | PUSH(PC);\r |
| 3718 | PCQ_ENTRY(PCX);\r |
| 3719 | PC = 0x10;\r |
| 3720 | break;\r |
| 3721 | \r |
| 3722 | case 0xd8: /* RET C */\r |
| 3723 | if (TSTFLAG(C)) {\r |
| 3724 | CHECK_BREAK_WORD(SP);\r |
| 3725 | PCQ_ENTRY(PCX);\r |
| 3726 | POP(PC);\r |
| 3727 | tStates += 11;\r |
| 3728 | }\r |
| 3729 | else {\r |
| 3730 | sim_brk_pend[0] = FALSE;\r |
| 3731 | tStates += 5;\r |
| 3732 | }\r |
| 3733 | break;\r |
| 3734 | \r |
| 3735 | case 0xd9: /* EXX */\r |
| 3736 | tStates += 4;\r |
| 3737 | sim_brk_pend[0] = FALSE;\r |
| 3738 | CHECK_CPU_8080;\r |
| 3739 | temp = BC;\r |
| 3740 | BC = BC1_S;\r |
| 3741 | BC1_S = temp;\r |
| 3742 | temp = DE;\r |
| 3743 | DE = DE1_S;\r |
| 3744 | DE1_S = temp;\r |
| 3745 | temp = HL;\r |
| 3746 | HL = HL1_S;\r |
| 3747 | HL1_S = temp;\r |
| 3748 | break;\r |
| 3749 | \r |
| 3750 | case 0xda: /* JP C,nnnn */\r |
| 3751 | sim_brk_pend[0] = FALSE;\r |
| 3752 | JPC(TSTFLAG(C)); /* also updates tStates */\r |
| 3753 | break;\r |
| 3754 | \r |
| 3755 | case 0xdb: /* IN A,(nn) */\r |
| 3756 | tStates += 11;\r |
| 3757 | sim_brk_pend[0] = FALSE;\r |
| 3758 | SET_HIGH_REGISTER(AF, in(RAM_PP(PC)));\r |
| 3759 | break;\r |
| 3760 | \r |
| 3761 | case 0xdc: /* CALL C,nnnn */\r |
| 3762 | CALLC(TSTFLAG(C)); /* also updates tStates */\r |
| 3763 | break;\r |
| 3764 | \r |
| 3765 | case 0xdd: /* DD prefix */\r |
| 3766 | CHECK_CPU_8080;\r |
| 3767 | switch (op = RAM_PP(PC)) {\r |
| 3768 | \r |
| 3769 | case 0x09: /* ADD IX,BC */\r |
| 3770 | tStates += 15;\r |
| 3771 | sim_brk_pend[0] = FALSE;\r |
| 3772 | IX &= ADDRMASK;\r |
| 3773 | BC &= ADDRMASK;\r |
| 3774 | sum = IX + BC;\r |
| 3775 | AF = (AF & ~0x3b) | ((sum >> 8) & 0x28) | cbitsTable[(IX ^ BC ^ sum) >> 8];\r |
| 3776 | IX = sum;\r |
| 3777 | break;\r |
| 3778 | \r |
| 3779 | case 0x19: /* ADD IX,DE */\r |
| 3780 | tStates += 15;\r |
| 3781 | sim_brk_pend[0] = FALSE;\r |
| 3782 | IX &= ADDRMASK;\r |
| 3783 | DE &= ADDRMASK;\r |
| 3784 | sum = IX + DE;\r |
| 3785 | AF = (AF & ~0x3b) | ((sum >> 8) & 0x28) | cbitsTable[(IX ^ DE ^ sum) >> 8];\r |
| 3786 | IX = sum;\r |
| 3787 | break;\r |
| 3788 | \r |
| 3789 | case 0x21: /* LD IX,nnnn */\r |
| 3790 | tStates += 14;\r |
| 3791 | sim_brk_pend[0] = FALSE;\r |
| 3792 | IX = GET_WORD(PC);\r |
| 3793 | PC += 2;\r |
| 3794 | break;\r |
| 3795 | \r |
| 3796 | case 0x22: /* LD (nnnn),IX */\r |
| 3797 | tStates += 20;\r |
| 3798 | temp = GET_WORD(PC);\r |
| 3799 | CHECK_BREAK_WORD(temp);\r |
| 3800 | PutWORD(temp, IX);\r |
| 3801 | PC += 2;\r |
| 3802 | break;\r |
| 3803 | \r |
| 3804 | case 0x23: /* INC IX */\r |
| 3805 | tStates += 10;\r |
| 3806 | sim_brk_pend[0] = FALSE;\r |
| 3807 | ++IX;\r |
| 3808 | break;\r |
| 3809 | \r |
| 3810 | case 0x24: /* INC IXH */\r |
| 3811 | tStates += 9;\r |
| 3812 | sim_brk_pend[0] = FALSE;\r |
| 3813 | IX += 0x100;\r |
| 3814 | AF = (AF & ~0xfe) | incZ80Table[HIGH_REGISTER(IX)];\r |
| 3815 | break;\r |
| 3816 | \r |
| 3817 | case 0x25: /* DEC IXH */\r |
| 3818 | tStates += 9;\r |
| 3819 | sim_brk_pend[0] = FALSE;\r |
| 3820 | IX -= 0x100;\r |
| 3821 | AF = (AF & ~0xfe) | decZ80Table[HIGH_REGISTER(IX)];\r |
| 3822 | break;\r |
| 3823 | \r |
| 3824 | case 0x26: /* LD IXH,nn */\r |
| 3825 | tStates += 9;\r |
| 3826 | sim_brk_pend[0] = FALSE;\r |
| 3827 | SET_HIGH_REGISTER(IX, RAM_PP(PC));\r |
| 3828 | break;\r |
| 3829 | \r |
| 3830 | case 0x29: /* ADD IX,IX */\r |
| 3831 | tStates += 15;\r |
| 3832 | sim_brk_pend[0] = FALSE;\r |
| 3833 | IX &= ADDRMASK;\r |
| 3834 | sum = IX + IX;\r |
| 3835 | AF = (AF & ~0x3b) | cbitsDup16Table[sum >> 8];\r |
| 3836 | IX = sum;\r |
| 3837 | break;\r |
| 3838 | \r |
| 3839 | case 0x2a: /* LD IX,(nnnn) */\r |
| 3840 | tStates += 20;\r |
| 3841 | temp = GET_WORD(PC);\r |
| 3842 | CHECK_BREAK_WORD(temp);\r |
| 3843 | IX = GET_WORD(temp);\r |
| 3844 | PC += 2;\r |
| 3845 | break;\r |
| 3846 | \r |
| 3847 | case 0x2b: /* DEC IX */\r |
| 3848 | tStates += 10;\r |
| 3849 | sim_brk_pend[0] = FALSE;\r |
| 3850 | --IX;\r |
| 3851 | break;\r |
| 3852 | \r |
| 3853 | case 0x2c: /* INC IXL */\r |
| 3854 | tStates += 9;\r |
| 3855 | sim_brk_pend[0] = FALSE;\r |
| 3856 | temp = LOW_REGISTER(IX) + 1;\r |
| 3857 | SET_LOW_REGISTER(IX, temp);\r |
| 3858 | AF = (AF & ~0xfe) | incZ80Table[temp];\r |
| 3859 | break;\r |
| 3860 | \r |
| 3861 | case 0x2d: /* DEC IXL */\r |
| 3862 | tStates += 9;\r |
| 3863 | sim_brk_pend[0] = FALSE;\r |
| 3864 | temp = LOW_REGISTER(IX) - 1;\r |
| 3865 | SET_LOW_REGISTER(IX, temp);\r |
| 3866 | AF = (AF & ~0xfe) | decZ80Table[temp & 0xff];\r |
| 3867 | break;\r |
| 3868 | \r |
| 3869 | case 0x2e: /* LD IXL,nn */\r |
| 3870 | tStates += 9;\r |
| 3871 | sim_brk_pend[0] = FALSE;\r |
| 3872 | SET_LOW_REGISTER(IX, RAM_PP(PC));\r |
| 3873 | break;\r |
| 3874 | \r |
| 3875 | case 0x34: /* INC (IX+dd) */\r |
| 3876 | tStates += 23;\r |
| 3877 | adr = IX + (int8) RAM_PP(PC);\r |
| 3878 | CHECK_BREAK_BYTE(adr);\r |
| 3879 | temp = GetBYTE(adr) + 1;\r |
| 3880 | PutBYTE(adr, temp);\r |
| 3881 | AF = (AF & ~0xfe) | incZ80Table[temp];\r |
| 3882 | break;\r |
| 3883 | \r |
| 3884 | case 0x35: /* DEC (IX+dd) */\r |
| 3885 | tStates += 23;\r |
| 3886 | adr = IX + (int8) RAM_PP(PC);\r |
| 3887 | CHECK_BREAK_BYTE(adr);\r |
| 3888 | temp = GetBYTE(adr) - 1;\r |
| 3889 | PutBYTE(adr, temp);\r |
| 3890 | AF = (AF & ~0xfe) | decZ80Table[temp & 0xff];\r |
| 3891 | break;\r |
| 3892 | \r |
| 3893 | case 0x36: /* LD (IX+dd),nn */\r |
| 3894 | tStates += 19;\r |
| 3895 | adr = IX + (int8) RAM_PP(PC);\r |
| 3896 | CHECK_BREAK_BYTE(adr);\r |
| 3897 | PutBYTE(adr, RAM_PP(PC));\r |
| 3898 | break;\r |
| 3899 | \r |
| 3900 | case 0x39: /* ADD IX,SP */\r |
| 3901 | tStates += 15;\r |
| 3902 | sim_brk_pend[0] = FALSE;\r |
| 3903 | IX &= ADDRMASK;\r |
| 3904 | SP &= ADDRMASK;\r |
| 3905 | sum = IX + SP;\r |
| 3906 | AF = (AF & ~0x3b) | ((sum >> 8) & 0x28) | cbitsTable[(IX ^ SP ^ sum) >> 8];\r |
| 3907 | IX = sum;\r |
| 3908 | break;\r |
| 3909 | \r |
| 3910 | case 0x44: /* LD B,IXH */\r |
| 3911 | tStates += 9;\r |
| 3912 | sim_brk_pend[0] = FALSE;\r |
| 3913 | SET_HIGH_REGISTER(BC, HIGH_REGISTER(IX));\r |
| 3914 | break;\r |
| 3915 | \r |
| 3916 | case 0x45: /* LD B,IXL */\r |
| 3917 | tStates += 9;\r |
| 3918 | sim_brk_pend[0] = FALSE;\r |
| 3919 | SET_HIGH_REGISTER(BC, LOW_REGISTER(IX));\r |
| 3920 | break;\r |
| 3921 | \r |
| 3922 | case 0x46: /* LD B,(IX+dd) */\r |
| 3923 | tStates += 19;\r |
| 3924 | adr = IX + (int8) RAM_PP(PC);\r |
| 3925 | CHECK_BREAK_BYTE(adr);\r |
| 3926 | SET_HIGH_REGISTER(BC, GetBYTE(adr));\r |
| 3927 | break;\r |
| 3928 | \r |
| 3929 | case 0x4c: /* LD C,IXH */\r |
| 3930 | tStates += 9;\r |
| 3931 | sim_brk_pend[0] = FALSE;\r |
| 3932 | SET_LOW_REGISTER(BC, HIGH_REGISTER(IX));\r |
| 3933 | break;\r |
| 3934 | \r |
| 3935 | case 0x4d: /* LD C,IXL */\r |
| 3936 | tStates += 9;\r |
| 3937 | sim_brk_pend[0] = FALSE;\r |
| 3938 | SET_LOW_REGISTER(BC, LOW_REGISTER(IX));\r |
| 3939 | break;\r |
| 3940 | \r |
| 3941 | case 0x4e: /* LD C,(IX+dd) */\r |
| 3942 | tStates += 19;\r |
| 3943 | adr = IX + (int8) RAM_PP(PC);\r |
| 3944 | CHECK_BREAK_BYTE(adr);\r |
| 3945 | SET_LOW_REGISTER(BC, GetBYTE(adr));\r |
| 3946 | break;\r |
| 3947 | \r |
| 3948 | case 0x54: /* LD D,IXH */\r |
| 3949 | tStates += 9;\r |
| 3950 | sim_brk_pend[0] = FALSE;\r |
| 3951 | SET_HIGH_REGISTER(DE, HIGH_REGISTER(IX));\r |
| 3952 | break;\r |
| 3953 | \r |
| 3954 | case 0x55: /* LD D,IXL */\r |
| 3955 | tStates += 9;\r |
| 3956 | sim_brk_pend[0] = FALSE;\r |
| 3957 | SET_HIGH_REGISTER(DE, LOW_REGISTER(IX));\r |
| 3958 | break;\r |
| 3959 | \r |
| 3960 | case 0x56: /* LD D,(IX+dd) */\r |
| 3961 | tStates += 19;\r |
| 3962 | adr = IX + (int8) RAM_PP(PC);\r |
| 3963 | CHECK_BREAK_BYTE(adr);\r |
| 3964 | SET_HIGH_REGISTER(DE, GetBYTE(adr));\r |
| 3965 | break;\r |
| 3966 | \r |
| 3967 | case 0x5c: /* LD E,IXH */\r |
| 3968 | tStates += 9;\r |
| 3969 | sim_brk_pend[0] = FALSE;\r |
| 3970 | SET_LOW_REGISTER(DE, HIGH_REGISTER(IX));\r |
| 3971 | break;\r |
| 3972 | \r |
| 3973 | case 0x5d: /* LD E,IXL */\r |
| 3974 | tStates += 9;\r |
| 3975 | sim_brk_pend[0] = FALSE;\r |
| 3976 | SET_LOW_REGISTER(DE, LOW_REGISTER(IX));\r |
| 3977 | break;\r |
| 3978 | \r |
| 3979 | case 0x5e: /* LD E,(IX+dd) */\r |
| 3980 | tStates += 19;\r |
| 3981 | adr = IX + (int8) RAM_PP(PC);\r |
| 3982 | CHECK_BREAK_BYTE(adr);\r |
| 3983 | SET_LOW_REGISTER(DE, GetBYTE(adr));\r |
| 3984 | break;\r |
| 3985 | \r |
| 3986 | case 0x60: /* LD IXH,B */\r |
| 3987 | tStates += 9;\r |
| 3988 | sim_brk_pend[0] = FALSE;\r |
| 3989 | SET_HIGH_REGISTER(IX, HIGH_REGISTER(BC));\r |
| 3990 | break;\r |
| 3991 | \r |
| 3992 | case 0x61: /* LD IXH,C */\r |
| 3993 | tStates += 9;\r |
| 3994 | sim_brk_pend[0] = FALSE;\r |
| 3995 | SET_HIGH_REGISTER(IX, LOW_REGISTER(BC));\r |
| 3996 | break;\r |
| 3997 | \r |
| 3998 | case 0x62: /* LD IXH,D */\r |
| 3999 | tStates += 9;\r |
| 4000 | sim_brk_pend[0] = FALSE;\r |
| 4001 | SET_HIGH_REGISTER(IX, HIGH_REGISTER(DE));\r |
| 4002 | break;\r |
| 4003 | \r |
| 4004 | case 0x63: /* LD IXH,E */\r |
| 4005 | tStates += 9;\r |
| 4006 | sim_brk_pend[0] = FALSE;\r |
| 4007 | SET_HIGH_REGISTER(IX, LOW_REGISTER(DE));\r |
| 4008 | break;\r |
| 4009 | \r |
| 4010 | case 0x64: /* LD IXH,IXH */\r |
| 4011 | tStates += 9;\r |
| 4012 | sim_brk_pend[0] = FALSE; /* nop */\r |
| 4013 | break;\r |
| 4014 | \r |
| 4015 | case 0x65: /* LD IXH,IXL */\r |
| 4016 | tStates += 9;\r |
| 4017 | sim_brk_pend[0] = FALSE;\r |
| 4018 | SET_HIGH_REGISTER(IX, LOW_REGISTER(IX));\r |
| 4019 | break;\r |
| 4020 | \r |
| 4021 | case 0x66: /* LD H,(IX+dd) */\r |
| 4022 | tStates += 19;\r |
| 4023 | adr = IX + (int8) RAM_PP(PC);\r |
| 4024 | CHECK_BREAK_BYTE(adr);\r |
| 4025 | SET_HIGH_REGISTER(HL, GetBYTE(adr));\r |
| 4026 | break;\r |
| 4027 | \r |
| 4028 | case 0x67: /* LD IXH,A */\r |
| 4029 | tStates += 9;\r |
| 4030 | sim_brk_pend[0] = FALSE;\r |
| 4031 | SET_HIGH_REGISTER(IX, HIGH_REGISTER(AF));\r |
| 4032 | break;\r |
| 4033 | \r |
| 4034 | case 0x68: /* LD IXL,B */\r |
| 4035 | tStates += 9;\r |
| 4036 | sim_brk_pend[0] = FALSE;\r |
| 4037 | SET_LOW_REGISTER(IX, HIGH_REGISTER(BC));\r |
| 4038 | break;\r |
| 4039 | \r |
| 4040 | case 0x69: /* LD IXL,C */\r |
| 4041 | tStates += 9;\r |
| 4042 | sim_brk_pend[0] = FALSE;\r |
| 4043 | SET_LOW_REGISTER(IX, LOW_REGISTER(BC));\r |
| 4044 | break;\r |
| 4045 | \r |
| 4046 | case 0x6a: /* LD IXL,D */\r |
| 4047 | tStates += 9;\r |
| 4048 | sim_brk_pend[0] = FALSE;\r |
| 4049 | SET_LOW_REGISTER(IX, HIGH_REGISTER(DE));\r |
| 4050 | break;\r |
| 4051 | \r |
| 4052 | case 0x6b: /* LD IXL,E */\r |
| 4053 | tStates += 9;\r |
| 4054 | sim_brk_pend[0] = FALSE;\r |
| 4055 | SET_LOW_REGISTER(IX, LOW_REGISTER(DE));\r |
| 4056 | break;\r |
| 4057 | \r |
| 4058 | case 0x6c: /* LD IXL,IXH */\r |
| 4059 | tStates += 9;\r |
| 4060 | sim_brk_pend[0] = FALSE;\r |
| 4061 | SET_LOW_REGISTER(IX, HIGH_REGISTER(IX));\r |
| 4062 | break;\r |
| 4063 | \r |
| 4064 | case 0x6d: /* LD IXL,IXL */\r |
| 4065 | tStates += 9;\r |
| 4066 | sim_brk_pend[0] = FALSE; /* nop */\r |
| 4067 | break;\r |
| 4068 | \r |
| 4069 | case 0x6e: /* LD L,(IX+dd) */\r |
| 4070 | tStates += 19;\r |
| 4071 | adr = IX + (int8) RAM_PP(PC);\r |
| 4072 | CHECK_BREAK_BYTE(adr);\r |
| 4073 | SET_LOW_REGISTER(HL, GetBYTE(adr));\r |
| 4074 | break;\r |
| 4075 | \r |
| 4076 | case 0x6f: /* LD IXL,A */\r |
| 4077 | tStates += 9;\r |
| 4078 | sim_brk_pend[0] = FALSE;\r |
| 4079 | SET_LOW_REGISTER(IX, HIGH_REGISTER(AF));\r |
| 4080 | break;\r |
| 4081 | \r |
| 4082 | case 0x70: /* LD (IX+dd),B */\r |
| 4083 | tStates += 19;\r |
| 4084 | adr = IX + (int8) RAM_PP(PC);\r |
| 4085 | CHECK_BREAK_BYTE(adr);\r |
| 4086 | PutBYTE(adr, HIGH_REGISTER(BC));\r |
| 4087 | break;\r |
| 4088 | \r |
| 4089 | case 0x71: /* LD (IX+dd),C */\r |
| 4090 | tStates += 19;\r |
| 4091 | adr = IX + (int8) RAM_PP(PC);\r |
| 4092 | CHECK_BREAK_BYTE(adr);\r |
| 4093 | PutBYTE(adr, LOW_REGISTER(BC));\r |
| 4094 | break;\r |
| 4095 | \r |
| 4096 | case 0x72: /* LD (IX+dd),D */\r |
| 4097 | tStates += 19;\r |
| 4098 | adr = IX + (int8) RAM_PP(PC);\r |
| 4099 | CHECK_BREAK_BYTE(adr);\r |
| 4100 | PutBYTE(adr, HIGH_REGISTER(DE));\r |
| 4101 | break;\r |
| 4102 | \r |
| 4103 | case 0x73: /* LD (IX+dd),E */\r |
| 4104 | tStates += 19;\r |
| 4105 | adr = IX + (int8) RAM_PP(PC);\r |
| 4106 | CHECK_BREAK_BYTE(adr);\r |
| 4107 | PutBYTE(adr, LOW_REGISTER(DE));\r |
| 4108 | break;\r |
| 4109 | \r |
| 4110 | case 0x74: /* LD (IX+dd),H */\r |
| 4111 | tStates += 19;\r |
| 4112 | adr = IX + (int8) RAM_PP(PC);\r |
| 4113 | CHECK_BREAK_BYTE(adr);\r |
| 4114 | PutBYTE(adr, HIGH_REGISTER(HL));\r |
| 4115 | break;\r |
| 4116 | \r |
| 4117 | case 0x75: /* LD (IX+dd),L */\r |
| 4118 | tStates += 19;\r |
| 4119 | adr = IX + (int8) RAM_PP(PC);\r |
| 4120 | CHECK_BREAK_BYTE(adr);\r |
| 4121 | PutBYTE(adr, LOW_REGISTER(HL));\r |
| 4122 | break;\r |
| 4123 | \r |
| 4124 | case 0x77: /* LD (IX+dd),A */\r |
| 4125 | tStates += 19;\r |
| 4126 | adr = IX + (int8) RAM_PP(PC);\r |
| 4127 | CHECK_BREAK_BYTE(adr);\r |
| 4128 | PutBYTE(adr, HIGH_REGISTER(AF));\r |
| 4129 | break;\r |
| 4130 | \r |
| 4131 | case 0x7c: /* LD A,IXH */\r |
| 4132 | tStates += 9;\r |
| 4133 | sim_brk_pend[0] = FALSE;\r |
| 4134 | SET_HIGH_REGISTER(AF, HIGH_REGISTER(IX));\r |
| 4135 | break;\r |
| 4136 | \r |
| 4137 | case 0x7d: /* LD A,IXL */\r |
| 4138 | tStates += 9;\r |
| 4139 | sim_brk_pend[0] = FALSE;\r |
| 4140 | SET_HIGH_REGISTER(AF, LOW_REGISTER(IX));\r |
| 4141 | break;\r |
| 4142 | \r |
| 4143 | case 0x7e: /* LD A,(IX+dd) */\r |
| 4144 | tStates += 19;\r |
| 4145 | adr = IX + (int8) RAM_PP(PC);\r |
| 4146 | CHECK_BREAK_BYTE(adr);\r |
| 4147 | SET_HIGH_REGISTER(AF, GetBYTE(adr));\r |
| 4148 | break;\r |
| 4149 | \r |
| 4150 | case 0x84: /* ADD A,IXH */\r |
| 4151 | tStates += 9;\r |
| 4152 | sim_brk_pend[0] = FALSE;\r |
| 4153 | temp = HIGH_REGISTER(IX);\r |
| 4154 | acu = HIGH_REGISTER(AF);\r |
| 4155 | sum = acu + temp;\r |
| 4156 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 4157 | break;\r |
| 4158 | \r |
| 4159 | case 0x85: /* ADD A,IXL */\r |
| 4160 | tStates += 9;\r |
| 4161 | sim_brk_pend[0] = FALSE;\r |
| 4162 | temp = LOW_REGISTER(IX);\r |
| 4163 | acu = HIGH_REGISTER(AF);\r |
| 4164 | sum = acu + temp;\r |
| 4165 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 4166 | break;\r |
| 4167 | \r |
| 4168 | case 0x86: /* ADD A,(IX+dd) */\r |
| 4169 | tStates += 19;\r |
| 4170 | adr = IX + (int8) RAM_PP(PC);\r |
| 4171 | CHECK_BREAK_BYTE(adr);\r |
| 4172 | temp = GetBYTE(adr);\r |
| 4173 | acu = HIGH_REGISTER(AF);\r |
| 4174 | sum = acu + temp;\r |
| 4175 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 4176 | break;\r |
| 4177 | \r |
| 4178 | case 0x8c: /* ADC A,IXH */\r |
| 4179 | tStates += 9;\r |
| 4180 | sim_brk_pend[0] = FALSE;\r |
| 4181 | temp = HIGH_REGISTER(IX);\r |
| 4182 | acu = HIGH_REGISTER(AF);\r |
| 4183 | sum = acu + temp + TSTFLAG(C);\r |
| 4184 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 4185 | break;\r |
| 4186 | \r |
| 4187 | case 0x8d: /* ADC A,IXL */\r |
| 4188 | tStates += 9;\r |
| 4189 | sim_brk_pend[0] = FALSE;\r |
| 4190 | temp = LOW_REGISTER(IX);\r |
| 4191 | acu = HIGH_REGISTER(AF);\r |
| 4192 | sum = acu + temp + TSTFLAG(C);\r |
| 4193 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 4194 | break;\r |
| 4195 | \r |
| 4196 | case 0x8e: /* ADC A,(IX+dd) */\r |
| 4197 | tStates += 19;\r |
| 4198 | adr = IX + (int8) RAM_PP(PC);\r |
| 4199 | CHECK_BREAK_BYTE(adr);\r |
| 4200 | temp = GetBYTE(adr);\r |
| 4201 | acu = HIGH_REGISTER(AF);\r |
| 4202 | sum = acu + temp + TSTFLAG(C);\r |
| 4203 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 4204 | break;\r |
| 4205 | \r |
| 4206 | case 0x96: /* SUB (IX+dd) */\r |
| 4207 | tStates += 19;\r |
| 4208 | adr = IX + (int8) RAM_PP(PC);\r |
| 4209 | CHECK_BREAK_BYTE(adr);\r |
| 4210 | temp = GetBYTE(adr);\r |
| 4211 | acu = HIGH_REGISTER(AF);\r |
| 4212 | sum = acu - temp;\r |
| 4213 | AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 4214 | break;\r |
| 4215 | \r |
| 4216 | case 0x94: /* SUB IXH */\r |
| 4217 | SETFLAG(C, 0);/* fall through, a bit less efficient but smaller code */\r |
| 4218 | \r |
| 4219 | case 0x9c: /* SBC A,IXH */\r |
| 4220 | tStates += 9;\r |
| 4221 | sim_brk_pend[0] = FALSE;\r |
| 4222 | temp = HIGH_REGISTER(IX);\r |
| 4223 | acu = HIGH_REGISTER(AF);\r |
| 4224 | sum = acu - temp - TSTFLAG(C);\r |
| 4225 | AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 4226 | break;\r |
| 4227 | \r |
| 4228 | case 0x95: /* SUB IXL */\r |
| 4229 | SETFLAG(C, 0);/* fall through, a bit less efficient but smaller code */\r |
| 4230 | \r |
| 4231 | case 0x9d: /* SBC A,IXL */\r |
| 4232 | tStates += 9;\r |
| 4233 | sim_brk_pend[0] = FALSE;\r |
| 4234 | temp = LOW_REGISTER(IX);\r |
| 4235 | acu = HIGH_REGISTER(AF);\r |
| 4236 | sum = acu - temp - TSTFLAG(C);\r |
| 4237 | AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 4238 | break;\r |
| 4239 | \r |
| 4240 | case 0x9e: /* SBC A,(IX+dd) */\r |
| 4241 | tStates += 19;\r |
| 4242 | adr = IX + (int8) RAM_PP(PC);\r |
| 4243 | CHECK_BREAK_BYTE(adr);\r |
| 4244 | temp = GetBYTE(adr);\r |
| 4245 | acu = HIGH_REGISTER(AF);\r |
| 4246 | sum = acu - temp - TSTFLAG(C);\r |
| 4247 | AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 4248 | break;\r |
| 4249 | \r |
| 4250 | case 0xa4: /* AND IXH */\r |
| 4251 | tStates += 9;\r |
| 4252 | sim_brk_pend[0] = FALSE;\r |
| 4253 | AF = andTable[((AF & IX) >> 8) & 0xff];\r |
| 4254 | break;\r |
| 4255 | \r |
| 4256 | case 0xa5: /* AND IXL */\r |
| 4257 | tStates += 9;\r |
| 4258 | sim_brk_pend[0] = FALSE;\r |
| 4259 | AF = andTable[((AF >> 8) & IX) & 0xff];\r |
| 4260 | break;\r |
| 4261 | \r |
| 4262 | case 0xa6: /* AND (IX+dd) */\r |
| 4263 | tStates += 19;\r |
| 4264 | adr = IX + (int8) RAM_PP(PC);\r |
| 4265 | CHECK_BREAK_BYTE(adr);\r |
| 4266 | AF = andTable[((AF >> 8) & GetBYTE(adr)) & 0xff];\r |
| 4267 | break;\r |
| 4268 | \r |
| 4269 | case 0xac: /* XOR IXH */\r |
| 4270 | tStates += 9;\r |
| 4271 | sim_brk_pend[0] = FALSE;\r |
| 4272 | AF = xororTable[((AF ^ IX) >> 8) & 0xff];\r |
| 4273 | break;\r |
| 4274 | \r |
| 4275 | case 0xad: /* XOR IXL */\r |
| 4276 | tStates += 9;\r |
| 4277 | sim_brk_pend[0] = FALSE;\r |
| 4278 | AF = xororTable[((AF >> 8) ^ IX) & 0xff];\r |
| 4279 | break;\r |
| 4280 | \r |
| 4281 | case 0xae: /* XOR (IX+dd) */\r |
| 4282 | tStates += 19;\r |
| 4283 | adr = IX + (int8) RAM_PP(PC);\r |
| 4284 | CHECK_BREAK_BYTE(adr);\r |
| 4285 | AF = xororTable[((AF >> 8) ^ GetBYTE(adr)) & 0xff];\r |
| 4286 | break;\r |
| 4287 | \r |
| 4288 | case 0xb4: /* OR IXH */\r |
| 4289 | tStates += 9;\r |
| 4290 | sim_brk_pend[0] = FALSE;\r |
| 4291 | AF = xororTable[((AF | IX) >> 8) & 0xff];\r |
| 4292 | break;\r |
| 4293 | \r |
| 4294 | case 0xb5: /* OR IXL */\r |
| 4295 | tStates += 9;\r |
| 4296 | sim_brk_pend[0] = FALSE;\r |
| 4297 | AF = xororTable[((AF >> 8) | IX) & 0xff];\r |
| 4298 | break;\r |
| 4299 | \r |
| 4300 | case 0xb6: /* OR (IX+dd) */\r |
| 4301 | tStates += 19;\r |
| 4302 | adr = IX + (int8) RAM_PP(PC);\r |
| 4303 | CHECK_BREAK_BYTE(adr);\r |
| 4304 | AF = xororTable[((AF >> 8) | GetBYTE(adr)) & 0xff];\r |
| 4305 | break;\r |
| 4306 | \r |
| 4307 | case 0xbc: /* CP IXH */\r |
| 4308 | tStates += 9;\r |
| 4309 | sim_brk_pend[0] = FALSE;\r |
| 4310 | temp = HIGH_REGISTER(IX);\r |
| 4311 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 4312 | acu = HIGH_REGISTER(AF);\r |
| 4313 | sum = acu - temp;\r |
| 4314 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 4315 | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 4316 | break;\r |
| 4317 | \r |
| 4318 | case 0xbd: /* CP IXL */\r |
| 4319 | tStates += 9;\r |
| 4320 | sim_brk_pend[0] = FALSE;\r |
| 4321 | temp = LOW_REGISTER(IX);\r |
| 4322 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 4323 | acu = HIGH_REGISTER(AF);\r |
| 4324 | sum = acu - temp;\r |
| 4325 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 4326 | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 4327 | break;\r |
| 4328 | \r |
| 4329 | case 0xbe: /* CP (IX+dd) */\r |
| 4330 | tStates += 19;\r |
| 4331 | adr = IX + (int8) RAM_PP(PC);\r |
| 4332 | CHECK_BREAK_BYTE(adr);\r |
| 4333 | temp = GetBYTE(adr);\r |
| 4334 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 4335 | acu = HIGH_REGISTER(AF);\r |
| 4336 | sum = acu - temp;\r |
| 4337 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 4338 | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 4339 | break;\r |
| 4340 | \r |
| 4341 | case 0xcb: /* CB prefix */\r |
| 4342 | adr = IX + (int8) RAM_PP(PC);\r |
| 4343 | switch ((op = GetBYTE(PC)) & 7) {\r |
| 4344 | \r |
| 4345 | case 0:\r |
| 4346 | sim_brk_pend[0] = FALSE;\r |
| 4347 | ++PC;\r |
| 4348 | acu = HIGH_REGISTER(BC);\r |
| 4349 | break;\r |
| 4350 | \r |
| 4351 | case 1:\r |
| 4352 | sim_brk_pend[0] = FALSE;\r |
| 4353 | ++PC;\r |
| 4354 | acu = LOW_REGISTER(BC);\r |
| 4355 | break;\r |
| 4356 | \r |
| 4357 | case 2:\r |
| 4358 | sim_brk_pend[0] = FALSE;\r |
| 4359 | ++PC;\r |
| 4360 | acu = HIGH_REGISTER(DE);\r |
| 4361 | break;\r |
| 4362 | \r |
| 4363 | case 3:\r |
| 4364 | sim_brk_pend[0] = FALSE;\r |
| 4365 | ++PC;\r |
| 4366 | acu = LOW_REGISTER(DE);\r |
| 4367 | break;\r |
| 4368 | \r |
| 4369 | case 4:\r |
| 4370 | sim_brk_pend[0] = FALSE;\r |
| 4371 | ++PC;\r |
| 4372 | acu = HIGH_REGISTER(HL);\r |
| 4373 | break;\r |
| 4374 | \r |
| 4375 | case 5:\r |
| 4376 | sim_brk_pend[0] = FALSE;\r |
| 4377 | ++PC;\r |
| 4378 | acu = LOW_REGISTER(HL);\r |
| 4379 | break;\r |
| 4380 | \r |
| 4381 | case 6:\r |
| 4382 | CHECK_BREAK_BYTE(adr);\r |
| 4383 | ++PC;\r |
| 4384 | acu = GetBYTE(adr);\r |
| 4385 | break;\r |
| 4386 | \r |
| 4387 | case 7:\r |
| 4388 | sim_brk_pend[0] = FALSE;\r |
| 4389 | ++PC;\r |
| 4390 | acu = HIGH_REGISTER(AF);\r |
| 4391 | break;\r |
| 4392 | }\r |
| 4393 | switch (op & 0xc0) {\r |
| 4394 | \r |
| 4395 | case 0x00: /* shift/rotate */\r |
| 4396 | tStates += 23;\r |
| 4397 | switch (op & 0x38) {\r |
| 4398 | \r |
| 4399 | case 0x00: /* RLC */\r |
| 4400 | temp = (acu << 1) | (acu >> 7);\r |
| 4401 | cbits = temp & 1;\r |
| 4402 | goto cbshflg2;\r |
| 4403 | \r |
| 4404 | case 0x08: /* RRC */\r |
| 4405 | temp = (acu >> 1) | (acu << 7);\r |
| 4406 | cbits = temp & 0x80;\r |
| 4407 | goto cbshflg2;\r |
| 4408 | \r |
| 4409 | case 0x10: /* RL */\r |
| 4410 | temp = (acu << 1) | TSTFLAG(C);\r |
| 4411 | cbits = acu & 0x80;\r |
| 4412 | goto cbshflg2;\r |
| 4413 | \r |
| 4414 | case 0x18: /* RR */\r |
| 4415 | temp = (acu >> 1) | (TSTFLAG(C) << 7);\r |
| 4416 | cbits = acu & 1;\r |
| 4417 | goto cbshflg2;\r |
| 4418 | \r |
| 4419 | case 0x20: /* SLA */\r |
| 4420 | temp = acu << 1;\r |
| 4421 | cbits = acu & 0x80;\r |
| 4422 | goto cbshflg2;\r |
| 4423 | \r |
| 4424 | case 0x28: /* SRA */\r |
| 4425 | temp = (acu >> 1) | (acu & 0x80);\r |
| 4426 | cbits = acu & 1;\r |
| 4427 | goto cbshflg2;\r |
| 4428 | \r |
| 4429 | case 0x30: /* SLIA */\r |
| 4430 | temp = (acu << 1) | 1;\r |
| 4431 | cbits = acu & 0x80;\r |
| 4432 | goto cbshflg2;\r |
| 4433 | \r |
| 4434 | case 0x38: /* SRL */\r |
| 4435 | temp = acu >> 1;\r |
| 4436 | cbits = acu & 1;\r |
| 4437 | cbshflg2:\r |
| 4438 | AF = (AF & ~0xff) | rotateShiftTable[temp & 0xff] | !!cbits;\r |
| 4439 | /* !!cbits == 0 if cbits == 0 !!cbits == 1 if cbits > 0 */\r |
| 4440 | }\r |
| 4441 | break;\r |
| 4442 | \r |
| 4443 | case 0x40: /* BIT */\r |
| 4444 | tStates += 20;\r |
| 4445 | if (acu & (1 << ((op >> 3) & 7)))\r |
| 4446 | AF = (AF & ~0xfe) | 0x10 | (((op & 0x38) == 0x38) << 7);\r |
| 4447 | else AF = (AF & ~0xfe) | 0x54;\r |
| 4448 | if ((op & 7) != 6) AF |= (acu & 0x28);\r |
| 4449 | temp = acu;\r |
| 4450 | break;\r |
| 4451 | \r |
| 4452 | case 0x80: /* RES */\r |
| 4453 | tStates += 23;\r |
| 4454 | temp = acu & ~(1 << ((op >> 3) & 7));\r |
| 4455 | break;\r |
| 4456 | \r |
| 4457 | case 0xc0: /* SET */\r |
| 4458 | tStates += 23;\r |
| 4459 | temp = acu | (1 << ((op >> 3) & 7));\r |
| 4460 | break;\r |
| 4461 | }\r |
| 4462 | switch (op & 7) {\r |
| 4463 | \r |
| 4464 | case 0:\r |
| 4465 | SET_HIGH_REGISTER(BC, temp);\r |
| 4466 | break;\r |
| 4467 | \r |
| 4468 | case 1:\r |
| 4469 | SET_LOW_REGISTER(BC, temp);\r |
| 4470 | break;\r |
| 4471 | \r |
| 4472 | case 2:\r |
| 4473 | SET_HIGH_REGISTER(DE, temp);\r |
| 4474 | break;\r |
| 4475 | \r |
| 4476 | case 3:\r |
| 4477 | SET_LOW_REGISTER(DE, temp);\r |
| 4478 | break;\r |
| 4479 | \r |
| 4480 | case 4:\r |
| 4481 | SET_HIGH_REGISTER(HL, temp);\r |
| 4482 | break;\r |
| 4483 | \r |
| 4484 | case 5:\r |
| 4485 | SET_LOW_REGISTER(HL, temp);\r |
| 4486 | break;\r |
| 4487 | \r |
| 4488 | case 6:\r |
| 4489 | PutBYTE(adr, temp);\r |
| 4490 | break;\r |
| 4491 | \r |
| 4492 | case 7:\r |
| 4493 | SET_HIGH_REGISTER(AF, temp);\r |
| 4494 | break;\r |
| 4495 | }\r |
| 4496 | break;\r |
| 4497 | \r |
| 4498 | case 0xe1: /* POP IX */\r |
| 4499 | tStates += 14;\r |
| 4500 | CHECK_BREAK_WORD(SP);\r |
| 4501 | POP(IX);\r |
| 4502 | break;\r |
| 4503 | \r |
| 4504 | case 0xe3: /* EX (SP),IX */\r |
| 4505 | tStates += 23;\r |
| 4506 | CHECK_BREAK_WORD(SP);\r |
| 4507 | temp = IX;\r |
| 4508 | POP(IX);\r |
| 4509 | PUSH(temp);\r |
| 4510 | break;\r |
| 4511 | \r |
| 4512 | case 0xe5: /* PUSH IX */\r |
| 4513 | tStates += 15;\r |
| 4514 | CHECK_BREAK_WORD(SP - 2);\r |
| 4515 | PUSH(IX);\r |
| 4516 | break;\r |
| 4517 | \r |
| 4518 | case 0xe9: /* JP (IX) */\r |
| 4519 | tStates += 8;\r |
| 4520 | sim_brk_pend[0] = FALSE;\r |
| 4521 | PCQ_ENTRY(PCX);\r |
| 4522 | PC = IX;\r |
| 4523 | break;\r |
| 4524 | \r |
| 4525 | case 0xf9: /* LD SP,IX */\r |
| 4526 | tStates += 10;\r |
| 4527 | sim_brk_pend[0] = FALSE;\r |
| 4528 | SP = IX;\r |
| 4529 | break;\r |
| 4530 | \r |
| 4531 | default: /* ignore DD */\r |
| 4532 | sim_brk_pend[0] = FALSE;\r |
| 4533 | CHECK_CPU_Z80;\r |
| 4534 | PC--;\r |
| 4535 | }\r |
| 4536 | break;\r |
| 4537 | \r |
| 4538 | case 0xde: /* SBC A,nn */\r |
| 4539 | tStates += 7;\r |
| 4540 | sim_brk_pend[0] = FALSE;\r |
| 4541 | temp = RAM_PP(PC);\r |
| 4542 | acu = HIGH_REGISTER(AF);\r |
| 4543 | sum = acu - temp - TSTFLAG(C);\r |
| 4544 | cbits = acu ^ temp ^ sum;\r |
| 4545 | AF = subTable[sum & 0xff] | cbitsTable[cbits & 0x1ff] | (SET_PV);\r |
| 4546 | break;\r |
| 4547 | \r |
| 4548 | case 0xdf: /* RST 18H */\r |
| 4549 | tStates += 11;\r |
| 4550 | CHECK_BREAK_WORD(SP - 2);\r |
| 4551 | PUSH(PC);\r |
| 4552 | PCQ_ENTRY(PCX);\r |
| 4553 | PC = 0x18;\r |
| 4554 | break;\r |
| 4555 | \r |
| 4556 | case 0xe0: /* RET PO */\r |
| 4557 | if (TSTFLAG(P)) {\r |
| 4558 | sim_brk_pend[0] = FALSE;\r |
| 4559 | tStates += 5;\r |
| 4560 | }\r |
| 4561 | else {\r |
| 4562 | CHECK_BREAK_WORD(SP);\r |
| 4563 | PCQ_ENTRY(PCX);\r |
| 4564 | POP(PC);\r |
| 4565 | tStates += 11;\r |
| 4566 | }\r |
| 4567 | break;\r |
| 4568 | \r |
| 4569 | case 0xe1: /* POP HL */\r |
| 4570 | tStates += 10;\r |
| 4571 | CHECK_BREAK_WORD(SP);\r |
| 4572 | POP(HL);\r |
| 4573 | break;\r |
| 4574 | \r |
| 4575 | case 0xe2: /* JP PO,nnnn */\r |
| 4576 | sim_brk_pend[0] = FALSE;\r |
| 4577 | JPC(!TSTFLAG(P)); /* also updates tStates */\r |
| 4578 | break;\r |
| 4579 | \r |
| 4580 | case 0xe3: /* EX (SP),HL */\r |
| 4581 | tStates += 19;\r |
| 4582 | CHECK_BREAK_WORD(SP);\r |
| 4583 | temp = HL;\r |
| 4584 | POP(HL);\r |
| 4585 | PUSH(temp);\r |
| 4586 | break;\r |
| 4587 | \r |
| 4588 | case 0xe4: /* CALL PO,nnnn */\r |
| 4589 | CALLC(!TSTFLAG(P)); /* also updates tStates */\r |
| 4590 | break;\r |
| 4591 | \r |
| 4592 | case 0xe5: /* PUSH HL */\r |
| 4593 | tStates += 11;\r |
| 4594 | CHECK_BREAK_WORD(SP - 2);\r |
| 4595 | PUSH(HL);\r |
| 4596 | break;\r |
| 4597 | \r |
| 4598 | case 0xe6: /* AND nn */\r |
| 4599 | tStates += 7;\r |
| 4600 | sim_brk_pend[0] = FALSE;\r |
| 4601 | AF = andTable[((AF >> 8) & RAM_PP(PC)) & 0xff];\r |
| 4602 | break;\r |
| 4603 | \r |
| 4604 | case 0xe7: /* RST 20H */\r |
| 4605 | tStates += 11;\r |
| 4606 | CHECK_BREAK_WORD(SP - 2);\r |
| 4607 | PUSH(PC);\r |
| 4608 | PCQ_ENTRY(PCX);\r |
| 4609 | PC = 0x20;\r |
| 4610 | break;\r |
| 4611 | \r |
| 4612 | case 0xe8: /* RET PE */\r |
| 4613 | if (TSTFLAG(P)) {\r |
| 4614 | CHECK_BREAK_WORD(SP);\r |
| 4615 | PCQ_ENTRY(PCX);\r |
| 4616 | POP(PC);\r |
| 4617 | tStates += 11;\r |
| 4618 | }\r |
| 4619 | else {\r |
| 4620 | sim_brk_pend[0] = FALSE;\r |
| 4621 | tStates += 5;\r |
| 4622 | }\r |
| 4623 | break;\r |
| 4624 | \r |
| 4625 | case 0xe9: /* JP (HL) */\r |
| 4626 | tStates += 4;\r |
| 4627 | sim_brk_pend[0] = FALSE;\r |
| 4628 | PCQ_ENTRY(PCX);\r |
| 4629 | PC = HL;\r |
| 4630 | break;\r |
| 4631 | \r |
| 4632 | case 0xea: /* JP PE,nnnn */\r |
| 4633 | sim_brk_pend[0] = FALSE;\r |
| 4634 | JPC(TSTFLAG(P)); /* also updates tStates */\r |
| 4635 | break;\r |
| 4636 | \r |
| 4637 | case 0xeb: /* EX DE,HL */\r |
| 4638 | tStates += 4;\r |
| 4639 | sim_brk_pend[0] = FALSE;\r |
| 4640 | temp = HL;\r |
| 4641 | HL = DE;\r |
| 4642 | DE = temp;\r |
| 4643 | break;\r |
| 4644 | \r |
| 4645 | case 0xec: /* CALL PE,nnnn */\r |
| 4646 | CALLC(TSTFLAG(P)); /* also updates tStates */\r |
| 4647 | break;\r |
| 4648 | \r |
| 4649 | case 0xed: /* ED prefix */\r |
| 4650 | CHECK_CPU_8080;\r |
| 4651 | switch (op = RAM_PP(PC)) {\r |
| 4652 | \r |
| 4653 | case 0x40: /* IN B,(C) */\r |
| 4654 | tStates += 12;\r |
| 4655 | sim_brk_pend[0] = FALSE;\r |
| 4656 | temp = in(LOW_REGISTER(BC));\r |
| 4657 | SET_HIGH_REGISTER(BC, temp);\r |
| 4658 | AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];\r |
| 4659 | break;\r |
| 4660 | \r |
| 4661 | case 0x41: /* OUT (C),B */\r |
| 4662 | tStates += 12;\r |
| 4663 | sim_brk_pend[0] = FALSE;\r |
| 4664 | out(LOW_REGISTER(BC), HIGH_REGISTER(BC));\r |
| 4665 | break;\r |
| 4666 | \r |
| 4667 | case 0x42: /* SBC HL,BC */\r |
| 4668 | tStates += 15;\r |
| 4669 | sim_brk_pend[0] = FALSE;\r |
| 4670 | HL &= ADDRMASK;\r |
| 4671 | BC &= ADDRMASK;\r |
| 4672 | sum = HL - BC - TSTFLAG(C);\r |
| 4673 | AF = (AF & ~0xff) | ((sum >> 8) & 0xa8) | (((sum & ADDRMASK) == 0) << 6) |\r |
| 4674 | cbits2Z80Table[((HL ^ BC ^ sum) >> 8) & 0x1ff];\r |
| 4675 | HL = sum;\r |
| 4676 | break;\r |
| 4677 | \r |
| 4678 | case 0x43: /* LD (nnnn),BC */\r |
| 4679 | tStates += 20;\r |
| 4680 | temp = GET_WORD(PC);\r |
| 4681 | CHECK_BREAK_WORD(temp);\r |
| 4682 | PutWORD(temp, BC);\r |
| 4683 | PC += 2;\r |
| 4684 | break;\r |
| 4685 | \r |
| 4686 | case 0x44: /* NEG */\r |
| 4687 | \r |
| 4688 | case 0x4C: /* NEG, unofficial */\r |
| 4689 | \r |
| 4690 | case 0x54: /* NEG, unofficial */\r |
| 4691 | \r |
| 4692 | case 0x5C: /* NEG, unofficial */\r |
| 4693 | \r |
| 4694 | case 0x64: /* NEG, unofficial */\r |
| 4695 | \r |
| 4696 | case 0x6C: /* NEG, unofficial */\r |
| 4697 | \r |
| 4698 | case 0x74: /* NEG, unofficial */\r |
| 4699 | \r |
| 4700 | case 0x7C: /* NEG, unofficial */\r |
| 4701 | tStates += 8;\r |
| 4702 | sim_brk_pend[0] = FALSE;\r |
| 4703 | temp = HIGH_REGISTER(AF);\r |
| 4704 | AF = ((~(AF & 0xff00) + 1) & 0xff00); /* AF = (-(AF & 0xff00) & 0xff00); */\r |
| 4705 | AF |= ((AF >> 8) & 0xa8) | (((AF & 0xff00) == 0) << 6) | negTable[temp];\r |
| 4706 | break;\r |
| 4707 | \r |
| 4708 | case 0x45: /* RETN */\r |
| 4709 | \r |
| 4710 | case 0x55: /* RETN, unofficial */\r |
| 4711 | \r |
| 4712 | case 0x5D: /* RETN, unofficial */\r |
| 4713 | \r |
| 4714 | case 0x65: /* RETN, unofficial */\r |
| 4715 | \r |
| 4716 | case 0x6D: /* RETN, unofficial */\r |
| 4717 | \r |
| 4718 | case 0x75: /* RETN, unofficial */\r |
| 4719 | \r |
| 4720 | case 0x7D: /* RETN, unofficial */\r |
| 4721 | tStates += 14;\r |
| 4722 | IFF_S |= IFF_S >> 1;\r |
| 4723 | CHECK_BREAK_WORD(SP);\r |
| 4724 | PCQ_ENTRY(PCX);\r |
| 4725 | POP(PC);\r |
| 4726 | break;\r |
| 4727 | \r |
| 4728 | case 0x46: /* IM 0 */\r |
| 4729 | tStates += 8;\r |
| 4730 | sim_brk_pend[0] = FALSE;\r |
| 4731 | /* interrupt mode 0 */\r |
| 4732 | break;\r |
| 4733 | \r |
| 4734 | case 0x47: /* LD I,A */\r |
| 4735 | tStates += 9;\r |
| 4736 | sim_brk_pend[0] = FALSE;\r |
| 4737 | IR_S = (IR_S & 0xff) | (AF & ~0xff);\r |
| 4738 | break;\r |
| 4739 | \r |
| 4740 | case 0x48: /* IN C,(C) */\r |
| 4741 | tStates += 12;\r |
| 4742 | sim_brk_pend[0] = FALSE;\r |
| 4743 | temp = in(LOW_REGISTER(BC));\r |
| 4744 | SET_LOW_REGISTER(BC, temp);\r |
| 4745 | AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];\r |
| 4746 | break;\r |
| 4747 | \r |
| 4748 | case 0x49: /* OUT (C),C */\r |
| 4749 | tStates += 12;\r |
| 4750 | sim_brk_pend[0] = FALSE;\r |
| 4751 | out(LOW_REGISTER(BC), LOW_REGISTER(BC));\r |
| 4752 | break;\r |
| 4753 | \r |
| 4754 | case 0x4a: /* ADC HL,BC */\r |
| 4755 | tStates += 15;\r |
| 4756 | sim_brk_pend[0] = FALSE;\r |
| 4757 | HL &= ADDRMASK;\r |
| 4758 | BC &= ADDRMASK;\r |
| 4759 | sum = HL + BC + TSTFLAG(C);\r |
| 4760 | AF = (AF & ~0xff) | ((sum >> 8) & 0xa8) | (((sum & ADDRMASK) == 0) << 6) |\r |
| 4761 | cbitsZ80Table[(HL ^ BC ^ sum) >> 8];\r |
| 4762 | HL = sum;\r |
| 4763 | break;\r |
| 4764 | \r |
| 4765 | case 0x4b: /* LD BC,(nnnn) */\r |
| 4766 | tStates += 20;\r |
| 4767 | temp = GET_WORD(PC);\r |
| 4768 | CHECK_BREAK_WORD(temp);\r |
| 4769 | BC = GET_WORD(temp);\r |
| 4770 | PC += 2;\r |
| 4771 | break;\r |
| 4772 | \r |
| 4773 | case 0x4d: /* RETI */\r |
| 4774 | tStates += 14;\r |
| 4775 | IFF_S |= IFF_S >> 1;\r |
| 4776 | CHECK_BREAK_WORD(SP);\r |
| 4777 | PCQ_ENTRY(PCX);\r |
| 4778 | POP(PC);\r |
| 4779 | break;\r |
| 4780 | \r |
| 4781 | case 0x4f: /* LD R,A */\r |
| 4782 | tStates += 9;\r |
| 4783 | sim_brk_pend[0] = FALSE;\r |
| 4784 | IR_S = (IR_S & ~0xff) | ((AF >> 8) & 0xff);\r |
| 4785 | break;\r |
| 4786 | \r |
| 4787 | case 0x50: /* IN D,(C) */\r |
| 4788 | tStates += 12;\r |
| 4789 | sim_brk_pend[0] = FALSE;\r |
| 4790 | temp = in(LOW_REGISTER(BC));\r |
| 4791 | SET_HIGH_REGISTER(DE, temp);\r |
| 4792 | AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];\r |
| 4793 | break;\r |
| 4794 | \r |
| 4795 | case 0x51: /* OUT (C),D */\r |
| 4796 | tStates += 12;\r |
| 4797 | sim_brk_pend[0] = FALSE;\r |
| 4798 | out(LOW_REGISTER(BC), HIGH_REGISTER(DE));\r |
| 4799 | break;\r |
| 4800 | \r |
| 4801 | case 0x52: /* SBC HL,DE */\r |
| 4802 | tStates += 15;\r |
| 4803 | sim_brk_pend[0] = FALSE;\r |
| 4804 | HL &= ADDRMASK;\r |
| 4805 | DE &= ADDRMASK;\r |
| 4806 | sum = HL - DE - TSTFLAG(C);\r |
| 4807 | AF = (AF & ~0xff) | ((sum >> 8) & 0xa8) | (((sum & ADDRMASK) == 0) << 6) |\r |
| 4808 | cbits2Z80Table[((HL ^ DE ^ sum) >> 8) & 0x1ff];\r |
| 4809 | HL = sum;\r |
| 4810 | break;\r |
| 4811 | \r |
| 4812 | case 0x53: /* LD (nnnn),DE */\r |
| 4813 | tStates += 20;\r |
| 4814 | temp = GET_WORD(PC);\r |
| 4815 | CHECK_BREAK_WORD(temp);\r |
| 4816 | PutWORD(temp, DE);\r |
| 4817 | PC += 2;\r |
| 4818 | break;\r |
| 4819 | \r |
| 4820 | case 0x56: /* IM 1 */\r |
| 4821 | tStates += 8;\r |
| 4822 | sim_brk_pend[0] = FALSE;\r |
| 4823 | /* interrupt mode 1 */\r |
| 4824 | break;\r |
| 4825 | \r |
| 4826 | case 0x57: /* LD A,I */\r |
| 4827 | tStates += 9;\r |
| 4828 | sim_brk_pend[0] = FALSE;\r |
| 4829 | AF = (AF & 0x29) | (IR_S & ~0xff) | ((IR_S >> 8) & 0x80) | (((IR_S & ~0xff) == 0) << 6) | ((IFF_S & 2) << 1);\r |
| 4830 | break;\r |
| 4831 | \r |
| 4832 | case 0x58: /* IN E,(C) */\r |
| 4833 | tStates += 12;\r |
| 4834 | sim_brk_pend[0] = FALSE;\r |
| 4835 | temp = in(LOW_REGISTER(BC));\r |
| 4836 | SET_LOW_REGISTER(DE, temp);\r |
| 4837 | AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];\r |
| 4838 | break;\r |
| 4839 | \r |
| 4840 | case 0x59: /* OUT (C),E */\r |
| 4841 | tStates += 12;\r |
| 4842 | sim_brk_pend[0] = FALSE;\r |
| 4843 | out(LOW_REGISTER(BC), LOW_REGISTER(DE));\r |
| 4844 | break;\r |
| 4845 | \r |
| 4846 | case 0x5a: /* ADC HL,DE */\r |
| 4847 | tStates += 15;\r |
| 4848 | sim_brk_pend[0] = FALSE;\r |
| 4849 | HL &= ADDRMASK;\r |
| 4850 | DE &= ADDRMASK;\r |
| 4851 | sum = HL + DE + TSTFLAG(C);\r |
| 4852 | AF = (AF & ~0xff) | ((sum >> 8) & 0xa8) | (((sum & ADDRMASK) == 0) << 6) |\r |
| 4853 | cbitsZ80Table[(HL ^ DE ^ sum) >> 8];\r |
| 4854 | HL = sum;\r |
| 4855 | break;\r |
| 4856 | \r |
| 4857 | case 0x5b: /* LD DE,(nnnn) */\r |
| 4858 | tStates += 20;\r |
| 4859 | temp = GET_WORD(PC);\r |
| 4860 | CHECK_BREAK_WORD(temp);\r |
| 4861 | DE = GET_WORD(temp);\r |
| 4862 | PC += 2;\r |
| 4863 | break;\r |
| 4864 | \r |
| 4865 | case 0x5e: /* IM 2 */\r |
| 4866 | tStates += 8;\r |
| 4867 | sim_brk_pend[0] = FALSE;\r |
| 4868 | /* interrupt mode 2 */\r |
| 4869 | break;\r |
| 4870 | \r |
| 4871 | case 0x5f: /* LD A,R */\r |
| 4872 | tStates += 9;\r |
| 4873 | sim_brk_pend[0] = FALSE;\r |
| 4874 | AF = (AF & 0x29) | ((IR_S & 0xff) << 8) | (IR_S & 0x80) |\r |
| 4875 | (((IR_S & 0xff) == 0) << 6) | ((IFF_S & 2) << 1);\r |
| 4876 | break;\r |
| 4877 | \r |
| 4878 | case 0x60: /* IN H,(C) */\r |
| 4879 | tStates += 12;\r |
| 4880 | sim_brk_pend[0] = FALSE;\r |
| 4881 | temp = in(LOW_REGISTER(BC));\r |
| 4882 | SET_HIGH_REGISTER(HL, temp);\r |
| 4883 | AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];\r |
| 4884 | break;\r |
| 4885 | \r |
| 4886 | case 0x61: /* OUT (C),H */\r |
| 4887 | tStates += 12;\r |
| 4888 | sim_brk_pend[0] = FALSE;\r |
| 4889 | out(LOW_REGISTER(BC), HIGH_REGISTER(HL));\r |
| 4890 | break;\r |
| 4891 | \r |
| 4892 | case 0x62: /* SBC HL,HL */\r |
| 4893 | tStates += 15;\r |
| 4894 | sim_brk_pend[0] = FALSE;\r |
| 4895 | HL &= ADDRMASK;\r |
| 4896 | sum = HL - HL - TSTFLAG(C);\r |
| 4897 | AF = (AF & ~0xff) | (((sum & ADDRMASK) == 0) << 6) |\r |
| 4898 | cbits2Z80DupTable[(sum >> 8) & 0x1ff];\r |
| 4899 | HL = sum;\r |
| 4900 | break;\r |
| 4901 | \r |
| 4902 | case 0x63: /* LD (nnnn),HL */\r |
| 4903 | tStates += 20;\r |
| 4904 | temp = GET_WORD(PC);\r |
| 4905 | CHECK_BREAK_WORD(temp);\r |
| 4906 | PutWORD(temp, HL);\r |
| 4907 | PC += 2;\r |
| 4908 | break;\r |
| 4909 | \r |
| 4910 | case 0x67: /* RRD */\r |
| 4911 | tStates += 18;\r |
| 4912 | sim_brk_pend[0] = FALSE;\r |
| 4913 | temp = GetBYTE(HL);\r |
| 4914 | acu = HIGH_REGISTER(AF);\r |
| 4915 | PutBYTE(HL, HIGH_DIGIT(temp) | (LOW_DIGIT(acu) << 4));\r |
| 4916 | AF = rrdrldTable[(acu & 0xf0) | LOW_DIGIT(temp)] | (AF & 1);\r |
| 4917 | break;\r |
| 4918 | \r |
| 4919 | case 0x68: /* IN L,(C) */\r |
| 4920 | tStates += 12;\r |
| 4921 | sim_brk_pend[0] = FALSE;\r |
| 4922 | temp = in(LOW_REGISTER(BC));\r |
| 4923 | SET_LOW_REGISTER(HL, temp);\r |
| 4924 | AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];\r |
| 4925 | break;\r |
| 4926 | \r |
| 4927 | case 0x69: /* OUT (C),L */\r |
| 4928 | tStates += 12;\r |
| 4929 | sim_brk_pend[0] = FALSE;\r |
| 4930 | out(LOW_REGISTER(BC), LOW_REGISTER(HL));\r |
| 4931 | break;\r |
| 4932 | \r |
| 4933 | case 0x6a: /* ADC HL,HL */\r |
| 4934 | tStates += 15;\r |
| 4935 | sim_brk_pend[0] = FALSE;\r |
| 4936 | HL &= ADDRMASK;\r |
| 4937 | sum = HL + HL + TSTFLAG(C);\r |
| 4938 | AF = (AF & ~0xff) | (((sum & ADDRMASK) == 0) << 6) |\r |
| 4939 | cbitsZ80DupTable[sum >> 8];\r |
| 4940 | HL = sum;\r |
| 4941 | break;\r |
| 4942 | \r |
| 4943 | case 0x6b: /* LD HL,(nnnn) */\r |
| 4944 | tStates += 20;\r |
| 4945 | temp = GET_WORD(PC);\r |
| 4946 | CHECK_BREAK_WORD(temp);\r |
| 4947 | HL = GET_WORD(temp);\r |
| 4948 | PC += 2;\r |
| 4949 | break;\r |
| 4950 | \r |
| 4951 | case 0x6f: /* RLD */\r |
| 4952 | tStates += 18;\r |
| 4953 | sim_brk_pend[0] = FALSE;\r |
| 4954 | temp = GetBYTE(HL);\r |
| 4955 | acu = HIGH_REGISTER(AF);\r |
| 4956 | PutBYTE(HL, (LOW_DIGIT(temp) << 4) | LOW_DIGIT(acu));\r |
| 4957 | AF = rrdrldTable[(acu & 0xf0) | HIGH_DIGIT(temp)] | (AF & 1);\r |
| 4958 | break;\r |
| 4959 | \r |
| 4960 | case 0x70: /* IN (C) */\r |
| 4961 | tStates += 12;\r |
| 4962 | sim_brk_pend[0] = FALSE;\r |
| 4963 | temp = in(LOW_REGISTER(BC));\r |
| 4964 | SET_LOW_REGISTER(temp, temp);\r |
| 4965 | AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];\r |
| 4966 | break;\r |
| 4967 | \r |
| 4968 | case 0x71: /* OUT (C),0 */\r |
| 4969 | tStates += 12;\r |
| 4970 | sim_brk_pend[0] = FALSE;\r |
| 4971 | out(LOW_REGISTER(BC), 0);\r |
| 4972 | break;\r |
| 4973 | \r |
| 4974 | case 0x72: /* SBC HL,SP */\r |
| 4975 | tStates += 15;\r |
| 4976 | sim_brk_pend[0] = FALSE;\r |
| 4977 | HL &= ADDRMASK;\r |
| 4978 | SP &= ADDRMASK;\r |
| 4979 | sum = HL - SP - TSTFLAG(C);\r |
| 4980 | AF = (AF & ~0xff) | ((sum >> 8) & 0xa8) | (((sum & ADDRMASK) == 0) << 6) |\r |
| 4981 | cbits2Z80Table[((HL ^ SP ^ sum) >> 8) & 0x1ff];\r |
| 4982 | HL = sum;\r |
| 4983 | break;\r |
| 4984 | \r |
| 4985 | case 0x73: /* LD (nnnn),SP */\r |
| 4986 | tStates += 20;\r |
| 4987 | temp = GET_WORD(PC);\r |
| 4988 | CHECK_BREAK_WORD(temp);\r |
| 4989 | PutWORD(temp, SP);\r |
| 4990 | PC += 2;\r |
| 4991 | break;\r |
| 4992 | \r |
| 4993 | case 0x78: /* IN A,(C) */\r |
| 4994 | tStates += 12;\r |
| 4995 | sim_brk_pend[0] = FALSE;\r |
| 4996 | temp = in(LOW_REGISTER(BC));\r |
| 4997 | SET_HIGH_REGISTER(AF, temp);\r |
| 4998 | AF = (AF & ~0xfe) | rotateShiftTable[temp & 0xff];\r |
| 4999 | break;\r |
| 5000 | \r |
| 5001 | case 0x79: /* OUT (C),A */\r |
| 5002 | tStates += 12;\r |
| 5003 | sim_brk_pend[0] = FALSE;\r |
| 5004 | out(LOW_REGISTER(BC), HIGH_REGISTER(AF));\r |
| 5005 | break;\r |
| 5006 | \r |
| 5007 | case 0x7a: /* ADC HL,SP */\r |
| 5008 | tStates += 15;\r |
| 5009 | sim_brk_pend[0] = FALSE;\r |
| 5010 | HL &= ADDRMASK;\r |
| 5011 | SP &= ADDRMASK;\r |
| 5012 | sum = HL + SP + TSTFLAG(C);\r |
| 5013 | AF = (AF & ~0xff) | ((sum >> 8) & 0xa8) | (((sum & ADDRMASK) == 0) << 6) |\r |
| 5014 | cbitsZ80Table[(HL ^ SP ^ sum) >> 8];\r |
| 5015 | HL = sum;\r |
| 5016 | break;\r |
| 5017 | \r |
| 5018 | case 0x7b: /* LD SP,(nnnn) */\r |
| 5019 | tStates += 20;\r |
| 5020 | temp = GET_WORD(PC);\r |
| 5021 | CHECK_BREAK_WORD(temp);\r |
| 5022 | SP = GET_WORD(temp);\r |
| 5023 | PC += 2;\r |
| 5024 | break;\r |
| 5025 | \r |
| 5026 | case 0xa0: /* LDI */\r |
| 5027 | tStates += 16;\r |
| 5028 | CHECK_BREAK_TWO_BYTES(HL, DE);\r |
| 5029 | acu = RAM_PP(HL);\r |
| 5030 | PUT_BYTE_PP(DE, acu);\r |
| 5031 | acu += HIGH_REGISTER(AF);\r |
| 5032 | AF = (AF & ~0x3e) | (acu & 8) | ((acu & 2) << 4) |\r |
| 5033 | (((--BC & ADDRMASK) != 0) << 2);\r |
| 5034 | break;\r |
| 5035 | \r |
| 5036 | case 0xa1: /* CPI */\r |
| 5037 | tStates += 16;\r |
| 5038 | CHECK_BREAK_BYTE(HL);\r |
| 5039 | acu = HIGH_REGISTER(AF);\r |
| 5040 | temp = RAM_PP(HL);\r |
| 5041 | sum = acu - temp;\r |
| 5042 | cbits = acu ^ temp ^ sum;\r |
| 5043 | AF = (AF & ~0xfe) | (sum & 0x80) | (!(sum & 0xff) << 6) |\r |
| 5044 | (((sum - ((cbits & 16) >> 4)) & 2) << 4) | (cbits & 16) |\r |
| 5045 | ((sum - ((cbits >> 4) & 1)) & 8) |\r |
| 5046 | ((--BC & ADDRMASK) != 0) << 2 | 2;\r |
| 5047 | if ((sum & 15) == 8 && (cbits & 16) != 0) AF &= ~8;\r |
| 5048 | break;\r |
| 5049 | \r |
| 5050 | /* SF, ZF, YF, XF flags are affected by decreasing register B, as in DEC B.\r |
| 5051 | NF flag A is copy of bit 7 of the value read from or written to an I/O port.\r |
| 5052 | INI/INIR/IND/INDR use the C flag in stead of the L register. There is a\r |
| 5053 | catch though, because not the value of C is used, but C + 1 if it's INI/INIR or\r |
| 5054 | C - 1 if it's IND/INDR. So, first of all INI/INIR:\r |
| 5055 | HF and CF Both set if ((HL) + ((C + 1) & 255) > 255)\r |
| 5056 | PF The parity of (((HL) + ((C + 1) & 255)) & 7) xor B) */\r |
| 5057 | case 0xa2: /* INI */\r |
| 5058 | tStates += 16;\r |
| 5059 | CHECK_BREAK_BYTE(HL);\r |
| 5060 | acu = in(LOW_REGISTER(BC));\r |
| 5061 | PutBYTE(HL, acu);\r |
| 5062 | ++HL;\r |
| 5063 | temp = HIGH_REGISTER(BC);\r |
| 5064 | BC -= 0x100;\r |
| 5065 | INOUTFLAGS_NONZERO((LOW_REGISTER(BC) + 1) & 0xff);\r |
| 5066 | break;\r |
| 5067 | \r |
| 5068 | /* SF, ZF, YF, XF flags are affected by decreasing register B, as in DEC B.\r |
| 5069 | NF flag A is copy of bit 7 of the value read from or written to an I/O port.\r |
| 5070 | And now the for OUTI/OTIR/OUTD/OTDR instructions. Take state of the L\r |
| 5071 | after the increment or decrement of HL; add the value written to the I/O port\r |
| 5072 | to; call that k for now. If k > 255, then the CF and HF flags are set. The PF\r |
| 5073 | flags is set like the parity of k bitwise and'ed with 7, bitwise xor'ed with B.\r |
| 5074 | HF and CF Both set if ((HL) + L > 255)\r |
| 5075 | PF The parity of ((((HL) + L) & 7) xor B) */\r |
| 5076 | case 0xa3: /* OUTI */\r |
| 5077 | tStates += 16;\r |
| 5078 | CHECK_BREAK_BYTE(HL);\r |
| 5079 | acu = GetBYTE(HL);\r |
| 5080 | out(LOW_REGISTER(BC), acu);\r |
| 5081 | ++HL;\r |
| 5082 | temp = HIGH_REGISTER(BC);\r |
| 5083 | BC -= 0x100;\r |
| 5084 | INOUTFLAGS_NONZERO(LOW_REGISTER(HL));\r |
| 5085 | break;\r |
| 5086 | \r |
| 5087 | case 0xa8: /* LDD */\r |
| 5088 | tStates += 16;\r |
| 5089 | CHECK_BREAK_TWO_BYTES(HL, DE);\r |
| 5090 | acu = RAM_MM(HL);\r |
| 5091 | PUT_BYTE_MM(DE, acu);\r |
| 5092 | acu += HIGH_REGISTER(AF);\r |
| 5093 | AF = (AF & ~0x3e) | (acu & 8) | ((acu & 2) << 4) |\r |
| 5094 | (((--BC & ADDRMASK) != 0) << 2);\r |
| 5095 | break;\r |
| 5096 | \r |
| 5097 | case 0xa9: /* CPD */\r |
| 5098 | tStates += 16;\r |
| 5099 | CHECK_BREAK_BYTE(HL);\r |
| 5100 | acu = HIGH_REGISTER(AF);\r |
| 5101 | temp = RAM_MM(HL);\r |
| 5102 | sum = acu - temp;\r |
| 5103 | cbits = acu ^ temp ^ sum;\r |
| 5104 | AF = (AF & ~0xfe) | (sum & 0x80) | (!(sum & 0xff) << 6) |\r |
| 5105 | (((sum - ((cbits & 16) >> 4)) & 2) << 4) | (cbits & 16) |\r |
| 5106 | ((sum - ((cbits >> 4) & 1)) & 8) |\r |
| 5107 | ((--BC & ADDRMASK) != 0) << 2 | 2;\r |
| 5108 | if ((sum & 15) == 8 && (cbits & 16) != 0) AF &= ~8;\r |
| 5109 | break;\r |
| 5110 | \r |
| 5111 | /* SF, ZF, YF, XF flags are affected by decreasing register B, as in DEC B.\r |
| 5112 | NF flag A is copy of bit 7 of the value read from or written to an I/O port.\r |
| 5113 | INI/INIR/IND/INDR use the C flag in stead of the L register. There is a\r |
| 5114 | catch though, because not the value of C is used, but C + 1 if it's INI/INIR or\r |
| 5115 | C - 1 if it's IND/INDR. And last IND/INDR:\r |
| 5116 | HF and CF Both set if ((HL) + ((C - 1) & 255) > 255)\r |
| 5117 | PF The parity of (((HL) + ((C - 1) & 255)) & 7) xor B) */\r |
| 5118 | case 0xaa: /* IND */\r |
| 5119 | tStates += 16;\r |
| 5120 | CHECK_BREAK_BYTE(HL);\r |
| 5121 | acu = in(LOW_REGISTER(BC));\r |
| 5122 | PutBYTE(HL, acu);\r |
| 5123 | --HL;\r |
| 5124 | temp = HIGH_REGISTER(BC);\r |
| 5125 | BC -= 0x100;\r |
| 5126 | INOUTFLAGS_NONZERO((LOW_REGISTER(BC) - 1) & 0xff);\r |
| 5127 | break;\r |
| 5128 | \r |
| 5129 | case 0xab: /* OUTD */\r |
| 5130 | tStates += 16;\r |
| 5131 | CHECK_BREAK_BYTE(HL);\r |
| 5132 | acu = GetBYTE(HL);\r |
| 5133 | out(LOW_REGISTER(BC), acu);\r |
| 5134 | --HL;\r |
| 5135 | temp = HIGH_REGISTER(BC);\r |
| 5136 | BC -= 0x100;\r |
| 5137 | INOUTFLAGS_NONZERO(LOW_REGISTER(HL));\r |
| 5138 | break;\r |
| 5139 | \r |
| 5140 | case 0xb0: /* LDIR */\r |
| 5141 | tStates -= 5;\r |
| 5142 | acu = HIGH_REGISTER(AF);\r |
| 5143 | BC &= ADDRMASK;\r |
| 5144 | if (BC == 0) BC = 0x10000;\r |
| 5145 | do {\r |
| 5146 | tStates += 21;\r |
| 5147 | CHECK_BREAK_TWO_BYTES(HL, DE);\r |
| 5148 | acu = RAM_PP(HL);\r |
| 5149 | PUT_BYTE_PP(DE, acu);\r |
| 5150 | } while (--BC);\r |
| 5151 | acu += HIGH_REGISTER(AF);\r |
| 5152 | AF = (AF & ~0x3e) | (acu & 8) | ((acu & 2) << 4);\r |
| 5153 | break;\r |
| 5154 | \r |
| 5155 | case 0xb1: /* CPIR */\r |
| 5156 | tStates -= 5;\r |
| 5157 | acu = HIGH_REGISTER(AF);\r |
| 5158 | BC &= ADDRMASK;\r |
| 5159 | if (BC == 0) BC = 0x10000;\r |
| 5160 | do {\r |
| 5161 | tStates += 21;\r |
| 5162 | CHECK_BREAK_BYTE(HL);\r |
| 5163 | temp = RAM_PP(HL);\r |
| 5164 | op = --BC != 0;\r |
| 5165 | sum = acu - temp;\r |
| 5166 | } while (op && sum != 0);\r |
| 5167 | cbits = acu ^ temp ^ sum;\r |
| 5168 | AF = (AF & ~0xfe) | (sum & 0x80) | (!(sum & 0xff) << 6) |\r |
| 5169 | (((sum - ((cbits & 16) >> 4)) & 2) << 4) |\r |
| 5170 | (cbits & 16) | ((sum - ((cbits >> 4) & 1)) & 8) |\r |
| 5171 | op << 2 | 2;\r |
| 5172 | if ((sum & 15) == 8 && (cbits & 16) != 0) AF &= ~8;\r |
| 5173 | break;\r |
| 5174 | \r |
| 5175 | case 0xb2: /* INIR */\r |
| 5176 | tStates -= 5;\r |
| 5177 | temp = HIGH_REGISTER(BC);\r |
| 5178 | if (temp == 0) temp = 0x100;\r |
| 5179 | do {\r |
| 5180 | tStates += 21;\r |
| 5181 | CHECK_BREAK_BYTE(HL);\r |
| 5182 | acu = in(LOW_REGISTER(BC));\r |
| 5183 | PutBYTE(HL, acu);\r |
| 5184 | ++HL;\r |
| 5185 | } while (--temp);\r |
| 5186 | temp = HIGH_REGISTER(BC);\r |
| 5187 | SET_HIGH_REGISTER(BC, 0);\r |
| 5188 | INOUTFLAGS_ZERO((LOW_REGISTER(BC) + 1) & 0xff);\r |
| 5189 | break;\r |
| 5190 | \r |
| 5191 | case 0xb3: /* OTIR */\r |
| 5192 | tStates -= 5;\r |
| 5193 | temp = HIGH_REGISTER(BC);\r |
| 5194 | if (temp == 0) temp = 0x100;\r |
| 5195 | do {\r |
| 5196 | tStates += 21;\r |
| 5197 | CHECK_BREAK_BYTE(HL);\r |
| 5198 | acu = GetBYTE(HL);\r |
| 5199 | out(LOW_REGISTER(BC), acu);\r |
| 5200 | ++HL;\r |
| 5201 | } while (--temp);\r |
| 5202 | temp = HIGH_REGISTER(BC);\r |
| 5203 | SET_HIGH_REGISTER(BC, 0);\r |
| 5204 | INOUTFLAGS_ZERO(LOW_REGISTER(HL));\r |
| 5205 | break;\r |
| 5206 | \r |
| 5207 | case 0xb8: /* LDDR */\r |
| 5208 | tStates -= 5;\r |
| 5209 | BC &= ADDRMASK;\r |
| 5210 | if (BC == 0) BC = 0x10000;\r |
| 5211 | do {\r |
| 5212 | tStates += 21;\r |
| 5213 | CHECK_BREAK_TWO_BYTES(HL, DE);\r |
| 5214 | acu = RAM_MM(HL);\r |
| 5215 | PUT_BYTE_MM(DE, acu);\r |
| 5216 | } while (--BC);\r |
| 5217 | acu += HIGH_REGISTER(AF);\r |
| 5218 | AF = (AF & ~0x3e) | (acu & 8) | ((acu & 2) << 4);\r |
| 5219 | break;\r |
| 5220 | \r |
| 5221 | case 0xb9: /* CPDR */\r |
| 5222 | tStates -= 5;\r |
| 5223 | acu = HIGH_REGISTER(AF);\r |
| 5224 | BC &= ADDRMASK;\r |
| 5225 | if (BC == 0) BC = 0x10000;\r |
| 5226 | do {\r |
| 5227 | tStates += 21;\r |
| 5228 | CHECK_BREAK_BYTE(HL);\r |
| 5229 | temp = RAM_MM(HL);\r |
| 5230 | op = --BC != 0;\r |
| 5231 | sum = acu - temp;\r |
| 5232 | } while (op && sum != 0);\r |
| 5233 | cbits = acu ^ temp ^ sum;\r |
| 5234 | AF = (AF & ~0xfe) | (sum & 0x80) | (!(sum & 0xff) << 6) |\r |
| 5235 | (((sum - ((cbits & 16) >> 4)) & 2) << 4) |\r |
| 5236 | (cbits & 16) | ((sum - ((cbits >> 4) & 1)) & 8) |\r |
| 5237 | op << 2 | 2;\r |
| 5238 | if ((sum & 15) == 8 && (cbits & 16) != 0) AF &= ~8;\r |
| 5239 | break;\r |
| 5240 | \r |
| 5241 | case 0xba: /* INDR */\r |
| 5242 | tStates -= 5;\r |
| 5243 | temp = HIGH_REGISTER(BC);\r |
| 5244 | if (temp == 0) temp = 0x100;\r |
| 5245 | do {\r |
| 5246 | tStates += 21;\r |
| 5247 | CHECK_BREAK_BYTE(HL);\r |
| 5248 | acu = in(LOW_REGISTER(BC));\r |
| 5249 | PutBYTE(HL, acu);\r |
| 5250 | --HL;\r |
| 5251 | } while (--temp);\r |
| 5252 | temp = HIGH_REGISTER(BC);\r |
| 5253 | SET_HIGH_REGISTER(BC, 0);\r |
| 5254 | INOUTFLAGS_ZERO((LOW_REGISTER(BC) - 1) & 0xff);\r |
| 5255 | break;\r |
| 5256 | \r |
| 5257 | case 0xbb: /* OTDR */\r |
| 5258 | tStates -= 5;\r |
| 5259 | temp = HIGH_REGISTER(BC);\r |
| 5260 | if (temp == 0) temp = 0x100;\r |
| 5261 | do {\r |
| 5262 | tStates += 21;\r |
| 5263 | CHECK_BREAK_BYTE(HL);\r |
| 5264 | acu = GetBYTE(HL);\r |
| 5265 | out(LOW_REGISTER(BC), acu);\r |
| 5266 | --HL;\r |
| 5267 | } while (--temp);\r |
| 5268 | temp = HIGH_REGISTER(BC);\r |
| 5269 | SET_HIGH_REGISTER(BC, 0);\r |
| 5270 | INOUTFLAGS_ZERO(LOW_REGISTER(HL));\r |
| 5271 | break;\r |
| 5272 | \r |
| 5273 | default: /* ignore ED and following byte */\r |
| 5274 | sim_brk_pend[0] = FALSE;\r |
| 5275 | CHECK_CPU_Z80;\r |
| 5276 | }\r |
| 5277 | break;\r |
| 5278 | \r |
| 5279 | case 0xee: /* XOR nn */\r |
| 5280 | tStates += 7;\r |
| 5281 | sim_brk_pend[0] = FALSE;\r |
| 5282 | AF = xororTable[((AF >> 8) ^ RAM_PP(PC)) & 0xff];\r |
| 5283 | break;\r |
| 5284 | \r |
| 5285 | case 0xef: /* RST 28H */\r |
| 5286 | tStates += 11;\r |
| 5287 | CHECK_BREAK_WORD(SP - 2);\r |
| 5288 | PUSH(PC);\r |
| 5289 | PCQ_ENTRY(PCX);\r |
| 5290 | PC = 0x28;\r |
| 5291 | break;\r |
| 5292 | \r |
| 5293 | case 0xf0: /* RET P */\r |
| 5294 | if (TSTFLAG(S)) {\r |
| 5295 | sim_brk_pend[0] = FALSE;\r |
| 5296 | tStates += 5;\r |
| 5297 | }\r |
| 5298 | else {\r |
| 5299 | CHECK_BREAK_WORD(SP);\r |
| 5300 | PCQ_ENTRY(PCX);\r |
| 5301 | POP(PC);\r |
| 5302 | tStates += 11;\r |
| 5303 | }\r |
| 5304 | break;\r |
| 5305 | \r |
| 5306 | case 0xf1: /* POP AF */\r |
| 5307 | tStates += 10;\r |
| 5308 | CHECK_BREAK_WORD(SP);\r |
| 5309 | POP(AF);\r |
| 5310 | break;\r |
| 5311 | \r |
| 5312 | case 0xf2: /* JP P,nnnn */\r |
| 5313 | sim_brk_pend[0] = FALSE;\r |
| 5314 | JPC(!TSTFLAG(S)); /* also updates tStates */\r |
| 5315 | break;\r |
| 5316 | \r |
| 5317 | case 0xf3: /* DI */\r |
| 5318 | tStates += 4;\r |
| 5319 | sim_brk_pend[0] = FALSE;\r |
| 5320 | IFF_S = 0;\r |
| 5321 | break;\r |
| 5322 | \r |
| 5323 | case 0xf4: /* CALL P,nnnn */\r |
| 5324 | CALLC(!TSTFLAG(S)); /* also updates tStates */\r |
| 5325 | break;\r |
| 5326 | \r |
| 5327 | case 0xf5: /* PUSH AF */\r |
| 5328 | tStates += 11;\r |
| 5329 | CHECK_BREAK_WORD(SP - 2);\r |
| 5330 | PUSH(AF);\r |
| 5331 | break;\r |
| 5332 | \r |
| 5333 | case 0xf6: /* OR nn */\r |
| 5334 | tStates += 7;\r |
| 5335 | sim_brk_pend[0] = FALSE;\r |
| 5336 | AF = xororTable[((AF >> 8) | RAM_PP(PC)) & 0xff];\r |
| 5337 | break;\r |
| 5338 | \r |
| 5339 | case 0xf7: /* RST 30H */\r |
| 5340 | tStates += 11;\r |
| 5341 | CHECK_BREAK_WORD(SP - 2);\r |
| 5342 | PUSH(PC);\r |
| 5343 | PCQ_ENTRY(PCX);\r |
| 5344 | PC = 0x30;\r |
| 5345 | break;\r |
| 5346 | \r |
| 5347 | case 0xf8: /* RET M */\r |
| 5348 | if (TSTFLAG(S)) {\r |
| 5349 | CHECK_BREAK_WORD(SP);\r |
| 5350 | PCQ_ENTRY(PCX);\r |
| 5351 | POP(PC);\r |
| 5352 | tStates += 11;\r |
| 5353 | }\r |
| 5354 | else {\r |
| 5355 | sim_brk_pend[0] = FALSE;\r |
| 5356 | tStates += 5;\r |
| 5357 | }\r |
| 5358 | break;\r |
| 5359 | \r |
| 5360 | case 0xf9: /* LD SP,HL */\r |
| 5361 | tStates += 6;\r |
| 5362 | sim_brk_pend[0] = FALSE;\r |
| 5363 | SP = HL;\r |
| 5364 | break;\r |
| 5365 | \r |
| 5366 | case 0xfa: /* JP M,nnnn */\r |
| 5367 | sim_brk_pend[0] = FALSE;\r |
| 5368 | JPC(TSTFLAG(S)); /* also updates tStates */\r |
| 5369 | break;\r |
| 5370 | \r |
| 5371 | case 0xfb: /* EI */\r |
| 5372 | tStates += 4;\r |
| 5373 | sim_brk_pend[0] = FALSE;\r |
| 5374 | IFF_S = 3;\r |
| 5375 | break;\r |
| 5376 | \r |
| 5377 | case 0xfc: /* CALL M,nnnn */\r |
| 5378 | CALLC(TSTFLAG(S)); /* also updates tStates */\r |
| 5379 | break;\r |
| 5380 | \r |
| 5381 | case 0xfd: /* FD prefix */\r |
| 5382 | CHECK_CPU_8080;\r |
| 5383 | switch (op = RAM_PP(PC)) {\r |
| 5384 | \r |
| 5385 | case 0x09: /* ADD IY,BC */\r |
| 5386 | tStates += 15;\r |
| 5387 | sim_brk_pend[0] = FALSE;\r |
| 5388 | IY &= ADDRMASK;\r |
| 5389 | BC &= ADDRMASK;\r |
| 5390 | sum = IY + BC;\r |
| 5391 | AF = (AF & ~0x3b) | ((sum >> 8) & 0x28) | cbitsTable[(IY ^ BC ^ sum) >> 8];\r |
| 5392 | IY = sum;\r |
| 5393 | break;\r |
| 5394 | \r |
| 5395 | case 0x19: /* ADD IY,DE */\r |
| 5396 | tStates += 15;\r |
| 5397 | sim_brk_pend[0] = FALSE;\r |
| 5398 | IY &= ADDRMASK;\r |
| 5399 | DE &= ADDRMASK;\r |
| 5400 | sum = IY + DE;\r |
| 5401 | AF = (AF & ~0x3b) | ((sum >> 8) & 0x28) | cbitsTable[(IY ^ DE ^ sum) >> 8];\r |
| 5402 | IY = sum;\r |
| 5403 | break;\r |
| 5404 | \r |
| 5405 | case 0x21: /* LD IY,nnnn */\r |
| 5406 | tStates += 14;\r |
| 5407 | sim_brk_pend[0] = FALSE;\r |
| 5408 | IY = GET_WORD(PC);\r |
| 5409 | PC += 2;\r |
| 5410 | break;\r |
| 5411 | \r |
| 5412 | case 0x22: /* LD (nnnn),IY */\r |
| 5413 | tStates += 20;\r |
| 5414 | temp = GET_WORD(PC);\r |
| 5415 | CHECK_BREAK_WORD(temp);\r |
| 5416 | PutWORD(temp, IY);\r |
| 5417 | PC += 2;\r |
| 5418 | break;\r |
| 5419 | \r |
| 5420 | case 0x23: /* INC IY */\r |
| 5421 | tStates += 10;\r |
| 5422 | sim_brk_pend[0] = FALSE;\r |
| 5423 | ++IY;\r |
| 5424 | break;\r |
| 5425 | \r |
| 5426 | case 0x24: /* INC IYH */\r |
| 5427 | tStates += 9;\r |
| 5428 | sim_brk_pend[0] = FALSE;\r |
| 5429 | IY += 0x100;\r |
| 5430 | AF = (AF & ~0xfe) | incZ80Table[HIGH_REGISTER(IY)];\r |
| 5431 | break;\r |
| 5432 | \r |
| 5433 | case 0x25: /* DEC IYH */\r |
| 5434 | tStates += 9;\r |
| 5435 | sim_brk_pend[0] = FALSE;\r |
| 5436 | IY -= 0x100;\r |
| 5437 | AF = (AF & ~0xfe) | decZ80Table[HIGH_REGISTER(IY)];\r |
| 5438 | break;\r |
| 5439 | \r |
| 5440 | case 0x26: /* LD IYH,nn */\r |
| 5441 | tStates += 9;\r |
| 5442 | sim_brk_pend[0] = FALSE;\r |
| 5443 | SET_HIGH_REGISTER(IY, RAM_PP(PC));\r |
| 5444 | break;\r |
| 5445 | \r |
| 5446 | case 0x29: /* ADD IY,IY */\r |
| 5447 | tStates += 15;\r |
| 5448 | sim_brk_pend[0] = FALSE;\r |
| 5449 | IY &= ADDRMASK;\r |
| 5450 | sum = IY + IY;\r |
| 5451 | AF = (AF & ~0x3b) | cbitsDup16Table[sum >> 8];\r |
| 5452 | IY = sum;\r |
| 5453 | break;\r |
| 5454 | \r |
| 5455 | case 0x2a: /* LD IY,(nnnn) */\r |
| 5456 | tStates += 20;\r |
| 5457 | temp = GET_WORD(PC);\r |
| 5458 | CHECK_BREAK_WORD(temp);\r |
| 5459 | IY = GET_WORD(temp);\r |
| 5460 | PC += 2;\r |
| 5461 | break;\r |
| 5462 | \r |
| 5463 | case 0x2b: /* DEC IY */\r |
| 5464 | tStates += 10;\r |
| 5465 | sim_brk_pend[0] = FALSE;\r |
| 5466 | --IY;\r |
| 5467 | break;\r |
| 5468 | \r |
| 5469 | case 0x2c: /* INC IYL */\r |
| 5470 | tStates += 9;\r |
| 5471 | sim_brk_pend[0] = FALSE;\r |
| 5472 | temp = LOW_REGISTER(IY) + 1;\r |
| 5473 | SET_LOW_REGISTER(IY, temp);\r |
| 5474 | AF = (AF & ~0xfe) | incZ80Table[temp];\r |
| 5475 | break;\r |
| 5476 | \r |
| 5477 | case 0x2d: /* DEC IYL */\r |
| 5478 | tStates += 9;\r |
| 5479 | sim_brk_pend[0] = FALSE;\r |
| 5480 | temp = LOW_REGISTER(IY) - 1;\r |
| 5481 | SET_LOW_REGISTER(IY, temp);\r |
| 5482 | AF = (AF & ~0xfe) | decZ80Table[temp & 0xff];\r |
| 5483 | break;\r |
| 5484 | \r |
| 5485 | case 0x2e: /* LD IYL,nn */\r |
| 5486 | tStates += 9;\r |
| 5487 | sim_brk_pend[0] = FALSE;\r |
| 5488 | SET_LOW_REGISTER(IY, RAM_PP(PC));\r |
| 5489 | break;\r |
| 5490 | \r |
| 5491 | case 0x34: /* INC (IY+dd) */\r |
| 5492 | tStates += 23;\r |
| 5493 | adr = IY + (int8) RAM_PP(PC);\r |
| 5494 | CHECK_BREAK_BYTE(adr);\r |
| 5495 | temp = GetBYTE(adr) + 1;\r |
| 5496 | PutBYTE(adr, temp);\r |
| 5497 | AF = (AF & ~0xfe) | incZ80Table[temp];\r |
| 5498 | break;\r |
| 5499 | \r |
| 5500 | case 0x35: /* DEC (IY+dd) */\r |
| 5501 | tStates += 23;\r |
| 5502 | adr = IY + (int8) RAM_PP(PC);\r |
| 5503 | CHECK_BREAK_BYTE(adr);\r |
| 5504 | temp = GetBYTE(adr) - 1;\r |
| 5505 | PutBYTE(adr, temp);\r |
| 5506 | AF = (AF & ~0xfe) | decZ80Table[temp & 0xff];\r |
| 5507 | break;\r |
| 5508 | \r |
| 5509 | case 0x36: /* LD (IY+dd),nn */\r |
| 5510 | tStates += 19;\r |
| 5511 | adr = IY + (int8) RAM_PP(PC);\r |
| 5512 | CHECK_BREAK_BYTE(adr);\r |
| 5513 | PutBYTE(adr, RAM_PP(PC));\r |
| 5514 | break;\r |
| 5515 | \r |
| 5516 | case 0x39: /* ADD IY,SP */\r |
| 5517 | tStates += 15;\r |
| 5518 | sim_brk_pend[0] = FALSE;\r |
| 5519 | IY &= ADDRMASK;\r |
| 5520 | SP &= ADDRMASK;\r |
| 5521 | sum = IY + SP;\r |
| 5522 | AF = (AF & ~0x3b) | ((sum >> 8) & 0x28) | cbitsTable[(IY ^ SP ^ sum) >> 8];\r |
| 5523 | IY = sum;\r |
| 5524 | break;\r |
| 5525 | \r |
| 5526 | case 0x44: /* LD B,IYH */\r |
| 5527 | tStates += 9;\r |
| 5528 | sim_brk_pend[0] = FALSE;\r |
| 5529 | SET_HIGH_REGISTER(BC, HIGH_REGISTER(IY));\r |
| 5530 | break;\r |
| 5531 | \r |
| 5532 | case 0x45: /* LD B,IYL */\r |
| 5533 | tStates += 9;\r |
| 5534 | sim_brk_pend[0] = FALSE;\r |
| 5535 | SET_HIGH_REGISTER(BC, LOW_REGISTER(IY));\r |
| 5536 | break;\r |
| 5537 | \r |
| 5538 | case 0x46: /* LD B,(IY+dd) */\r |
| 5539 | tStates += 19;\r |
| 5540 | adr = IY + (int8) RAM_PP(PC);\r |
| 5541 | CHECK_BREAK_BYTE(adr);\r |
| 5542 | SET_HIGH_REGISTER(BC, GetBYTE(adr));\r |
| 5543 | break;\r |
| 5544 | \r |
| 5545 | case 0x4c: /* LD C,IYH */\r |
| 5546 | tStates += 9;\r |
| 5547 | sim_brk_pend[0] = FALSE;\r |
| 5548 | SET_LOW_REGISTER(BC, HIGH_REGISTER(IY));\r |
| 5549 | break;\r |
| 5550 | \r |
| 5551 | case 0x4d: /* LD C,IYL */\r |
| 5552 | tStates += 9;\r |
| 5553 | sim_brk_pend[0] = FALSE;\r |
| 5554 | SET_LOW_REGISTER(BC, LOW_REGISTER(IY));\r |
| 5555 | break;\r |
| 5556 | \r |
| 5557 | case 0x4e: /* LD C,(IY+dd) */\r |
| 5558 | tStates += 19;\r |
| 5559 | adr = IY + (int8) RAM_PP(PC);\r |
| 5560 | CHECK_BREAK_BYTE(adr);\r |
| 5561 | SET_LOW_REGISTER(BC, GetBYTE(adr));\r |
| 5562 | break;\r |
| 5563 | \r |
| 5564 | case 0x54: /* LD D,IYH */\r |
| 5565 | tStates += 9;\r |
| 5566 | sim_brk_pend[0] = FALSE;\r |
| 5567 | SET_HIGH_REGISTER(DE, HIGH_REGISTER(IY));\r |
| 5568 | break;\r |
| 5569 | \r |
| 5570 | case 0x55: /* LD D,IYL */\r |
| 5571 | tStates += 9;\r |
| 5572 | sim_brk_pend[0] = FALSE;\r |
| 5573 | SET_HIGH_REGISTER(DE, LOW_REGISTER(IY));\r |
| 5574 | break;\r |
| 5575 | \r |
| 5576 | case 0x56: /* LD D,(IY+dd) */\r |
| 5577 | tStates += 19;\r |
| 5578 | adr = IY + (int8) RAM_PP(PC);\r |
| 5579 | CHECK_BREAK_BYTE(adr);\r |
| 5580 | SET_HIGH_REGISTER(DE, GetBYTE(adr));\r |
| 5581 | break;\r |
| 5582 | \r |
| 5583 | case 0x5c: /* LD E,IYH */\r |
| 5584 | tStates += 9;\r |
| 5585 | sim_brk_pend[0] = FALSE;\r |
| 5586 | SET_LOW_REGISTER(DE, HIGH_REGISTER(IY));\r |
| 5587 | break;\r |
| 5588 | \r |
| 5589 | case 0x5d: /* LD E,IYL */\r |
| 5590 | tStates += 9;\r |
| 5591 | sim_brk_pend[0] = FALSE;\r |
| 5592 | SET_LOW_REGISTER(DE, LOW_REGISTER(IY));\r |
| 5593 | break;\r |
| 5594 | \r |
| 5595 | case 0x5e: /* LD E,(IY+dd) */\r |
| 5596 | tStates += 19;\r |
| 5597 | adr = IY + (int8) RAM_PP(PC);\r |
| 5598 | CHECK_BREAK_BYTE(adr);\r |
| 5599 | SET_LOW_REGISTER(DE, GetBYTE(adr));\r |
| 5600 | break;\r |
| 5601 | \r |
| 5602 | case 0x60: /* LD IYH,B */\r |
| 5603 | tStates += 9;\r |
| 5604 | sim_brk_pend[0] = FALSE;\r |
| 5605 | SET_HIGH_REGISTER(IY, HIGH_REGISTER(BC));\r |
| 5606 | break;\r |
| 5607 | \r |
| 5608 | case 0x61: /* LD IYH,C */\r |
| 5609 | tStates += 9;\r |
| 5610 | sim_brk_pend[0] = FALSE;\r |
| 5611 | SET_HIGH_REGISTER(IY, LOW_REGISTER(BC));\r |
| 5612 | break;\r |
| 5613 | \r |
| 5614 | case 0x62: /* LD IYH,D */\r |
| 5615 | tStates += 9;\r |
| 5616 | sim_brk_pend[0] = FALSE;\r |
| 5617 | SET_HIGH_REGISTER(IY, HIGH_REGISTER(DE));\r |
| 5618 | break;\r |
| 5619 | \r |
| 5620 | case 0x63: /* LD IYH,E */\r |
| 5621 | tStates += 9;\r |
| 5622 | sim_brk_pend[0] = FALSE;\r |
| 5623 | SET_HIGH_REGISTER(IY, LOW_REGISTER(DE));\r |
| 5624 | break;\r |
| 5625 | \r |
| 5626 | case 0x64: /* LD IYH,IYH */\r |
| 5627 | tStates += 9;\r |
| 5628 | sim_brk_pend[0] = FALSE; /* nop */\r |
| 5629 | break;\r |
| 5630 | \r |
| 5631 | case 0x65: /* LD IYH,IYL */\r |
| 5632 | tStates += 9;\r |
| 5633 | sim_brk_pend[0] = FALSE;\r |
| 5634 | SET_HIGH_REGISTER(IY, LOW_REGISTER(IY));\r |
| 5635 | break;\r |
| 5636 | \r |
| 5637 | case 0x66: /* LD H,(IY+dd) */\r |
| 5638 | tStates += 19;\r |
| 5639 | adr = IY + (int8) RAM_PP(PC);\r |
| 5640 | CHECK_BREAK_BYTE(adr);\r |
| 5641 | SET_HIGH_REGISTER(HL, GetBYTE(adr));\r |
| 5642 | break;\r |
| 5643 | \r |
| 5644 | case 0x67: /* LD IYH,A */\r |
| 5645 | tStates += 9;\r |
| 5646 | sim_brk_pend[0] = FALSE;\r |
| 5647 | SET_HIGH_REGISTER(IY, HIGH_REGISTER(AF));\r |
| 5648 | break;\r |
| 5649 | \r |
| 5650 | case 0x68: /* LD IYL,B */\r |
| 5651 | tStates += 9;\r |
| 5652 | sim_brk_pend[0] = FALSE;\r |
| 5653 | SET_LOW_REGISTER(IY, HIGH_REGISTER(BC));\r |
| 5654 | break;\r |
| 5655 | \r |
| 5656 | case 0x69: /* LD IYL,C */\r |
| 5657 | tStates += 9;\r |
| 5658 | sim_brk_pend[0] = FALSE;\r |
| 5659 | SET_LOW_REGISTER(IY, LOW_REGISTER(BC));\r |
| 5660 | break;\r |
| 5661 | \r |
| 5662 | case 0x6a: /* LD IYL,D */\r |
| 5663 | tStates += 9;\r |
| 5664 | sim_brk_pend[0] = FALSE;\r |
| 5665 | SET_LOW_REGISTER(IY, HIGH_REGISTER(DE));\r |
| 5666 | break;\r |
| 5667 | \r |
| 5668 | case 0x6b: /* LD IYL,E */\r |
| 5669 | tStates += 9;\r |
| 5670 | sim_brk_pend[0] = FALSE;\r |
| 5671 | SET_LOW_REGISTER(IY, LOW_REGISTER(DE));\r |
| 5672 | break;\r |
| 5673 | \r |
| 5674 | case 0x6c: /* LD IYL,IYH */\r |
| 5675 | tStates += 9;\r |
| 5676 | sim_brk_pend[0] = FALSE;\r |
| 5677 | SET_LOW_REGISTER(IY, HIGH_REGISTER(IY));\r |
| 5678 | break;\r |
| 5679 | \r |
| 5680 | case 0x6d: /* LD IYL,IYL */\r |
| 5681 | tStates += 9;\r |
| 5682 | sim_brk_pend[0] = FALSE; /* nop */\r |
| 5683 | break;\r |
| 5684 | \r |
| 5685 | case 0x6e: /* LD L,(IY+dd) */\r |
| 5686 | tStates += 19;\r |
| 5687 | adr = IY + (int8) RAM_PP(PC);\r |
| 5688 | CHECK_BREAK_BYTE(adr);\r |
| 5689 | SET_LOW_REGISTER(HL, GetBYTE(adr));\r |
| 5690 | break;\r |
| 5691 | \r |
| 5692 | case 0x6f: /* LD IYL,A */\r |
| 5693 | tStates += 9;\r |
| 5694 | sim_brk_pend[0] = FALSE;\r |
| 5695 | SET_LOW_REGISTER(IY, HIGH_REGISTER(AF));\r |
| 5696 | break;\r |
| 5697 | \r |
| 5698 | case 0x70: /* LD (IY+dd),B */\r |
| 5699 | tStates += 19;\r |
| 5700 | adr = IY + (int8) RAM_PP(PC);\r |
| 5701 | CHECK_BREAK_BYTE(adr);\r |
| 5702 | PutBYTE(adr, HIGH_REGISTER(BC));\r |
| 5703 | break;\r |
| 5704 | \r |
| 5705 | case 0x71: /* LD (IY+dd),C */\r |
| 5706 | tStates += 19;\r |
| 5707 | adr = IY + (int8) RAM_PP(PC);\r |
| 5708 | CHECK_BREAK_BYTE(adr);\r |
| 5709 | PutBYTE(adr, LOW_REGISTER(BC));\r |
| 5710 | break;\r |
| 5711 | \r |
| 5712 | case 0x72: /* LD (IY+dd),D */\r |
| 5713 | tStates += 19;\r |
| 5714 | adr = IY + (int8) RAM_PP(PC);\r |
| 5715 | CHECK_BREAK_BYTE(adr);\r |
| 5716 | PutBYTE(adr, HIGH_REGISTER(DE));\r |
| 5717 | break;\r |
| 5718 | \r |
| 5719 | case 0x73: /* LD (IY+dd),E */\r |
| 5720 | tStates += 19;\r |
| 5721 | adr = IY + (int8) RAM_PP(PC);\r |
| 5722 | CHECK_BREAK_BYTE(adr);\r |
| 5723 | PutBYTE(adr, LOW_REGISTER(DE));\r |
| 5724 | break;\r |
| 5725 | \r |
| 5726 | case 0x74: /* LD (IY+dd),H */\r |
| 5727 | tStates += 19;\r |
| 5728 | adr = IY + (int8) RAM_PP(PC);\r |
| 5729 | CHECK_BREAK_BYTE(adr);\r |
| 5730 | PutBYTE(adr, HIGH_REGISTER(HL));\r |
| 5731 | break;\r |
| 5732 | \r |
| 5733 | case 0x75: /* LD (IY+dd),L */\r |
| 5734 | tStates += 19;\r |
| 5735 | adr = IY + (int8) RAM_PP(PC);\r |
| 5736 | CHECK_BREAK_BYTE(adr);\r |
| 5737 | PutBYTE(adr, LOW_REGISTER(HL));\r |
| 5738 | break;\r |
| 5739 | \r |
| 5740 | case 0x77: /* LD (IY+dd),A */\r |
| 5741 | tStates += 19;\r |
| 5742 | adr = IY + (int8) RAM_PP(PC);\r |
| 5743 | CHECK_BREAK_BYTE(adr);\r |
| 5744 | PutBYTE(adr, HIGH_REGISTER(AF));\r |
| 5745 | break;\r |
| 5746 | \r |
| 5747 | case 0x7c: /* LD A,IYH */\r |
| 5748 | tStates += 9;\r |
| 5749 | sim_brk_pend[0] = FALSE;\r |
| 5750 | SET_HIGH_REGISTER(AF, HIGH_REGISTER(IY));\r |
| 5751 | break;\r |
| 5752 | \r |
| 5753 | case 0x7d: /* LD A,IYL */\r |
| 5754 | tStates += 9;\r |
| 5755 | sim_brk_pend[0] = FALSE;\r |
| 5756 | SET_HIGH_REGISTER(AF, LOW_REGISTER(IY));\r |
| 5757 | break;\r |
| 5758 | \r |
| 5759 | case 0x7e: /* LD A,(IY+dd) */\r |
| 5760 | tStates += 19;\r |
| 5761 | adr = IY + (int8) RAM_PP(PC);\r |
| 5762 | CHECK_BREAK_BYTE(adr);\r |
| 5763 | SET_HIGH_REGISTER(AF, GetBYTE(adr));\r |
| 5764 | break;\r |
| 5765 | \r |
| 5766 | case 0x84: /* ADD A,IYH */\r |
| 5767 | tStates += 9;\r |
| 5768 | sim_brk_pend[0] = FALSE;\r |
| 5769 | temp = HIGH_REGISTER(IY);\r |
| 5770 | acu = HIGH_REGISTER(AF);\r |
| 5771 | sum = acu + temp;\r |
| 5772 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 5773 | break;\r |
| 5774 | \r |
| 5775 | case 0x85: /* ADD A,IYL */\r |
| 5776 | tStates += 9;\r |
| 5777 | sim_brk_pend[0] = FALSE;\r |
| 5778 | temp = LOW_REGISTER(IY);\r |
| 5779 | acu = HIGH_REGISTER(AF);\r |
| 5780 | sum = acu + temp;\r |
| 5781 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 5782 | break;\r |
| 5783 | \r |
| 5784 | case 0x86: /* ADD A,(IY+dd) */\r |
| 5785 | tStates += 19;\r |
| 5786 | adr = IY + (int8) RAM_PP(PC);\r |
| 5787 | CHECK_BREAK_BYTE(adr);\r |
| 5788 | temp = GetBYTE(adr);\r |
| 5789 | acu = HIGH_REGISTER(AF);\r |
| 5790 | sum = acu + temp;\r |
| 5791 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 5792 | break;\r |
| 5793 | \r |
| 5794 | case 0x8c: /* ADC A,IYH */\r |
| 5795 | tStates += 9;\r |
| 5796 | sim_brk_pend[0] = FALSE;\r |
| 5797 | temp = HIGH_REGISTER(IY);\r |
| 5798 | acu = HIGH_REGISTER(AF);\r |
| 5799 | sum = acu + temp + TSTFLAG(C);\r |
| 5800 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 5801 | break;\r |
| 5802 | \r |
| 5803 | case 0x8d: /* ADC A,IYL */\r |
| 5804 | tStates += 9;\r |
| 5805 | sim_brk_pend[0] = FALSE;\r |
| 5806 | temp = LOW_REGISTER(IY);\r |
| 5807 | acu = HIGH_REGISTER(AF);\r |
| 5808 | sum = acu + temp + TSTFLAG(C);\r |
| 5809 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 5810 | break;\r |
| 5811 | \r |
| 5812 | case 0x8e: /* ADC A,(IY+dd) */\r |
| 5813 | tStates += 19;\r |
| 5814 | adr = IY + (int8) RAM_PP(PC);\r |
| 5815 | CHECK_BREAK_BYTE(adr);\r |
| 5816 | temp = GetBYTE(adr);\r |
| 5817 | acu = HIGH_REGISTER(AF);\r |
| 5818 | sum = acu + temp + TSTFLAG(C);\r |
| 5819 | AF = addTable[sum] | cbitsZ80Table[acu ^ temp ^ sum];\r |
| 5820 | break;\r |
| 5821 | \r |
| 5822 | case 0x96: /* SUB (IY+dd) */\r |
| 5823 | tStates += 19;\r |
| 5824 | adr = IY + (int8) RAM_PP(PC);\r |
| 5825 | CHECK_BREAK_BYTE(adr);\r |
| 5826 | temp = GetBYTE(adr);\r |
| 5827 | acu = HIGH_REGISTER(AF);\r |
| 5828 | sum = acu - temp;\r |
| 5829 | AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 5830 | break;\r |
| 5831 | \r |
| 5832 | case 0x94: /* SUB IYH */\r |
| 5833 | SETFLAG(C, 0);/* fall through, a bit less efficient but smaller code */\r |
| 5834 | \r |
| 5835 | case 0x9c: /* SBC A,IYH */\r |
| 5836 | tStates += 9;\r |
| 5837 | sim_brk_pend[0] = FALSE;\r |
| 5838 | temp = HIGH_REGISTER(IY);\r |
| 5839 | acu = HIGH_REGISTER(AF);\r |
| 5840 | sum = acu - temp - TSTFLAG(C);\r |
| 5841 | AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 5842 | break;\r |
| 5843 | \r |
| 5844 | case 0x95: /* SUB IYL */\r |
| 5845 | SETFLAG(C, 0);/* fall through, a bit less efficient but smaller code */\r |
| 5846 | \r |
| 5847 | case 0x9d: /* SBC A,IYL */\r |
| 5848 | tStates += 9;\r |
| 5849 | sim_brk_pend[0] = FALSE;\r |
| 5850 | temp = LOW_REGISTER(IY);\r |
| 5851 | acu = HIGH_REGISTER(AF);\r |
| 5852 | sum = acu - temp - TSTFLAG(C);\r |
| 5853 | AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 5854 | break;\r |
| 5855 | \r |
| 5856 | case 0x9e: /* SBC A,(IY+dd) */\r |
| 5857 | tStates += 19;\r |
| 5858 | adr = IY + (int8) RAM_PP(PC);\r |
| 5859 | CHECK_BREAK_BYTE(adr);\r |
| 5860 | temp = GetBYTE(adr);\r |
| 5861 | acu = HIGH_REGISTER(AF);\r |
| 5862 | sum = acu - temp - TSTFLAG(C);\r |
| 5863 | AF = addTable[sum & 0xff] | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 5864 | break;\r |
| 5865 | \r |
| 5866 | case 0xa4: /* AND IYH */\r |
| 5867 | tStates += 9;\r |
| 5868 | sim_brk_pend[0] = FALSE;\r |
| 5869 | AF = andTable[((AF & IY) >> 8) & 0xff];\r |
| 5870 | break;\r |
| 5871 | \r |
| 5872 | case 0xa5: /* AND IYL */\r |
| 5873 | tStates += 9;\r |
| 5874 | sim_brk_pend[0] = FALSE;\r |
| 5875 | AF = andTable[((AF >> 8) & IY) & 0xff];\r |
| 5876 | break;\r |
| 5877 | \r |
| 5878 | case 0xa6: /* AND (IY+dd) */\r |
| 5879 | tStates += 19;\r |
| 5880 | adr = IY + (int8) RAM_PP(PC);\r |
| 5881 | CHECK_BREAK_BYTE(adr);\r |
| 5882 | AF = andTable[((AF >> 8) & GetBYTE(adr)) & 0xff];\r |
| 5883 | break;\r |
| 5884 | \r |
| 5885 | case 0xac: /* XOR IYH */\r |
| 5886 | tStates += 9;\r |
| 5887 | sim_brk_pend[0] = FALSE;\r |
| 5888 | AF = xororTable[((AF ^ IY) >> 8) & 0xff];\r |
| 5889 | break;\r |
| 5890 | \r |
| 5891 | case 0xad: /* XOR IYL */\r |
| 5892 | tStates += 9;\r |
| 5893 | sim_brk_pend[0] = FALSE;\r |
| 5894 | AF = xororTable[((AF >> 8) ^ IY) & 0xff];\r |
| 5895 | break;\r |
| 5896 | \r |
| 5897 | case 0xae: /* XOR (IY+dd) */\r |
| 5898 | tStates += 19;\r |
| 5899 | adr = IY + (int8) RAM_PP(PC);\r |
| 5900 | CHECK_BREAK_BYTE(adr);\r |
| 5901 | AF = xororTable[((AF >> 8) ^ GetBYTE(adr)) & 0xff];\r |
| 5902 | break;\r |
| 5903 | \r |
| 5904 | case 0xb4: /* OR IYH */\r |
| 5905 | tStates += 9;\r |
| 5906 | sim_brk_pend[0] = FALSE;\r |
| 5907 | AF = xororTable[((AF | IY) >> 8) & 0xff];\r |
| 5908 | break;\r |
| 5909 | \r |
| 5910 | case 0xb5: /* OR IYL */\r |
| 5911 | tStates += 9;\r |
| 5912 | sim_brk_pend[0] = FALSE;\r |
| 5913 | AF = xororTable[((AF >> 8) | IY) & 0xff];\r |
| 5914 | break;\r |
| 5915 | \r |
| 5916 | case 0xb6: /* OR (IY+dd) */\r |
| 5917 | tStates += 19;\r |
| 5918 | adr = IY + (int8) RAM_PP(PC);\r |
| 5919 | CHECK_BREAK_BYTE(adr);\r |
| 5920 | AF = xororTable[((AF >> 8) | GetBYTE(adr)) & 0xff];\r |
| 5921 | break;\r |
| 5922 | \r |
| 5923 | case 0xbc: /* CP IYH */\r |
| 5924 | tStates += 9;\r |
| 5925 | sim_brk_pend[0] = FALSE;\r |
| 5926 | temp = HIGH_REGISTER(IY);\r |
| 5927 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 5928 | acu = HIGH_REGISTER(AF);\r |
| 5929 | sum = acu - temp;\r |
| 5930 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 5931 | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 5932 | break;\r |
| 5933 | \r |
| 5934 | case 0xbd: /* CP IYL */\r |
| 5935 | tStates += 9;\r |
| 5936 | sim_brk_pend[0] = FALSE;\r |
| 5937 | temp = LOW_REGISTER(IY);\r |
| 5938 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 5939 | acu = HIGH_REGISTER(AF);\r |
| 5940 | sum = acu - temp;\r |
| 5941 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 5942 | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 5943 | break;\r |
| 5944 | \r |
| 5945 | case 0xbe: /* CP (IY+dd) */\r |
| 5946 | tStates += 19;\r |
| 5947 | adr = IY + (int8) RAM_PP(PC);\r |
| 5948 | CHECK_BREAK_BYTE(adr);\r |
| 5949 | temp = GetBYTE(adr);\r |
| 5950 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 5951 | acu = HIGH_REGISTER(AF);\r |
| 5952 | sum = acu - temp;\r |
| 5953 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 5954 | cbits2Z80Table[(acu ^ temp ^ sum) & 0x1ff];\r |
| 5955 | break;\r |
| 5956 | \r |
| 5957 | case 0xcb: /* CB prefix */\r |
| 5958 | adr = IY + (int8) RAM_PP(PC);\r |
| 5959 | switch ((op = GetBYTE(PC)) & 7) {\r |
| 5960 | \r |
| 5961 | case 0:\r |
| 5962 | sim_brk_pend[0] = FALSE;\r |
| 5963 | ++PC;\r |
| 5964 | acu = HIGH_REGISTER(BC);\r |
| 5965 | break;\r |
| 5966 | \r |
| 5967 | case 1:\r |
| 5968 | sim_brk_pend[0] = FALSE;\r |
| 5969 | ++PC;\r |
| 5970 | acu = LOW_REGISTER(BC);\r |
| 5971 | break;\r |
| 5972 | \r |
| 5973 | case 2:\r |
| 5974 | sim_brk_pend[0] = FALSE;\r |
| 5975 | ++PC;\r |
| 5976 | acu = HIGH_REGISTER(DE);\r |
| 5977 | break;\r |
| 5978 | \r |
| 5979 | case 3:\r |
| 5980 | sim_brk_pend[0] = FALSE;\r |
| 5981 | ++PC;\r |
| 5982 | acu = LOW_REGISTER(DE);\r |
| 5983 | break;\r |
| 5984 | \r |
| 5985 | case 4:\r |
| 5986 | sim_brk_pend[0] = FALSE;\r |
| 5987 | ++PC;\r |
| 5988 | acu = HIGH_REGISTER(HL);\r |
| 5989 | break;\r |
| 5990 | \r |
| 5991 | case 5:\r |
| 5992 | sim_brk_pend[0] = FALSE;\r |
| 5993 | ++PC;\r |
| 5994 | acu = LOW_REGISTER(HL);\r |
| 5995 | break;\r |
| 5996 | \r |
| 5997 | case 6:\r |
| 5998 | CHECK_BREAK_BYTE(adr);\r |
| 5999 | ++PC;\r |
| 6000 | acu = GetBYTE(adr);\r |
| 6001 | break;\r |
| 6002 | \r |
| 6003 | case 7:\r |
| 6004 | sim_brk_pend[0] = FALSE;\r |
| 6005 | ++PC;\r |
| 6006 | acu = HIGH_REGISTER(AF);\r |
| 6007 | break;\r |
| 6008 | }\r |
| 6009 | switch (op & 0xc0) {\r |
| 6010 | \r |
| 6011 | case 0x00: /* shift/rotate */\r |
| 6012 | tStates += 23;\r |
| 6013 | switch (op & 0x38) {\r |
| 6014 | \r |
| 6015 | case 0x00: /* RLC */\r |
| 6016 | temp = (acu << 1) | (acu >> 7);\r |
| 6017 | cbits = temp & 1;\r |
| 6018 | goto cbshflg3;\r |
| 6019 | \r |
| 6020 | case 0x08: /* RRC */\r |
| 6021 | temp = (acu >> 1) | (acu << 7);\r |
| 6022 | cbits = temp & 0x80;\r |
| 6023 | goto cbshflg3;\r |
| 6024 | \r |
| 6025 | case 0x10: /* RL */\r |
| 6026 | temp = (acu << 1) | TSTFLAG(C);\r |
| 6027 | cbits = acu & 0x80;\r |
| 6028 | goto cbshflg3;\r |
| 6029 | \r |
| 6030 | case 0x18: /* RR */\r |
| 6031 | temp = (acu >> 1) | (TSTFLAG(C) << 7);\r |
| 6032 | cbits = acu & 1;\r |
| 6033 | goto cbshflg3;\r |
| 6034 | \r |
| 6035 | case 0x20: /* SLA */\r |
| 6036 | temp = acu << 1;\r |
| 6037 | cbits = acu & 0x80;\r |
| 6038 | goto cbshflg3;\r |
| 6039 | \r |
| 6040 | case 0x28: /* SRA */\r |
| 6041 | temp = (acu >> 1) | (acu & 0x80);\r |
| 6042 | cbits = acu & 1;\r |
| 6043 | goto cbshflg3;\r |
| 6044 | \r |
| 6045 | case 0x30: /* SLIA */\r |
| 6046 | temp = (acu << 1) | 1;\r |
| 6047 | cbits = acu & 0x80;\r |
| 6048 | goto cbshflg3;\r |
| 6049 | \r |
| 6050 | case 0x38: /* SRL */\r |
| 6051 | temp = acu >> 1;\r |
| 6052 | cbits = acu & 1;\r |
| 6053 | cbshflg3:\r |
| 6054 | AF = (AF & ~0xff) | rotateShiftTable[temp & 0xff] | !!cbits;\r |
| 6055 | /* !!cbits == 0 if cbits == 0 !!cbits == 1 if cbits > 0 */\r |
| 6056 | }\r |
| 6057 | break;\r |
| 6058 | \r |
| 6059 | case 0x40: /* BIT */\r |
| 6060 | tStates += 20;\r |
| 6061 | if (acu & (1 << ((op >> 3) & 7)))\r |
| 6062 | AF = (AF & ~0xfe) | 0x10 | (((op & 0x38) == 0x38) << 7);\r |
| 6063 | else AF = (AF & ~0xfe) | 0x54;\r |
| 6064 | if ((op & 7) != 6) AF |= (acu & 0x28);\r |
| 6065 | temp = acu;\r |
| 6066 | break;\r |
| 6067 | \r |
| 6068 | case 0x80: /* RES */\r |
| 6069 | tStates += 23;\r |
| 6070 | temp = acu & ~(1 << ((op >> 3) & 7));\r |
| 6071 | break;\r |
| 6072 | \r |
| 6073 | case 0xc0: /* SET */\r |
| 6074 | tStates += 23;\r |
| 6075 | temp = acu | (1 << ((op >> 3) & 7));\r |
| 6076 | break;\r |
| 6077 | }\r |
| 6078 | switch (op & 7) {\r |
| 6079 | \r |
| 6080 | case 0:\r |
| 6081 | SET_HIGH_REGISTER(BC, temp);\r |
| 6082 | break;\r |
| 6083 | \r |
| 6084 | case 1:\r |
| 6085 | SET_LOW_REGISTER(BC, temp);\r |
| 6086 | break;\r |
| 6087 | \r |
| 6088 | case 2:\r |
| 6089 | SET_HIGH_REGISTER(DE, temp);\r |
| 6090 | break;\r |
| 6091 | \r |
| 6092 | case 3:\r |
| 6093 | SET_LOW_REGISTER(DE, temp);\r |
| 6094 | break;\r |
| 6095 | \r |
| 6096 | case 4:\r |
| 6097 | SET_HIGH_REGISTER(HL, temp);\r |
| 6098 | break;\r |
| 6099 | \r |
| 6100 | case 5:\r |
| 6101 | SET_LOW_REGISTER(HL, temp);\r |
| 6102 | break;\r |
| 6103 | \r |
| 6104 | case 6:\r |
| 6105 | PutBYTE(adr, temp);\r |
| 6106 | break;\r |
| 6107 | \r |
| 6108 | case 7:\r |
| 6109 | SET_HIGH_REGISTER(AF, temp);\r |
| 6110 | break;\r |
| 6111 | }\r |
| 6112 | break;\r |
| 6113 | \r |
| 6114 | case 0xe1: /* POP IY */\r |
| 6115 | tStates += 14;\r |
| 6116 | CHECK_BREAK_WORD(SP);\r |
| 6117 | POP(IY);\r |
| 6118 | break;\r |
| 6119 | \r |
| 6120 | case 0xe3: /* EX (SP),IY */\r |
| 6121 | tStates += 23;\r |
| 6122 | CHECK_BREAK_WORD(SP);\r |
| 6123 | temp = IY;\r |
| 6124 | POP(IY);\r |
| 6125 | PUSH(temp);\r |
| 6126 | break;\r |
| 6127 | \r |
| 6128 | case 0xe5: /* PUSH IY */\r |
| 6129 | tStates += 15;\r |
| 6130 | CHECK_BREAK_WORD(SP - 2);\r |
| 6131 | PUSH(IY);\r |
| 6132 | break;\r |
| 6133 | \r |
| 6134 | case 0xe9: /* JP (IY) */\r |
| 6135 | tStates += 8;\r |
| 6136 | sim_brk_pend[0] = FALSE;\r |
| 6137 | PCQ_ENTRY(PCX);\r |
| 6138 | PC = IY;\r |
| 6139 | break;\r |
| 6140 | \r |
| 6141 | case 0xf9: /* LD SP,IY */\r |
| 6142 | tStates += 10;\r |
| 6143 | sim_brk_pend[0] = FALSE;\r |
| 6144 | SP = IY;\r |
| 6145 | break;\r |
| 6146 | \r |
| 6147 | default: /* ignore FD */\r |
| 6148 | sim_brk_pend[0] = FALSE;\r |
| 6149 | CHECK_CPU_Z80;\r |
| 6150 | PC--;\r |
| 6151 | }\r |
| 6152 | break;\r |
| 6153 | \r |
| 6154 | case 0xfe: /* CP nn */\r |
| 6155 | tStates += 7;\r |
| 6156 | sim_brk_pend[0] = FALSE;\r |
| 6157 | temp = RAM_PP(PC);\r |
| 6158 | AF = (AF & ~0x28) | (temp & 0x28);\r |
| 6159 | acu = HIGH_REGISTER(AF);\r |
| 6160 | sum = acu - temp;\r |
| 6161 | cbits = acu ^ temp ^ sum;\r |
| 6162 | AF = (AF & ~0xff) | cpTable[sum & 0xff] | (temp & 0x28) |\r |
| 6163 | (SET_PV) | cbits2Table[cbits & 0x1ff];\r |
| 6164 | break;\r |
| 6165 | \r |
| 6166 | case 0xff: /* RST 38H */\r |
| 6167 | tStates += 11;\r |
| 6168 | CHECK_BREAK_WORD(SP - 2);\r |
| 6169 | PUSH(PC);\r |
| 6170 | PCQ_ENTRY(PCX);\r |
| 6171 | PC = 0x38;\r |
| 6172 | }\r |
| 6173 | }\r |
| 6174 | end_decode:\r |
| 6175 | \r |
| 6176 | /* simulation halted */\r |
| 6177 | PC_S = ((reason == STOP_OPCODE) || (reason == STOP_MEM)) ? PCX : (PC & ADDRMASK);\r |
| 6178 | pcq_r -> qptr = pcq_p; /* update pc q ptr */\r |
| 6179 | AF_S = AF;\r |
| 6180 | BC_S = BC;\r |
| 6181 | DE_S = DE;\r |
| 6182 | HL_S = HL;\r |
| 6183 | IX_S = IX;\r |
| 6184 | IY_S = IY;\r |
| 6185 | SP_S = SP;\r |
| 6186 | executedTStates = tStates;\r |
| 6187 | return reason;\r |
| 6188 | }\r |
| 6189 | \r |
| 6190 | /* reset routine */\r |
| 6191 | \r |
| 6192 | static t_stat cpu_reset(DEVICE *dptr) {\r |
| 6193 | extern uint32 sim_brk_types, sim_brk_dflt; /* breakpoint info */\r |
| 6194 | int32 i;\r |
| 6195 | AF_S = AF1_S = 0;\r |
| 6196 | BC_S = DE_S = HL_S = 0;\r |
| 6197 | BC1_S = DE1_S = HL1_S = 0;\r |
| 6198 | IR_S = IX_S = IY_S = SP_S = 0;\r |
| 6199 | IFF_S = 3;\r |
| 6200 | setBankSelect(0);\r |
| 6201 | cpu8086reset();\r |
| 6202 | sim_brk_types = (SWMASK('E') | SWMASK('I') | SWMASK('M'));\r |
| 6203 | sim_brk_dflt = SWMASK('E');\r |
| 6204 | for (i = 0; i < PCQ_SIZE; i++) pcq[i] = 0;\r |
| 6205 | pcq_p = 0;\r |
| 6206 | pcq_r = find_reg("PCQ", NULL, dptr);\r |
| 6207 | if (pcq_r) pcq_r -> qptr = 0;\r |
| 6208 | else return SCPE_IERR;\r |
| 6209 | return SCPE_OK;\r |
| 6210 | }\r |
| 6211 | \r |
| 6212 | t_stat install_bootrom(int32 bootrom[], int32 size, int32 addr, int32 makeROM) {\r |
| 6213 | int32 i;\r |
| 6214 | if (addr & (PAGESIZE - 1)) return SCPE_IERR;\r |
| 6215 | for (i = 0; i < size; i++) {\r |
| 6216 | if (makeROM && ((i & (PAGESIZE - 1)) == 0))\r |
| 6217 | mmu_table[(i + addr) >> LOG2PAGESIZE] = ROM_PAGE;\r |
| 6218 | M[i + addr] = bootrom[i] & 0xff;\r |
| 6219 | }\r |
| 6220 | return SCPE_OK;\r |
| 6221 | }\r |
| 6222 | \r |
| 6223 | /* memory examine */\r |
| 6224 | static t_stat cpu_ex(t_value *vptr, t_addr addr, UNIT *uptr, int32 sw) {\r |
| 6225 | int32 oldBankSelect;\r |
| 6226 | if (chiptype == CHIP_TYPE_8086) *vptr = GetBYTEExtended(addr);\r |
| 6227 | else {\r |
| 6228 | oldBankSelect = getBankSelect();\r |
| 6229 | setBankSelect((addr >> MAXBANKSIZELOG2) & BANKMASK);\r |
| 6230 | *vptr = GetBYTE(addr & ADDRMASK);\r |
| 6231 | setBankSelect(oldBankSelect);\r |
| 6232 | }\r |
| 6233 | return SCPE_OK;\r |
| 6234 | }\r |
| 6235 | \r |
| 6236 | /* memory deposit */\r |
| 6237 | static t_stat cpu_dep(t_value val, t_addr addr, UNIT *uptr, int32 sw) {\r |
| 6238 | int32 oldBankSelect;\r |
| 6239 | if (chiptype == CHIP_TYPE_8086) PutBYTEExtended(addr, val);\r |
| 6240 | else {\r |
| 6241 | oldBankSelect = getBankSelect();\r |
| 6242 | setBankSelect((addr >> MAXBANKSIZELOG2) & BANKMASK);\r |
| 6243 | PutBYTE(addr & ADDRMASK, val);\r |
| 6244 | setBankSelect(oldBankSelect);\r |
| 6245 | }\r |
| 6246 | return SCPE_OK;\r |
| 6247 | }\r |
| 6248 | \r |
| 6249 | static t_stat chip_show(FILE *st, UNIT *uptr, int32 val, void *desc) {\r |
| 6250 | fprintf(st, cpu_unit.flags & UNIT_CPU_OPSTOP ? "ITRAP, " : "NOITRAP, ");\r |
| 6251 | if (chiptype == CHIP_TYPE_8080) fprintf(st, "8080");\r |
| 6252 | else if (chiptype == CHIP_TYPE_Z80) fprintf(st, "Z80");\r |
| 6253 | else if (chiptype == CHIP_TYPE_8086) fprintf(st, "8086");\r |
| 6254 | fprintf(st, ", ");\r |
| 6255 | if (ramtype == 0) fprintf(st, "AZ80");\r |
| 6256 | else if (ramtype == 1) fprintf(st, "HRAM");\r |
| 6257 | else if (ramtype == 2) fprintf(st, "VRAM");\r |
| 6258 | else if (ramtype == 3) fprintf(st, "CRAM");\r |
| 6259 | return SCPE_OK;\r |
| 6260 | }\r |
| 6261 | \r |
| 6262 | static t_stat cpu_show(FILE *st, UNIT *uptr, int32 val, void *desc) {\r |
| 6263 | uint32 i, maxBanks;\r |
| 6264 | MDEV m;\r |
| 6265 | maxBanks = ((cpu_unit.flags & UNIT_CPU_BANKED) ||\r |
| 6266 | (chiptype == CHIP_TYPE_8086)) ? MAXBANKS : 1;\r |
| 6267 | fprintf(st, "VERBOSE,\n ");\r |
| 6268 | for (i = 0; i < 4; i++) fprintf(st, "0123456789ABCDEF");\r |
| 6269 | fprintf(st, " [16k]");\r |
| 6270 | for (i = 0; i < (maxBanks * (MAXBANKSIZE >> LOG2PAGESIZE)); i++) {\r |
| 6271 | if ((i & 0x3f) == 0) fprintf(st, "\n%05X: ", (i << LOG2PAGESIZE));\r |
| 6272 | m = mmu_table[i];\r |
| 6273 | if (m.isRAM) fprintf(st, "W");\r |
| 6274 | else if (m.isEmpty) fprintf(st, "U");\r |
| 6275 | else if (m.routine) fprintf(st, "M");\r |
| 6276 | else fprintf(st, "R");\r |
| 6277 | }\r |
| 6278 | return SCPE_OK;\r |
| 6279 | }\r |
| 6280 | \r |
| 6281 | static void cpu_clear(void) {\r |
| 6282 | uint32 i;\r |
| 6283 | for (i = 0; i < MAXMEMORY; i++) M[i] = 0;\r |
| 6284 | for (i = 0; i < (MAXMEMORY >> LOG2PAGESIZE); i++) mmu_table[i] = RAM_PAGE;\r |
| 6285 | for (i = (MEMORYSIZE >> LOG2PAGESIZE); i < (MAXMEMORY >> LOG2PAGESIZE); i++)\r |
| 6286 | mmu_table[i] = EMPTY_PAGE;\r |
| 6287 | if (cpu_unit.flags & UNIT_CPU_ALTAIRROM) install_ALTAIRbootROM();\r |
| 6288 | }\r |
| 6289 | \r |
| 6290 | static t_stat cpu_clear_command(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6291 | cpu_clear();\r |
| 6292 | return SCPE_OK;\r |
| 6293 | }\r |
| 6294 | \r |
| 6295 | static t_stat cpu_set_altairrom(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6296 | install_ALTAIRbootROM();\r |
| 6297 | return SCPE_OK;\r |
| 6298 | }\r |
| 6299 | \r |
| 6300 | static t_stat cpu_set_noaltairrom(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6301 | mmu_table[ALTAIR_ROM_LOW >> LOG2PAGESIZE] = MEMORYSIZE < MAXBANKSIZE ?\r |
| 6302 | EMPTY_PAGE : RAM_PAGE;\r |
| 6303 | return SCPE_OK;\r |
| 6304 | }\r |
| 6305 | \r |
| 6306 | static t_stat cpu_set_nommu(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6307 | if (chiptype == CHIP_TYPE_8086) {\r |
| 6308 | printf("Cannot switch off MMU for 8086 CPU.\n");\r |
| 6309 | return SCPE_ARG;\r |
| 6310 | }\r |
| 6311 | if (cpu_unit.flags & UNIT_CPU_BANKED) {\r |
| 6312 | printf("Cannot switch off MMU for banked memory.\n");\r |
| 6313 | return SCPE_ARG;\r |
| 6314 | }\r |
| 6315 | if (((chiptype == CHIP_TYPE_8080) || (chiptype == CHIP_TYPE_Z80)) &&\r |
| 6316 | (MEMORYSIZE < MAXBANKSIZE)) {\r |
| 6317 | printf("Cannot switch off MMU when memory is %iKB < %iKB.\n",\r |
| 6318 | MEMORYSIZE >> KBLOG2, MAXBANKSIZE >> KBLOG2);\r |
| 6319 | return SCPE_ARG;\r |
| 6320 | }\r |
| 6321 | return SCPE_OK;\r |
| 6322 | }\r |
| 6323 | \r |
| 6324 | static t_stat cpu_set_banked(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6325 | if ((chiptype == CHIP_TYPE_8080) || (chiptype == CHIP_TYPE_Z80)) {\r |
| 6326 | if (MEMORYSIZE <= MAXBANKSIZE) previousCapacity = MEMORYSIZE;\r |
| 6327 | MEMORYSIZE = MAXMEMORY;\r |
| 6328 | cpu_dev.awidth = MAXBANKSIZELOG2 + MAXBANKSLOG2;\r |
| 6329 | cpu_clear();\r |
| 6330 | }\r |
| 6331 | else if (chiptype == CHIP_TYPE_8086) {\r |
| 6332 | printf("Cannot use banked memory for 8086 CPU.\n");\r |
| 6333 | return SCPE_ARG;\r |
| 6334 | }\r |
| 6335 | return SCPE_OK;\r |
| 6336 | }\r |
| 6337 | \r |
| 6338 | static t_stat cpu_set_nonbanked(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6339 | if ((chiptype == CHIP_TYPE_8080) || (chiptype == CHIP_TYPE_Z80)) {\r |
| 6340 | MEMORYSIZE = previousCapacity;\r |
| 6341 | cpu_dev.awidth = MAXBANKSIZELOG2;\r |
| 6342 | cpu_clear();\r |
| 6343 | }\r |
| 6344 | return SCPE_OK;\r |
| 6345 | }\r |
| 6346 | \r |
| 6347 | static int32 bankseldev(const int32 port, const int32 io, const int32 data) {\r |
| 6348 | if(io) {\r |
| 6349 | switch(ramtype) {\r |
| 6350 | case 1:\r |
| 6351 | if(data & 0x40) {\r |
| 6352 | printf("HRAM: Parity %s" NLP, data & 1 ? "ON" : "OFF");\r |
| 6353 | } else {\r |
| 6354 | printf("HRAM BANKSEL=%02x" NLP, data);\r |
| 6355 | }\r |
| 6356 | break;\r |
| 6357 | case 2:\r |
| 6358 | /* printf("VRAM BANKSEL=%02x" NLP, data);*/\r |
| 6359 | switch(data & 0xFF) {\r |
| 6360 | case 0x01:\r |
| 6361 | /* case 0x41: // OASIS uses this for some reason?*/\r |
| 6362 | setBankSelect(0);\r |
| 6363 | break;\r |
| 6364 | case 0x02:\r |
| 6365 | /* case 0x42: // OASIS uses this for some reason?*/\r |
| 6366 | setBankSelect(1);\r |
| 6367 | break;\r |
| 6368 | case 0x04:\r |
| 6369 | setBankSelect(2);\r |
| 6370 | break;\r |
| 6371 | case 0x08:\r |
| 6372 | setBankSelect(3);\r |
| 6373 | break;\r |
| 6374 | case 0x10:\r |
| 6375 | setBankSelect(4);\r |
| 6376 | break;\r |
| 6377 | case 0x20:\r |
| 6378 | setBankSelect(5);\r |
| 6379 | break;\r |
| 6380 | case 0x40:\r |
| 6381 | setBankSelect(6);\r |
| 6382 | break;\r |
| 6383 | case 0x80:\r |
| 6384 | setBankSelect(7);\r |
| 6385 | break;\r |
| 6386 | default:\r |
| 6387 | /* printf("Invalid bank select 0x%02x for VRAM" NLP, data);*/\r |
| 6388 | break;\r |
| 6389 | }\r |
| 6390 | break;\r |
| 6391 | case 3:\r |
| 6392 | printf("CRAM BANKSEL=%02x" NLP, data);\r |
| 6393 | break;\r |
| 6394 | case 0:\r |
| 6395 | default:\r |
| 6396 | break;\r |
| 6397 | }\r |
| 6398 | return 0;\r |
| 6399 | } else {\r |
| 6400 | return(0xFF);\r |
| 6401 | }\r |
| 6402 | }\r |
| 6403 | \r |
| 6404 | static t_stat cpu_set_chiptype(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6405 | if (chiptype == value) return SCPE_OK; /* nothing to do */\r |
| 6406 | if ((chiptype == CHIP_TYPE_8080) && (value == CHIP_TYPE_Z80) ||\r |
| 6407 | (chiptype == CHIP_TYPE_Z80) && (value == CHIP_TYPE_8080)) {\r |
| 6408 | chiptype = value;\r |
| 6409 | return SCPE_OK;\r |
| 6410 | }\r |
| 6411 | chiptype = value;\r |
| 6412 | if (chiptype == CHIP_TYPE_8086) {\r |
| 6413 | if (MEMORYSIZE <= MAXBANKSIZE) previousCapacity = MEMORYSIZE;\r |
| 6414 | MEMORYSIZE = MAXMEMORY;\r |
| 6415 | cpu_unit.flags &= ~(UNIT_CPU_BANKED | UNIT_CPU_ALTAIRROM);\r |
| 6416 | cpu_unit.flags |= UNIT_CPU_MMU;\r |
| 6417 | cpu_dev.awidth = MAXBANKSIZELOG2 + MAXBANKSLOG2;\r |
| 6418 | cpu_clear();\r |
| 6419 | }\r |
| 6420 | else if ((chiptype == CHIP_TYPE_8080) || (chiptype == CHIP_TYPE_Z80)) {\r |
| 6421 | MEMORYSIZE = previousCapacity;\r |
| 6422 | cpu_dev.awidth = MAXBANKSIZELOG2;\r |
| 6423 | cpu_clear();\r |
| 6424 | }\r |
| 6425 | return SCPE_OK;\r |
| 6426 | }\r |
| 6427 | \r |
| 6428 | #ifdef CPUSWITCHER\r |
| 6429 | static int32 switchcpu_io(const int32 port, const int32 io, const int32 data) {\r |
| 6430 | if (cpu_unit.flags & UNIT_CPU_VERBOSE) {\r |
| 6431 | MESSAGE_5("SWITCH(port=%02x, io=%i, data=%04x(%i)", port, io, data, data);\r |
| 6432 | }\r |
| 6433 | return 0;\r |
| 6434 | }\r |
| 6435 | \r |
| 6436 | static t_stat cpu_show_switcher(FILE *st, UNIT *uptr, int32 val, void *desc) {\r |
| 6437 | if ((cpu_unit.flags & UNIT_CPU_SWITCHER) && (switcherPort >= 0))\r |
| 6438 | fprintf(st, "SWITCHER=0x%02x", switcherPort);\r |
| 6439 | else fprintf(st, "NOSWITCHER");\r |
| 6440 | return SCPE_OK;\r |
| 6441 | }\r |
| 6442 | \r |
| 6443 | static t_stat cpu_set_switcher(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6444 | struct idev safe;\r |
| 6445 | switcherPort &= 0xff;\r |
| 6446 | safe = dev_table[switcherPort];\r |
| 6447 | if (sim_map_resource(switcherPort, 1, RESOURCE_TYPE_IO, &switchcpu_io, FALSE)) {\r |
| 6448 | printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, switcherPort);\r |
| 6449 | return SCPE_ARG;\r |
| 6450 | }\r |
| 6451 | oldSwitcherDevice = safe;\r |
| 6452 | return SCPE_OK;\r |
| 6453 | }\r |
| 6454 | \r |
| 6455 | static t_stat cpu_reset_switcher(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6456 | if (sim_map_resource(switcherPort, 1, RESOURCE_TYPE_IO, oldSwitcherDevice.routine, FALSE)) {\r |
| 6457 | printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, switcherPort);\r |
| 6458 | return SCPE_ARG;\r |
| 6459 | }\r |
| 6460 | return SCPE_OK;\r |
| 6461 | }\r |
| 6462 | #endif\r |
| 6463 | \r |
| 6464 | static t_stat cpu_set_ramtype(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6465 | \r |
| 6466 | if(value == ramtype) {\r |
| 6467 | printf("RAM Selection unchanged\n");\r |
| 6468 | return SCPE_OK;\r |
| 6469 | }\r |
| 6470 | \r |
| 6471 | switch(ramtype) {\r |
| 6472 | case 1:\r |
| 6473 | printf("Unmapping NorthStar HRAM\n");\r |
| 6474 | sim_map_resource(0xC0, 1, RESOURCE_TYPE_IO, &bankseldev, TRUE);\r |
| 6475 | break;\r |
| 6476 | case 2:\r |
| 6477 | printf("Unmapping Vector RAM\n");\r |
| 6478 | sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &bankseldev, TRUE);\r |
| 6479 | break;\r |
| 6480 | case 3:\r |
| 6481 | printf("Unmapping Cromemco RAM\n");\r |
| 6482 | /* sim_map_resource(0xC0, 1, RESOURCE_TYPE_IO, &bankseldev, TRUE);*/\r |
| 6483 | break;\r |
| 6484 | case 0:\r |
| 6485 | default:\r |
| 6486 | printf("Unmapping AltairZ80 RAM\n");\r |
| 6487 | break;\r |
| 6488 | }\r |
| 6489 | \r |
| 6490 | switch(value) {\r |
| 6491 | case 1:\r |
| 6492 | printf("NorthStar HRAM Selected\n");\r |
| 6493 | sim_map_resource(0xC0, 1, RESOURCE_TYPE_IO, &bankseldev, FALSE);\r |
| 6494 | break;\r |
| 6495 | case 2:\r |
| 6496 | printf("Vector RAM Selected\n");\r |
| 6497 | sim_map_resource(0x40, 1, RESOURCE_TYPE_IO, &bankseldev, FALSE);\r |
| 6498 | break;\r |
| 6499 | case 3:\r |
| 6500 | printf("Cromemco RAM Selected\n");\r |
| 6501 | /* sim_map_resource(0xC0, 1, RESOURCE_TYPE_IO, &bankseldev, FALSE);*/\r |
| 6502 | break;\r |
| 6503 | case 0:\r |
| 6504 | default:\r |
| 6505 | printf("AltairZ80 RAM Selected\n");\r |
| 6506 | break;\r |
| 6507 | }\r |
| 6508 | \r |
| 6509 | ramtype = value;\r |
| 6510 | return SCPE_OK;\r |
| 6511 | }\r |
| 6512 | \r |
| 6513 | /* set memory to 'size' kilo byte */\r |
| 6514 | static t_stat set_size(uint32 size) {\r |
| 6515 | uint32 maxsize = (((chiptype == CHIP_TYPE_8080) || (chiptype == CHIP_TYPE_Z80)) &&\r |
| 6516 | ((cpu_unit.flags & UNIT_CPU_BANKED) == 0)) ? MAXBANKSIZE : MAXMEMORY;\r |
| 6517 | size <<= KBLOG2;\r |
| 6518 | if (cpu_unit.flags & UNIT_CPU_BANKED) size &= ~ADDRMASK;\r |
| 6519 | cpu_unit.flags |= UNIT_CPU_MMU;\r |
| 6520 | if (size < KB) MEMORYSIZE = KB;\r |
| 6521 | else if (size > maxsize) MEMORYSIZE = maxsize;\r |
| 6522 | else MEMORYSIZE = size;\r |
| 6523 | cpu_dev.awidth = MAXBANKSIZELOG2;\r |
| 6524 | if (size > MAXBANKSIZE) cpu_dev.awidth += MAXBANKSLOG2;\r |
| 6525 | cpu_clear();\r |
| 6526 | return SCPE_OK;\r |
| 6527 | }\r |
| 6528 | \r |
| 6529 | static t_stat cpu_set_size(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6530 | return set_size(value);\r |
| 6531 | }\r |
| 6532 | \r |
| 6533 | static t_stat cpu_set_memory(UNIT *uptr, int32 value, char *cptr, void *desc) {\r |
| 6534 | uint32 size, result, i;\r |
| 6535 | if (cptr == NULL) return SCPE_ARG;\r |
| 6536 | result = sscanf(cptr, "%i%n", &size, &i);\r |
| 6537 | if ((result == 1) && (cptr[i] == 'K') && ((cptr[i + 1] == 0) ||\r |
| 6538 | (cptr[i + 1] == 'B') && (cptr[i + 2] == 0)))\r |
| 6539 | return set_size(size);\r |
| 6540 | return SCPE_ARG;\r |
| 6541 | }\r |
| 6542 | \r |
| 6543 | /* AltairZ80 Simulator initialization */\r |
| 6544 | void altairz80_init(void) {\r |
| 6545 | cpu_clear();\r |
| 6546 | }\r |
| 6547 | \r |
| 6548 | void (*sim_vm_init) (void) = &altairz80_init;\r |
| 6549 | \r |
| 6550 | /* This is the binary loader. The input file is considered to be a string of\r |
| 6551 | literal bytes with no special format. The load starts at the current value\r |
| 6552 | of the PC if no start address is given. If the input string ends with ROM\r |
| 6553 | (not case sensitive) the memory area is made read only.\r |
| 6554 | ALTAIRROM/NOALTAIRROM settings are ignored.\r |
| 6555 | */\r |
| 6556 | \r |
| 6557 | #define PLURAL(x) (x), (x) == 1 ? "" : "s"\r |
| 6558 | \r |
| 6559 | t_stat sim_load(FILE *fileref, char *cptr, char *fnam, int32 flag) {\r |
| 6560 | uint32 i, addr, cnt = 0, org, pagesModified = 0, makeROM = FALSE;\r |
| 6561 | t_addr j, lo, hi;\r |
| 6562 | char *result;\r |
| 6563 | MDEV m;\r |
| 6564 | char gbuf[CBUFSIZE];\r |
| 6565 | if (flag) {\r |
| 6566 | result = (chiptype == CHIP_TYPE_8086) ?\r |
| 6567 | get_range(NULL, cptr, &lo, &hi, 16, ADDRMASK | (BANKMASK << MAXBANKSIZELOG2), 0) :\r |
| 6568 | get_range(NULL, cptr, &lo, &hi, 16, ADDRMASK, 0);\r |
| 6569 | if (result == NULL) return SCPE_ARG;\r |
| 6570 | for (j = lo; j <= hi; j++) {\r |
| 6571 | if (putc((chiptype == CHIP_TYPE_8086) ? GetBYTEExtended(j) : GetBYTE(j), fileref) == EOF) return SCPE_IOERR;\r |
| 6572 | }\r |
| 6573 | printf("%d byte%s dumped [%x - %x].\n", PLURAL(hi + 1 - lo), lo, hi);\r |
| 6574 | }\r |
| 6575 | else {\r |
| 6576 | if (*cptr == 0) addr = PC_S;\r |
| 6577 | else {\r |
| 6578 | get_glyph(cptr, gbuf, 0);\r |
| 6579 | if (strcmp(gbuf, "ROM") == 0) {\r |
| 6580 | addr = PC_S;\r |
| 6581 | makeROM = TRUE;\r |
| 6582 | }\r |
| 6583 | else {\r |
| 6584 | addr = strtotv(cptr, &result, 16);\r |
| 6585 | if (cptr == result) return SCPE_ARG;\r |
| 6586 | while (isspace(*result)) result++;\r |
| 6587 | get_glyph(result, gbuf, 0);\r |
| 6588 | if (strcmp(gbuf, "ROM") == 0) makeROM = TRUE;\r |
| 6589 | }\r |
| 6590 | }\r |
| 6591 | /* addr is start address to load to, makeROM == TRUE iff memory should become ROM */\r |
| 6592 | org = addr;\r |
| 6593 | while ((addr < MAXMEMORY) && ((i = getc(fileref)) != EOF)) {\r |
| 6594 | m = mmu_table[addr >> LOG2PAGESIZE];\r |
| 6595 | if (!m.isRAM && m.isEmpty) {\r |
| 6596 | mmu_table[addr >> LOG2PAGESIZE] = RAM_PAGE;\r |
| 6597 | pagesModified++;\r |
| 6598 | m = RAM_PAGE;\r |
| 6599 | }\r |
| 6600 | if (makeROM) {\r |
| 6601 | mmu_table[addr >> LOG2PAGESIZE] = ROM_PAGE;\r |
| 6602 | m = ROM_PAGE;\r |
| 6603 | }\r |
| 6604 | if (!m.isRAM && m.routine) m.routine(addr, 1, i);\r |
| 6605 | else M[addr] = i;\r |
| 6606 | addr++;\r |
| 6607 | cnt++;\r |
| 6608 | } /* end while */\r |
| 6609 | printf("%d byte%s [%d page%s] loaded at %x%s.\n", PLURAL(cnt),\r |
| 6610 | PLURAL((cnt + 0xff) >> 8), org, makeROM ? " [ROM]" : "");\r |
| 6611 | if (pagesModified)\r |
| 6612 | printf("Warning: %d page%s modified.\n", PLURAL(pagesModified));\r |
| 6613 | }\r |
| 6614 | return SCPE_OK;\r |
| 6615 | }\r |