| 1 | /* hp2100_cpu.h: HP 2100 CPU definitions\r |
| 2 | \r |
| 3 | Copyright (c) 2005-2008, Robert M. Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not\r |
| 23 | be used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | 24-Apr-08 JDB Added calc_defer() prototype\r |
| 27 | 20-Apr-08 JDB Added DEB_VIS and DEB_SIG debug flags\r |
| 28 | 26-Nov-07 JDB Added extern sim_deb, cpu_dev, DEB flags for debug printouts\r |
| 29 | 05-Nov-07 JDB Added extern intaddr, mp_viol, mp_mevff, calc_int, dev_ctl,\r |
| 30 | ReadIO, WriteIO for RTE-6/VM microcode support\r |
| 31 | 16-Dec-06 JDB Added UNIT_2115 and UNIT_2114\r |
| 32 | 16-Oct-06 JDB Moved ReadF to hp2100_cpu1.c\r |
| 33 | 26-Sep-06 JDB Added CPU externs for microcode simulators\r |
| 34 | 16-Aug-06 JDB Added UNIT_EMA for future RTE-4 EMA microcode\r |
| 35 | Added UNIT_VMA for future RTE-6 VMA and OS microcode\r |
| 36 | Added UNIT_1000_F for future F-Series support\r |
| 37 | 09-Aug-06 JDB Added UNIT_DBI for double integer microcode\r |
| 38 | 21-Jan-05 JDB Reorganized CPU option flags\r |
| 39 | 14-Jan-05 RMS Cloned from hp2100_cpu.c\r |
| 40 | \r |
| 41 | CPU models are broken down into family, type, and series to facilitate option\r |
| 42 | validation. Bit 3 encodes the family, bit 2 encodes the type, and bits 1:0\r |
| 43 | encode the series within the type.\r |
| 44 | */\r |
| 45 | \r |
| 46 | #ifndef _HP2100_CPU_H_\r |
| 47 | #define _HP2100_CPU_H_ 0\r |
| 48 | \r |
| 49 | /* CPU model definition flags */\r |
| 50 | \r |
| 51 | #define CPU_V_SERIES 0\r |
| 52 | #define CPU_V_TYPE 2\r |
| 53 | #define CPU_V_FAMILY 3\r |
| 54 | \r |
| 55 | #define FAMILY_21XX (0 << CPU_V_FAMILY)\r |
| 56 | #define FAMILY_1000 (1 << CPU_V_FAMILY)\r |
| 57 | \r |
| 58 | #define TYPE_211X (0 << CPU_V_TYPE) /* 2114, 2115, 2116 */\r |
| 59 | #define TYPE_2100 (1 << CPU_V_TYPE) /* 2100A, 2100S */\r |
| 60 | #define TYPE_1000MEF (0 << CPU_V_TYPE) /* 1000-M, 1000-E, 1000-F */\r |
| 61 | #define TYPE_1000AL (1 << CPU_V_TYPE) /* 1000-L, A600, A700, A900, A990 */\r |
| 62 | \r |
| 63 | #define SERIES_16 (0 << CPU_V_SERIES) /* 211X */\r |
| 64 | #define SERIES_15 (1 << CPU_V_SERIES) /* 211X */\r |
| 65 | #define SERIES_14 (2 << CPU_V_SERIES) /* 211X */\r |
| 66 | #define SERIES_00 (0 << CPU_V_SERIES) /* 2100 */\r |
| 67 | #define SERIES_M (0 << CPU_V_SERIES) /* 1000 */\r |
| 68 | #define SERIES_E (1 << CPU_V_SERIES) /* 1000 */\r |
| 69 | #define SERIES_F (2 << CPU_V_SERIES) /* 1000 */\r |
| 70 | \r |
| 71 | /* CPU unit flags */\r |
| 72 | \r |
| 73 | #define UNIT_M_CPU 017 /* CPU model mask [3:0] */\r |
| 74 | #define UNIT_M_TYPE 014 /* CPU type mask [3:2] */\r |
| 75 | #define UNIT_M_FAMILY 010 /* CPU family mask [3:3] */\r |
| 76 | \r |
| 77 | #define UNIT_V_CPU (UNIT_V_UF + 0) /* CPU model bits 0-3 */\r |
| 78 | #define UNIT_V_EAU (UNIT_V_UF + 4) /* EAU installed */\r |
| 79 | #define UNIT_V_FP (UNIT_V_UF + 5) /* FP installed */\r |
| 80 | #define UNIT_V_IOP (UNIT_V_UF + 6) /* IOP installed */\r |
| 81 | #define UNIT_V_DMS (UNIT_V_UF + 7) /* DMS installed */\r |
| 82 | #define UNIT_V_FFP (UNIT_V_UF + 8) /* FFP installed */\r |
| 83 | #define UNIT_V_DBI (UNIT_V_UF + 9) /* DBI installed */\r |
| 84 | #define UNIT_V_EMA (UNIT_V_UF + 10) /* RTE-4 EMA installed */\r |
| 85 | #define UNIT_V_VMAOS (UNIT_V_UF + 11) /* RTE-6 VMA/OS installed */\r |
| 86 | #define UNIT_V_VIS (UNIT_V_UF + 12) /* VIS installed */\r |
| 87 | #define UNIT_V_SIGNAL (UNIT_V_UF + 13) /* SIGNAL/1000 installed */\r |
| 88 | /* Future microcode expansion; reuse flags bottom-up if needed */\r |
| 89 | #define UNIT_V_DS (UNIT_V_UF + 14) /* DS installed */\r |
| 90 | \r |
| 91 | /* Unit models */\r |
| 92 | \r |
| 93 | #define UNIT_MODEL_MASK (UNIT_M_CPU << UNIT_V_CPU)\r |
| 94 | \r |
| 95 | #define UNIT_2116 ((FAMILY_21XX | TYPE_211X | SERIES_16) << UNIT_V_CPU)\r |
| 96 | #define UNIT_2115 ((FAMILY_21XX | TYPE_211X | SERIES_15) << UNIT_V_CPU)\r |
| 97 | #define UNIT_2114 ((FAMILY_21XX | TYPE_211X | SERIES_14) << UNIT_V_CPU)\r |
| 98 | #define UNIT_2100 ((FAMILY_21XX | TYPE_2100 | SERIES_00) << UNIT_V_CPU)\r |
| 99 | #define UNIT_1000_M ((FAMILY_1000 | TYPE_1000MEF | SERIES_M) << UNIT_V_CPU)\r |
| 100 | #define UNIT_1000_E ((FAMILY_1000 | TYPE_1000MEF | SERIES_E) << UNIT_V_CPU)\r |
| 101 | #define UNIT_1000_F ((FAMILY_1000 | TYPE_1000MEF | SERIES_F) << UNIT_V_CPU)\r |
| 102 | \r |
| 103 | /* Unit types */\r |
| 104 | \r |
| 105 | #define UNIT_TYPE_MASK (UNIT_M_TYPE << UNIT_V_CPU)\r |
| 106 | \r |
| 107 | #define UNIT_TYPE_211X ((FAMILY_21XX | TYPE_211X) << UNIT_V_CPU)\r |
| 108 | #define UNIT_TYPE_2100 ((FAMILY_21XX | TYPE_2100) << UNIT_V_CPU)\r |
| 109 | #define UNIT_TYPE_1000 ((FAMILY_1000 | TYPE_1000MEF) << UNIT_V_CPU)\r |
| 110 | \r |
| 111 | /* Unit families */\r |
| 112 | \r |
| 113 | #define UNIT_FAMILY_MASK (UNIT_M_FAMILY << UNIT_V_CPU)\r |
| 114 | \r |
| 115 | #define UNIT_FAMILY_21XX (FAMILY_21XX << UNIT_V_CPU)\r |
| 116 | #define UNIT_FAMILY_1000 (FAMILY_1000 << UNIT_V_CPU)\r |
| 117 | \r |
| 118 | /* Unit accessors */\r |
| 119 | \r |
| 120 | #define UNIT_CPU_MODEL (cpu_unit.flags & UNIT_MODEL_MASK)\r |
| 121 | #define UNIT_CPU_TYPE (cpu_unit.flags & UNIT_TYPE_MASK)\r |
| 122 | #define UNIT_CPU_FAMILY (cpu_unit.flags & UNIT_FAMILY_MASK)\r |
| 123 | \r |
| 124 | #define CPU_MODEL_INDEX (UNIT_CPU_MODEL >> UNIT_V_CPU)\r |
| 125 | \r |
| 126 | /* Unit features */\r |
| 127 | \r |
| 128 | #define UNIT_EAU (1 << UNIT_V_EAU)\r |
| 129 | #define UNIT_FP (1 << UNIT_V_FP)\r |
| 130 | #define UNIT_IOP (1 << UNIT_V_IOP)\r |
| 131 | #define UNIT_DMS (1 << UNIT_V_DMS)\r |
| 132 | #define UNIT_FFP (1 << UNIT_V_FFP)\r |
| 133 | #define UNIT_DBI (1 << UNIT_V_DBI)\r |
| 134 | #define UNIT_EMA (1 << UNIT_V_EMA)\r |
| 135 | #define UNIT_VMAOS (1 << UNIT_V_VMAOS)\r |
| 136 | #define UNIT_VIS (1 << UNIT_V_VIS)\r |
| 137 | #define UNIT_DS (1 << UNIT_V_DS)\r |
| 138 | #define UNIT_SIGNAL (1 << UNIT_V_SIGNAL)\r |
| 139 | \r |
| 140 | #define UNIT_EMA_VMA (UNIT_EMA | UNIT_VMAOS)\r |
| 141 | \r |
| 142 | #define UNIT_OPTS (UNIT_EAU | UNIT_FP | UNIT_IOP | \\r |
| 143 | UNIT_DMS | UNIT_FFP | UNIT_DBI | \\r |
| 144 | UNIT_EMA | UNIT_VMAOS | \\r |
| 145 | UNIT_VIS | UNIT_DS | UNIT_SIGNAL)\r |
| 146 | \r |
| 147 | /* "Pseudo-option" flags used only for option testing; never set into UNIT structure. */\r |
| 148 | \r |
| 149 | #define UNIT_V_PFAIL (UNIT_V_UF - 1) /* Power fail installed */\r |
| 150 | #define UNIT_V_DMA (UNIT_V_UF - 2) /* DMA installed */\r |
| 151 | #define UNIT_V_MP (UNIT_V_UF - 3) /* Memory protect installed */\r |
| 152 | \r |
| 153 | #define UNIT_PFAIL (1 << UNIT_V_PFAIL)\r |
| 154 | #define UNIT_DMA (1 << UNIT_V_DMA)\r |
| 155 | #define UNIT_MP (1 << UNIT_V_MP)\r |
| 156 | \r |
| 157 | #define UNIT_NONE 0 /* no options */\r |
| 158 | \r |
| 159 | /* Debug flags */\r |
| 160 | \r |
| 161 | #define DEB_OS (1 << 0) /* RTE-6/VM OS firmware non-TBG processing */\r |
| 162 | #define DEB_OSTBG (1 << 1) /* RTE-6/VM OS firmware TBG processing */\r |
| 163 | #define DEB_VMA (1 << 2) /* RTE-6/VM VMA firmware instructions */\r |
| 164 | #define DEB_EMA (1 << 3) /* RTE-6/VM EMA firmware instructions */\r |
| 165 | #define DEB_VIS (1 << 4) /* E/F-Series VIS firmware instructions */\r |
| 166 | #define DEB_SIG (1 << 5) /* F-Series SIGNAL/1000 firmware instructions */\r |
| 167 | \r |
| 168 | /* PC queue. */\r |
| 169 | \r |
| 170 | #define PCQ_SIZE 64 /* must be 2**n */\r |
| 171 | #define PCQ_MASK (PCQ_SIZE - 1)\r |
| 172 | #define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = err_PC\r |
| 173 | \r |
| 174 | /* simulator state */\r |
| 175 | \r |
| 176 | extern FILE *sim_deb;\r |
| 177 | \r |
| 178 | /* CPU registers */\r |
| 179 | \r |
| 180 | extern uint16 ABREG[2]; /* A/B regs (use AR/BR) */\r |
| 181 | extern uint32 PC; /* P register */\r |
| 182 | extern uint32 SR; /* S register */\r |
| 183 | extern uint32 MR; /* M register */\r |
| 184 | extern uint32 TR; /* T register */\r |
| 185 | extern uint32 XR; /* X register */\r |
| 186 | extern uint32 YR; /* Y register */\r |
| 187 | extern uint32 E; /* E register */\r |
| 188 | extern uint32 O; /* O register */\r |
| 189 | extern uint32 dev_ctl[2]; /* device control */\r |
| 190 | \r |
| 191 | /* CPU state */\r |
| 192 | \r |
| 193 | extern uint32 err_PC;\r |
| 194 | extern uint32 dms_enb;\r |
| 195 | extern uint32 dms_ump;\r |
| 196 | extern uint32 dms_sr;\r |
| 197 | extern uint32 dms_vr;\r |
| 198 | extern uint32 mp_fence;\r |
| 199 | extern uint32 mp_viol;\r |
| 200 | extern uint32 mp_mevff;\r |
| 201 | extern uint32 iop_sp;\r |
| 202 | extern uint32 ion_defer;\r |
| 203 | extern uint32 intaddr;\r |
| 204 | extern uint16 pcq[PCQ_SIZE];\r |
| 205 | extern uint32 pcq_p;\r |
| 206 | extern uint32 stop_inst;\r |
| 207 | extern UNIT cpu_unit;\r |
| 208 | extern DEVICE cpu_dev;\r |
| 209 | \r |
| 210 | /* CPU functions */\r |
| 211 | \r |
| 212 | t_stat resolve (uint32 MA, uint32 *addr, uint32 irq);\r |
| 213 | uint8 ReadB (uint32 addr);\r |
| 214 | uint8 ReadBA (uint32 addr);\r |
| 215 | uint16 ReadW (uint32 addr);\r |
| 216 | uint16 ReadWA (uint32 addr);\r |
| 217 | uint16 ReadIO (uint32 addr, uint32 map);\r |
| 218 | void WriteB (uint32 addr, uint32 dat);\r |
| 219 | void WriteBA (uint32 addr, uint32 dat);\r |
| 220 | void WriteW (uint32 addr, uint32 dat);\r |
| 221 | void WriteWA (uint32 addr, uint32 dat);\r |
| 222 | void WriteIO (uint32 addr, uint32 dat, uint32 map);\r |
| 223 | t_stat iogrp (uint32 ir, uint32 iotrap);\r |
| 224 | uint32 calc_int (void);\r |
| 225 | uint32 calc_defer (void);\r |
| 226 | void mp_dms_jmp (uint32 va);\r |
| 227 | uint16 dms_rmap (uint32 mapi);\r |
| 228 | void dms_wmap (uint32 mapi, uint32 dat);\r |
| 229 | void dms_viol (uint32 va, uint32 st);\r |
| 230 | uint32 dms_upd_sr (void);\r |
| 231 | \r |
| 232 | #endif\r |