| 1 | /* hp2100_cpu1.h: HP 2100/1000 firmware dispatcher definitions\r |
| 2 | \r |
| 3 | Copyright (c) 2006-2008, J. David Bryan\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of the author shall not\r |
| 23 | be used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from the author.\r |
| 25 | \r |
| 26 | 30-Apr-08 JDB Corrected OP_AFF to OP_AAFF for SIGNAL/1000\r |
| 27 | Removed unused operand patterns\r |
| 28 | 23-Feb-08 HV Added more OP_* for SIGNAL/1000 and VIS\r |
| 29 | 28-Nov-07 JDB Added fprint_ops, fprint_regs for debug printouts\r |
| 30 | 19-Oct-07 JDB Revised OP_KKKAKK operand profile to OP_CCCACC for $LOC\r |
| 31 | 16-Oct-06 JDB Generalized operands for F-Series FP types\r |
| 32 | 26-Sep-06 JDB Split from hp2100_cpu1.c\r |
| 33 | */\r |
| 34 | \r |
| 35 | #ifndef _HP2100_CPU1_H_\r |
| 36 | #define _HP2100_CPU1_H_\r |
| 37 | \r |
| 38 | \r |
| 39 | /* Register print encoding. */\r |
| 40 | \r |
| 41 | #define REG_COUNT 9 /* count of print flags */\r |
| 42 | \r |
| 43 | #define REG_CIR (1 << 0) /* print central interrupt register */\r |
| 44 | #define REG_A (1 << 1) /* print A register */\r |
| 45 | #define REG_B (1 << 2) /* print B register */\r |
| 46 | #define REG_E (1 << 3) /* print E register */\r |
| 47 | #define REG_X (1 << 4) /* print X register */\r |
| 48 | #define REG_Y (1 << 5) /* print Y register */\r |
| 49 | #define REG_O (1 << 6) /* print O register */\r |
| 50 | #define REG_P (1 << 7) /* print P register */\r |
| 51 | #define REG_P_REL (1 << 8) /* print P register as relative */\r |
| 52 | \r |
| 53 | \r |
| 54 | /* Operand processing encoding. */\r |
| 55 | \r |
| 56 | /* Base operand types. Note that all address encodings must be grouped together\r |
| 57 | after OP_ADR. */\r |
| 58 | \r |
| 59 | #define OP_NUL 0 /* no operand */\r |
| 60 | #define OP_IAR 1 /* 1-word int in A reg */\r |
| 61 | #define OP_JAB 2 /* 2-word int in A/B regs */\r |
| 62 | #define OP_FAB 3 /* 2-word FP const in A/B regs */\r |
| 63 | #define OP_CON 4 /* inline 1-word constant */\r |
| 64 | #define OP_VAR 5 /* inline 1-word variable */\r |
| 65 | \r |
| 66 | #define OP_ADR 6 /* inline address */\r |
| 67 | #define OP_ADK 7 /* addr of 1-word int const */\r |
| 68 | #define OP_ADD 8 /* addr of 2-word int const */\r |
| 69 | #define OP_ADF 9 /* addr of 2-word FP const */\r |
| 70 | #define OP_ADX 10 /* addr of 3-word FP const */\r |
| 71 | #define OP_ADT 11 /* addr of 4-word FP const */\r |
| 72 | #define OP_ADE 12 /* addr of 5-word FP const */\r |
| 73 | \r |
| 74 | #define OP_N_FLAGS 4 /* number of bits needed for flags */\r |
| 75 | #define OP_M_FLAGS ((1 << OP_N_FLAGS) - 1) /* mask for flag bits */\r |
| 76 | \r |
| 77 | #define OP_N_F (8 * sizeof (uint32) / OP_N_FLAGS) /* max number of op fields */\r |
| 78 | \r |
| 79 | #define OP_V_F1 (0 * OP_N_FLAGS) /* 1st operand field */\r |
| 80 | #define OP_V_F2 (1 * OP_N_FLAGS) /* 2nd operand field */\r |
| 81 | #define OP_V_F3 (2 * OP_N_FLAGS) /* 3rd operand field */\r |
| 82 | #define OP_V_F4 (3 * OP_N_FLAGS) /* 4th operand field */\r |
| 83 | #define OP_V_F5 (4 * OP_N_FLAGS) /* 5th operand field */\r |
| 84 | #define OP_V_F6 (5 * OP_N_FLAGS) /* 6th operand field */\r |
| 85 | #define OP_V_F7 (6 * OP_N_FLAGS) /* 7th operand field */\r |
| 86 | #define OP_V_F8 (7 * OP_N_FLAGS) /* 8th operand field */\r |
| 87 | \r |
| 88 | /* Operand processing patterns. */\r |
| 89 | \r |
| 90 | #define OP_N (OP_NUL << OP_V_F1)\r |
| 91 | #define OP_I (OP_IAR << OP_V_F1)\r |
| 92 | #define OP_J (OP_JAB << OP_V_F1)\r |
| 93 | #define OP_R (OP_FAB << OP_V_F1)\r |
| 94 | #define OP_C (OP_CON << OP_V_F1)\r |
| 95 | #define OP_V (OP_VAR << OP_V_F1)\r |
| 96 | #define OP_A (OP_ADR << OP_V_F1)\r |
| 97 | #define OP_K (OP_ADK << OP_V_F1)\r |
| 98 | #define OP_D (OP_ADD << OP_V_F1)\r |
| 99 | #define OP_X (OP_ADX << OP_V_F1)\r |
| 100 | #define OP_T (OP_ADT << OP_V_F1)\r |
| 101 | #define OP_E (OP_ADE << OP_V_F1)\r |
| 102 | \r |
| 103 | #define OP_IA ((OP_IAR << OP_V_F1) | (OP_ADR << OP_V_F2))\r |
| 104 | #define OP_JA ((OP_JAB << OP_V_F1) | (OP_ADR << OP_V_F2))\r |
| 105 | #define OP_JD ((OP_JAB << OP_V_F1) | (OP_ADD << OP_V_F2))\r |
| 106 | #define OP_RC ((OP_FAB << OP_V_F1) | (OP_CON << OP_V_F2))\r |
| 107 | #define OP_RK ((OP_FAB << OP_V_F1) | (OP_ADK << OP_V_F2))\r |
| 108 | #define OP_RF ((OP_FAB << OP_V_F1) | (OP_ADF << OP_V_F2))\r |
| 109 | #define OP_CV ((OP_CON << OP_V_F1) | (OP_VAR << OP_V_F2))\r |
| 110 | #define OP_AC ((OP_ADR << OP_V_F1) | (OP_CON << OP_V_F2))\r |
| 111 | #define OP_AA ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2))\r |
| 112 | #define OP_AK ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2))\r |
| 113 | #define OP_AX ((OP_ADR << OP_V_F1) | (OP_ADX << OP_V_F2))\r |
| 114 | #define OP_AT ((OP_ADR << OP_V_F1) | (OP_ADT << OP_V_F2))\r |
| 115 | #define OP_KV ((OP_ADK << OP_V_F1) | (OP_VAR << OP_V_F2))\r |
| 116 | #define OP_KA ((OP_ADK << OP_V_F1) | (OP_ADR << OP_V_F2))\r |
| 117 | #define OP_KK ((OP_ADK << OP_V_F1) | (OP_ADK << OP_V_F2))\r |
| 118 | \r |
| 119 | #define OP_IIF ((OP_IAR << OP_V_F1) | (OP_IAR << OP_V_F2) | \\r |
| 120 | (OP_ADF << OP_V_F3))\r |
| 121 | \r |
| 122 | #define OP_IAT ((OP_IAR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 123 | (OP_ADT << OP_V_F3))\r |
| 124 | \r |
| 125 | #define OP_CVA ((OP_CON << OP_V_F1) | (OP_VAR << OP_V_F2) | \\r |
| 126 | (OP_ADR << OP_V_F3))\r |
| 127 | \r |
| 128 | #define OP_AAA ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 129 | (OP_ADR << OP_V_F3))\r |
| 130 | \r |
| 131 | #define OP_AAF ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 132 | (OP_ADF << OP_V_F3))\r |
| 133 | \r |
| 134 | #define OP_AAX ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 135 | (OP_ADX << OP_V_F3))\r |
| 136 | \r |
| 137 | #define OP_AAT ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 138 | (OP_ADT << OP_V_F3))\r |
| 139 | \r |
| 140 | #define OP_AKA ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \\r |
| 141 | (OP_ADR << OP_V_F3))\r |
| 142 | \r |
| 143 | #define OP_AKK ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \\r |
| 144 | (OP_ADK << OP_V_F3))\r |
| 145 | \r |
| 146 | #define OP_AXX ((OP_ADR << OP_V_F1) | (OP_ADX << OP_V_F2) | \\r |
| 147 | (OP_ADX << OP_V_F3))\r |
| 148 | \r |
| 149 | #define OP_ATT ((OP_ADR << OP_V_F1) | (OP_ADT << OP_V_F2) | \\r |
| 150 | (OP_ADT << OP_V_F3))\r |
| 151 | \r |
| 152 | #define OP_AEE ((OP_ADR << OP_V_F1) | (OP_ADE << OP_V_F2) | \\r |
| 153 | (OP_ADE << OP_V_F3))\r |
| 154 | \r |
| 155 | #define OP_AAXX ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 156 | (OP_ADX << OP_V_F3) | (OP_ADX << OP_V_F4))\r |
| 157 | \r |
| 158 | #define OP_AAFF ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 159 | (OP_ADF << OP_V_F3) | (OP_ADF << OP_V_F4))\r |
| 160 | \r |
| 161 | #define OP_AAKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 162 | (OP_ADK << OP_V_F3) | (OP_ADK << OP_V_F4))\r |
| 163 | \r |
| 164 | #define OP_KKKK ((OP_ADK << OP_V_F1) | (OP_ADK << OP_V_F2) | \\r |
| 165 | (OP_ADK << OP_V_F3) | (OP_ADK << OP_V_F4))\r |
| 166 | \r |
| 167 | #define OP_AAAKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 168 | (OP_ADR << OP_V_F3) | (OP_ADK << OP_V_F4) | \\r |
| 169 | (OP_ADK << OP_V_F5))\r |
| 170 | \r |
| 171 | #define OP_AKAKK ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \\r |
| 172 | (OP_ADR << OP_V_F3) | (OP_ADK << OP_V_F4) | \\r |
| 173 | (OP_ADK << OP_V_F5))\r |
| 174 | \r |
| 175 | #define OP_AAACCC ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 176 | (OP_ADR << OP_V_F3) | (OP_CON << OP_V_F4) | \\r |
| 177 | (OP_CON << OP_V_F5) | (OP_CON << OP_V_F6))\r |
| 178 | \r |
| 179 | #define OP_AAFFKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 180 | (OP_ADF << OP_V_F3) | (OP_ADF << OP_V_F4) | \\r |
| 181 | (OP_ADK << OP_V_F5) | (OP_ADK << OP_V_F6))\r |
| 182 | \r |
| 183 | #define OP_AAKAKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 184 | (OP_ADK << OP_V_F3) | (OP_ADR << OP_V_F4) | \\r |
| 185 | (OP_ADK << OP_V_F5) | (OP_ADK << OP_V_F6))\r |
| 186 | \r |
| 187 | #define OP_CATAKK ((OP_CON << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 188 | (OP_ADT << OP_V_F3) | (OP_ADR << OP_V_F4) | \\r |
| 189 | (OP_ADK << OP_V_F5) | (OP_ADK << OP_V_F6))\r |
| 190 | \r |
| 191 | #define OP_CCCACC ((OP_CON << OP_V_F1) | (OP_CON << OP_V_F2) | \\r |
| 192 | (OP_CON << OP_V_F3) | (OP_ADR << OP_V_F4) | \\r |
| 193 | (OP_CON << OP_V_F5) | (OP_CON << OP_V_F6))\r |
| 194 | \r |
| 195 | #define OP_AAAFFKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 196 | (OP_ADR << OP_V_F3) | (OP_ADF << OP_V_F4) | \\r |
| 197 | (OP_ADF << OP_V_F5) | (OP_ADK << OP_V_F6) | \\r |
| 198 | (OP_ADK << OP_V_F7))\r |
| 199 | \r |
| 200 | #define OP_AKAKAKK ((OP_ADR << OP_V_F1) | (OP_ADK << OP_V_F2) | \\r |
| 201 | (OP_ADR << OP_V_F3) | (OP_ADK << OP_V_F4) | \\r |
| 202 | (OP_ADR << OP_V_F5) | (OP_ADK << OP_V_F6) | \\r |
| 203 | (OP_ADK << OP_V_F7))\r |
| 204 | \r |
| 205 | #define OP_AAKAKAKK ((OP_ADR << OP_V_F1) | (OP_ADR << OP_V_F2) | \\r |
| 206 | (OP_ADK << OP_V_F3) | (OP_ADR << OP_V_F4) | \\r |
| 207 | (OP_ADK << OP_V_F5) | (OP_ADR << OP_V_F6) | \\r |
| 208 | (OP_ADK << OP_V_F7) | (OP_ADK << OP_V_F8))\r |
| 209 | \r |
| 210 | #define OP_CCACACCA ((OP_CON << OP_V_F1) | (OP_CON << OP_V_F2) | \\r |
| 211 | (OP_ADR << OP_V_F3) | (OP_CON << OP_V_F4) | \\r |
| 212 | (OP_ADR << OP_V_F5) | (OP_CON << OP_V_F6) | \\r |
| 213 | (OP_CON << OP_V_F7) | (OP_ADR << OP_V_F8))\r |
| 214 | \r |
| 215 | \r |
| 216 | /* Operand precisions (compatible with F-Series FPP):\r |
| 217 | \r |
| 218 | - S = 1-word integer\r |
| 219 | - D = 2-word integer\r |
| 220 | - F = 2-word single-precision floating-point\r |
| 221 | - X = 3-word extended-precision floating-point\r |
| 222 | - T = 4-word double-precision floating-point\r |
| 223 | - E = 5-word expanded-exponent floating-point\r |
| 224 | - A = null operand (operand is in FPP accumulator)\r |
| 225 | \r |
| 226 | 5-word floating-point numbers are supported by the F-Series Floating-Point\r |
| 227 | Processor hardware, but the instruction codes are not documented.\r |
| 228 | \r |
| 229 | Note that ordering is important, as we depend on the "fp" type codes to\r |
| 230 | reflect the number of words needed.\r |
| 231 | */\r |
| 232 | \r |
| 233 | typedef enum { in_s, in_d, fp_f, fp_x, fp_t, fp_e, fp_a } OPSIZE;\r |
| 234 | \r |
| 235 | \r |
| 236 | /* Conversion from operand size to word count. */\r |
| 237 | \r |
| 238 | #define TO_COUNT(s) ((s == fp_a) ? 0 : (uint32) (s + (s < fp_f)))\r |
| 239 | \r |
| 240 | \r |
| 241 | /* HP in-memory representation of a packed floating-point number.\r |
| 242 | Actual value will use two, three, four, or five words, as needed. */\r |
| 243 | \r |
| 244 | typedef uint16 FPK[5];\r |
| 245 | \r |
| 246 | \r |
| 247 | /* Operand processing types.\r |
| 248 | \r |
| 249 | NOTE: Microsoft VC++ 6.0 does not support the C99 standard, so we cannot\r |
| 250 | initialize unions by arbitrary variant ("designated initializers").\r |
| 251 | Therefore, we follow the C90 form of initializing via the first named\r |
| 252 | variant. The FPK variant must appear first in the OP structure, as we define\r |
| 253 | a number of FPK constants in other modules.\r |
| 254 | */\r |
| 255 | \r |
| 256 | typedef union { /* general operand */\r |
| 257 | FPK fpk; /* floating-point value */\r |
| 258 | uint16 word; /* 16-bit integer */\r |
| 259 | uint32 dword; /* 32-bit integer */\r |
| 260 | } OP;\r |
| 261 | \r |
| 262 | typedef OP OPS[OP_N_F]; /* operand array */\r |
| 263 | \r |
| 264 | typedef uint32 OP_PAT; /* operand pattern */\r |
| 265 | \r |
| 266 | \r |
| 267 | /* Microcode dispatcher functions. */\r |
| 268 | \r |
| 269 | t_stat cpu_eau (uint32 IR, uint32 intrq); /* EAU group simulator */\r |
| 270 | t_stat cpu_uig_0 (uint32 IR, uint32 intrq, uint32 iotrap); /* UIG group 0 dispatcher */\r |
| 271 | t_stat cpu_uig_1 (uint32 IR, uint32 intrq, uint32 iotrap); /* UIG group 1 dispatcher */\r |
| 272 | \r |
| 273 | /* Microcode helper functions. */\r |
| 274 | \r |
| 275 | OP ReadOp (uint32 va, OPSIZE precision); /* generalized operand read */\r |
| 276 | void WriteOp (uint32 va, OP operand, OPSIZE precision); /* generalized operand write */\r |
| 277 | t_stat cpu_ops (OP_PAT pattern, OPS op, uint32 irq); /* operand processor */\r |
| 278 | \r |
| 279 | void fprint_ops (OP_PAT pattern, OPS op); /* debug print operands */\r |
| 280 | void fprint_regs (char *caption, uint32 regs, uint32 base); /* debug print CPU registers */\r |
| 281 | \r |
| 282 | #endif\r |