| 1 | /* hp2100_stddev.c: HP2100 standard devices simulator\r |
| 2 | \r |
| 3 | Copyright (c) 1993-2008, Robert M. Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | ptr 12597A-002 paper tape reader interface\r |
| 27 | ptp 12597A-005 paper tape punch interface\r |
| 28 | tty 12531C buffered teleprinter interface\r |
| 29 | clk 12539C time base generator\r |
| 30 | \r |
| 31 | 25-Apr-08 JDB Changed TTY output wait from 100 to 200 for MSU BASIC\r |
| 32 | 18-Apr-08 JDB Removed redundant control char handling definitions\r |
| 33 | 14-Apr-08 JDB Changed TTY console poll to 10 msec. real time\r |
| 34 | Synchronized CLK with TTY if set for 10 msec.\r |
| 35 | Added UNIT_IDLE to TTY and CLK\r |
| 36 | 09-Jan-08 JDB Fixed PTR trailing null counter for tape re-read\r |
| 37 | 31-Dec-07 JDB Added IPTICK register to CLK to display CPU instr/tick\r |
| 38 | Corrected and verified ioCRS actions\r |
| 39 | 28-Dec-06 JDB Added ioCRS state to I/O decoders\r |
| 40 | 22-Nov-05 RMS Revised for new terminal processing routines\r |
| 41 | 13-Sep-04 JDB Added paper tape loop mode, DIAG/READER modifiers to PTR\r |
| 42 | Added PV_LEFT to PTR TRLLIM register\r |
| 43 | Modified CLK to permit disable\r |
| 44 | 15-Aug-04 RMS Added tab to control char set (from Dave Bryan)\r |
| 45 | 14-Jul-04 RMS Generalized handling of control char echoing\r |
| 46 | (from Dave Bryan)\r |
| 47 | 26-Apr-04 RMS Fixed SFS x,C and SFC x,C\r |
| 48 | Fixed SR setting in IBL\r |
| 49 | Fixed input behavior during typeout for RTE-IV\r |
| 50 | Suppressed nulls on TTY output for RTE-IV\r |
| 51 | Implemented DMA SRQ (follows FLG)\r |
| 52 | 29-Mar-03 RMS Added support for console backpressure\r |
| 53 | 25-Apr-03 RMS Added extended file support\r |
| 54 | 22-Dec-02 RMS Added break support\r |
| 55 | 01-Nov-02 RMS Revised BOOT command for IBL ROMs\r |
| 56 | Fixed bug in TTY reset, TTY starts in input mode\r |
| 57 | Fixed bug in TTY mode OTA, stores data as well\r |
| 58 | Fixed clock to add calibration, proper start/stop\r |
| 59 | Added UC option to TTY output\r |
| 60 | 30-May-02 RMS Widened POS to 32b\r |
| 61 | 22-Mar-02 RMS Revised for dynamically allocated memory\r |
| 62 | 03-Nov-01 RMS Changed DEVNO to use extended SET/SHOW\r |
| 63 | 29-Nov-01 RMS Added read only unit support\r |
| 64 | 24-Nov-01 RMS Changed TIME to an array\r |
| 65 | 07-Sep-01 RMS Moved function prototypes\r |
| 66 | 21-Nov-00 RMS Fixed flag, buffer power up state\r |
| 67 | Added status input for ptp, tty\r |
| 68 | 15-Oct-00 RMS Added dynamic device number support\r |
| 69 | \r |
| 70 | The reader and punch, like most HP devices, have a command flop. The\r |
| 71 | teleprinter and clock do not.\r |
| 72 | \r |
| 73 | Reader diagnostic mode simulates a tape loop by rewinding the tape image file\r |
| 74 | upon EOF. Normal mode EOF action is to supply TRLLIM nulls and then either\r |
| 75 | return SCPE_IOERR or SCPE_OK without setting the device flag.\r |
| 76 | \r |
| 77 | To support CPU idling, the teleprinter interface (which doubles as the\r |
| 78 | simulator console) polls for input using a calibrated timer with a ten\r |
| 79 | millisecond period. Other polled-keyboard input devices (multiplexers and\r |
| 80 | the BACI card) synchronize with the console poll to ensure maximum available\r |
| 81 | idle time. The console poll is guaranteed to run, as the TTY device cannot\r |
| 82 | be disabled.\r |
| 83 | \r |
| 84 | The clock (time base generator) autocalibrates. If the CLK is set to a ten\r |
| 85 | millisecond period (e.g., as under RTE), it is synchronized to the console\r |
| 86 | poll. Otherwise (e.g., as under DOS or TSB, which use 100 millisecond\r |
| 87 | periods), it runs asynchronously. If the specified clock frequency is below\r |
| 88 | 10Hz, the clock service routine runs at 10Hz and counts down a repeat counter\r |
| 89 | before generating an interrupt. Autocalibration will not work if the clock\r |
| 90 | is running at 1Hz or less.\r |
| 91 | \r |
| 92 | Clock diagnostic mode corresponds to inserting jumper W2 on the 12539C.\r |
| 93 | This turns off autocalibration and divides the longest time intervals down\r |
| 94 | by 10**3. The clk_time values were chosen to allow the diagnostic to\r |
| 95 | pass its clock calibration test.\r |
| 96 | \r |
| 97 | References:\r |
| 98 | - 2748B Tape Reader Operating and Service Manual (02748-90041, Oct-1977)\r |
| 99 | - 12597A 8-Bit Duplex Register Interface Kit Operating and Service Manual\r |
| 100 | (12597-9002, Sep-1974)\r |
| 101 | - 12531C Buffered Teleprinter Interface Kit Operating and Service Manual\r |
| 102 | (12531-90033, Nov-1972)\r |
| 103 | - 12539C Time Base Generator Interface Kit Operating and Service Manual\r |
| 104 | (12539-90008, Jan-1975)\r |
| 105 | */\r |
| 106 | \r |
| 107 | #include "hp2100_defs.h"\r |
| 108 | \r |
| 109 | #define TTY_OUT_WAIT 200 /* TTY output wait */\r |
| 110 | \r |
| 111 | #define UNIT_V_DIAG (TTUF_V_UF + 0) /* diag mode */\r |
| 112 | #define UNIT_V_AUTOLF (TTUF_V_UF + 1) /* auto linefeed */\r |
| 113 | #define UNIT_DIAG (1 << UNIT_V_DIAG)\r |
| 114 | #define UNIT_AUTOLF (1 << UNIT_V_AUTOLF)\r |
| 115 | \r |
| 116 | #define PTP_LOW 0000040 /* low tape */\r |
| 117 | #define TM_MODE 0100000 /* mode change */\r |
| 118 | #define TM_KBD 0040000 /* enable keyboard */\r |
| 119 | #define TM_PRI 0020000 /* enable printer */\r |
| 120 | #define TM_PUN 0010000 /* enable punch */\r |
| 121 | #define TP_BUSY 0100000 /* busy */\r |
| 122 | \r |
| 123 | #define CLK_V_ERROR 4 /* clock overrun */\r |
| 124 | #define CLK_ERROR (1 << CLK_V_ERROR)\r |
| 125 | \r |
| 126 | extern uint32 PC, SR;\r |
| 127 | extern uint32 dev_cmd[2], dev_ctl[2], dev_flg[2], dev_fbf[2], dev_srq[2];\r |
| 128 | \r |
| 129 | int32 ptr_stopioe = 0; /* stop on error */\r |
| 130 | int32 ptr_trlcnt = 0; /* trailer counter */\r |
| 131 | int32 ptr_trllim = 40; /* trailer to add */\r |
| 132 | int32 ptp_stopioe = 0;\r |
| 133 | int32 ttp_stopioe = 0;\r |
| 134 | int32 tty_buf = 0; /* tty buffer */\r |
| 135 | int32 tty_mode = 0; /* tty mode */\r |
| 136 | int32 tty_shin = 0377; /* tty shift in */\r |
| 137 | int32 tty_lf = 0; /* lf flag */\r |
| 138 | int32 clk_select = 0; /* clock time select */\r |
| 139 | int32 clk_error = 0; /* clock error */\r |
| 140 | int32 clk_ctr = 0; /* clock counter */\r |
| 141 | int32 clk_time[8] = { /* clock intervals */\r |
| 142 | 155, 1550, 15500, 155000, 155000, 155000, 155000, 155000\r |
| 143 | };\r |
| 144 | int32 clk_tps[8] = { /* clock tps */\r |
| 145 | 10000, 1000, 100, 10, 10, 10, 10, 10\r |
| 146 | };\r |
| 147 | int32 clk_rpt[8] = { /* number of repeats */\r |
| 148 | 1, 1, 1, 1, 10, 100, 1000, 10000\r |
| 149 | };\r |
| 150 | uint32 clk_tick = 0; /* instructions per tick */\r |
| 151 | \r |
| 152 | DEVICE ptr_dev, ptp_dev, tty_dev, clk_dev;\r |
| 153 | int32 ptrio (int32 inst, int32 IR, int32 dat);\r |
| 154 | t_stat ptr_svc (UNIT *uptr);\r |
| 155 | t_stat ptr_attach (UNIT *uptr, char *cptr);\r |
| 156 | t_stat ptr_reset (DEVICE *dptr);\r |
| 157 | t_stat ptr_boot (int32 unitno, DEVICE *dptr);\r |
| 158 | int32 ptpio (int32 inst, int32 IR, int32 dat);\r |
| 159 | t_stat ptp_svc (UNIT *uptr);\r |
| 160 | t_stat ptp_reset (DEVICE *dptr);\r |
| 161 | int32 ttyio (int32 inst, int32 IR, int32 dat);\r |
| 162 | t_stat tti_svc (UNIT *uptr);\r |
| 163 | t_stat tto_svc (UNIT *uptr);\r |
| 164 | t_stat tty_reset (DEVICE *dptr);\r |
| 165 | t_stat tty_set_opt (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 166 | t_stat tty_set_alf (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 167 | int32 clkio (int32 inst, int32 IR, int32 dat);\r |
| 168 | t_stat clk_svc (UNIT *uptr);\r |
| 169 | t_stat clk_reset (DEVICE *dptr);\r |
| 170 | int32 clk_delay (int32 flg);\r |
| 171 | t_stat tto_out (int32 c);\r |
| 172 | t_stat ttp_out (int32 c);\r |
| 173 | \r |
| 174 | /* PTR data structures\r |
| 175 | \r |
| 176 | ptr_dev PTR device descriptor\r |
| 177 | ptr_unit PTR unit descriptor\r |
| 178 | ptr_mod PTR modifiers\r |
| 179 | ptr_reg PTR register list\r |
| 180 | */\r |
| 181 | \r |
| 182 | DIB ptr_dib = { PTR, 0, 0, 0, 0, 0, &ptrio };\r |
| 183 | \r |
| 184 | UNIT ptr_unit = {\r |
| 185 | UDATA (&ptr_svc, UNIT_SEQ+UNIT_ATTABLE+UNIT_ROABLE, 0),\r |
| 186 | SERIAL_IN_WAIT\r |
| 187 | };\r |
| 188 | \r |
| 189 | REG ptr_reg[] = {\r |
| 190 | { ORDATA (BUF, ptr_unit.buf, 8) },\r |
| 191 | { FLDATA (CMD, ptr_dib.cmd, 0) },\r |
| 192 | { FLDATA (CTL, ptr_dib.ctl, 0) },\r |
| 193 | { FLDATA (FLG, ptr_dib.flg, 0) },\r |
| 194 | { FLDATA (FBF, ptr_dib.fbf, 0) },\r |
| 195 | { FLDATA (SRQ, ptr_dib.srq, 0) },\r |
| 196 | { DRDATA (TRLCTR, ptr_trlcnt, 8), REG_HRO },\r |
| 197 | { DRDATA (TRLLIM, ptr_trllim, 8), PV_LEFT },\r |
| 198 | { DRDATA (POS, ptr_unit.pos, T_ADDR_W), PV_LEFT },\r |
| 199 | { DRDATA (TIME, ptr_unit.wait, 24), PV_LEFT },\r |
| 200 | { FLDATA (STOP_IOE, ptr_stopioe, 0) },\r |
| 201 | { ORDATA (DEVNO, ptr_dib.devno, 6), REG_HRO },\r |
| 202 | { NULL }\r |
| 203 | };\r |
| 204 | \r |
| 205 | MTAB ptr_mod[] = {\r |
| 206 | { UNIT_DIAG, UNIT_DIAG, "diagnostic mode", "DIAG", NULL },\r |
| 207 | { UNIT_DIAG, 0, "reader mode", "READER", NULL },\r |
| 208 | { MTAB_XTD | MTAB_VDV, 0, "DEVNO", "DEVNO",\r |
| 209 | &hp_setdev, &hp_showdev, &ptr_dev },\r |
| 210 | { 0 }\r |
| 211 | };\r |
| 212 | \r |
| 213 | DEVICE ptr_dev = {\r |
| 214 | "PTR", &ptr_unit, ptr_reg, ptr_mod,\r |
| 215 | 1, 10, 31, 1, 8, 8,\r |
| 216 | NULL, NULL, &ptr_reset,\r |
| 217 | &ptr_boot, &ptr_attach, NULL,\r |
| 218 | &ptr_dib, DEV_DISABLE\r |
| 219 | };\r |
| 220 | \r |
| 221 | /* PTP data structures\r |
| 222 | \r |
| 223 | ptp_dev PTP device descriptor\r |
| 224 | ptp_unit PTP unit descriptor\r |
| 225 | ptp_mod PTP modifiers\r |
| 226 | ptp_reg PTP register list\r |
| 227 | */\r |
| 228 | \r |
| 229 | DIB ptp_dib = { PTP, 0, 0, 0, 0, 0, &ptpio };\r |
| 230 | \r |
| 231 | UNIT ptp_unit = {\r |
| 232 | UDATA (&ptp_svc, UNIT_SEQ+UNIT_ATTABLE, 0), SERIAL_OUT_WAIT\r |
| 233 | };\r |
| 234 | \r |
| 235 | REG ptp_reg[] = {\r |
| 236 | { ORDATA (BUF, ptp_unit.buf, 8) },\r |
| 237 | { FLDATA (CMD, ptp_dib.cmd, 0) },\r |
| 238 | { FLDATA (CTL, ptp_dib.ctl, 0) },\r |
| 239 | { FLDATA (FLG, ptp_dib.flg, 0) },\r |
| 240 | { FLDATA (FBF, ptp_dib.fbf, 0) },\r |
| 241 | { FLDATA (SRQ, ptp_dib.srq, 0) },\r |
| 242 | { DRDATA (POS, ptp_unit.pos, T_ADDR_W), PV_LEFT },\r |
| 243 | { DRDATA (TIME, ptp_unit.wait, 24), PV_LEFT },\r |
| 244 | { FLDATA (STOP_IOE, ptp_stopioe, 0) },\r |
| 245 | { ORDATA (DEVNO, ptp_dib.devno, 6), REG_HRO },\r |
| 246 | { NULL }\r |
| 247 | };\r |
| 248 | \r |
| 249 | MTAB ptp_mod[] = {\r |
| 250 | { MTAB_XTD | MTAB_VDV, 0, "DEVNO", "DEVNO",\r |
| 251 | &hp_setdev, &hp_showdev, &ptp_dev },\r |
| 252 | { 0 }\r |
| 253 | };\r |
| 254 | \r |
| 255 | DEVICE ptp_dev = {\r |
| 256 | "PTP", &ptp_unit, ptp_reg, ptp_mod,\r |
| 257 | 1, 10, 31, 1, 8, 8,\r |
| 258 | NULL, NULL, &ptp_reset,\r |
| 259 | NULL, NULL, NULL,\r |
| 260 | &ptp_dib, DEV_DISABLE\r |
| 261 | };\r |
| 262 | \r |
| 263 | /* TTY data structures\r |
| 264 | \r |
| 265 | tty_dev TTY device descriptor\r |
| 266 | tty_unit TTY unit descriptor\r |
| 267 | tty_reg TTY register list\r |
| 268 | tty_mod TTy modifiers list\r |
| 269 | */\r |
| 270 | \r |
| 271 | #define TTI 0\r |
| 272 | #define TTO 1\r |
| 273 | #define TTP 2\r |
| 274 | \r |
| 275 | DIB tty_dib = { TTY, 0, 0, 0, 0, 0, &ttyio };\r |
| 276 | \r |
| 277 | UNIT tty_unit[] = {\r |
| 278 | { UDATA (&tti_svc, UNIT_IDLE | TT_MODE_UC, 0), POLL_WAIT },\r |
| 279 | { UDATA (&tto_svc, TT_MODE_UC, 0), TTY_OUT_WAIT },\r |
| 280 | { UDATA (&tto_svc, UNIT_SEQ | UNIT_ATTABLE | TT_MODE_8B, 0), SERIAL_OUT_WAIT }\r |
| 281 | };\r |
| 282 | \r |
| 283 | REG tty_reg[] = {\r |
| 284 | { ORDATA (BUF, tty_buf, 8) },\r |
| 285 | { ORDATA (MODE, tty_mode, 16) },\r |
| 286 | { ORDATA (SHIN, tty_shin, 8), REG_HRO },\r |
| 287 | { FLDATA (CMD, tty_dib.cmd, 0), REG_HRO },\r |
| 288 | { FLDATA (CTL, tty_dib.ctl, 0) },\r |
| 289 | { FLDATA (FLG, tty_dib.flg, 0) },\r |
| 290 | { FLDATA (FBF, tty_dib.fbf, 0) },\r |
| 291 | { FLDATA (SRQ, tty_dib.srq, 0) },\r |
| 292 | { FLDATA (KLFP, tty_lf, 0), REG_HRO },\r |
| 293 | { DRDATA (KPOS, tty_unit[TTI].pos, T_ADDR_W), PV_LEFT },\r |
| 294 | { DRDATA (KTIME, tty_unit[TTI].wait, 24), REG_NZ + PV_LEFT },\r |
| 295 | { DRDATA (TPOS, tty_unit[TTO].pos, T_ADDR_W), PV_LEFT },\r |
| 296 | { DRDATA (TTIME, tty_unit[TTO].wait, 24), REG_NZ + PV_LEFT },\r |
| 297 | { DRDATA (PPOS, tty_unit[TTP].pos, T_ADDR_W), PV_LEFT },\r |
| 298 | { FLDATA (STOP_IOE, ttp_stopioe, 0) },\r |
| 299 | { ORDATA (DEVNO, tty_dib.devno, 6), REG_HRO },\r |
| 300 | { NULL }\r |
| 301 | };\r |
| 302 | \r |
| 303 | MTAB tty_mod[] = {\r |
| 304 | { TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_opt },\r |
| 305 | { TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_opt },\r |
| 306 | { TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_opt },\r |
| 307 | { TT_MODE, TT_MODE_7P, "7p", "7P", &tty_set_opt },\r |
| 308 | { UNIT_AUTOLF, UNIT_AUTOLF, "autolf", "AUTOLF", &tty_set_alf },\r |
| 309 | { UNIT_AUTOLF, 0 , NULL, "NOAUTOLF", &tty_set_alf },\r |
| 310 | { MTAB_XTD | MTAB_VDV, 0, "DEVNO", "DEVNO",\r |
| 311 | &hp_setdev, &hp_showdev, &tty_dev },\r |
| 312 | { 0 }\r |
| 313 | };\r |
| 314 | \r |
| 315 | DEVICE tty_dev = {\r |
| 316 | "TTY", tty_unit, tty_reg, tty_mod,\r |
| 317 | 3, 10, 31, 1, 8, 8,\r |
| 318 | NULL, NULL, &tty_reset,\r |
| 319 | NULL, NULL, NULL,\r |
| 320 | &tty_dib, 0\r |
| 321 | };\r |
| 322 | \r |
| 323 | /* CLK data structures\r |
| 324 | \r |
| 325 | clk_dev CLK device descriptor\r |
| 326 | clk_unit CLK unit descriptor\r |
| 327 | clk_mod CLK modifiers\r |
| 328 | clk_reg CLK register list\r |
| 329 | */\r |
| 330 | \r |
| 331 | DIB clk_dib = { CLK, 0, 0, 0, 0, 0, &clkio };\r |
| 332 | \r |
| 333 | UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0) };\r |
| 334 | \r |
| 335 | REG clk_reg[] = {\r |
| 336 | { ORDATA (SEL, clk_select, 3) },\r |
| 337 | { DRDATA (CTR, clk_ctr, 14) },\r |
| 338 | { FLDATA (CMD, clk_dib.cmd, 0), REG_HRO },\r |
| 339 | { FLDATA (CTL, clk_dib.ctl, 0) },\r |
| 340 | { FLDATA (FLG, clk_dib.flg, 0) },\r |
| 341 | { FLDATA (FBF, clk_dib.fbf, 0) },\r |
| 342 | { FLDATA (SRQ, clk_dib.srq, 0) },\r |
| 343 | { FLDATA (ERR, clk_error, CLK_V_ERROR) },\r |
| 344 | { BRDATA (TIME, clk_time, 10, 24, 8) },\r |
| 345 | { DRDATA (IPTICK, clk_tick, 24), PV_RSPC | REG_RO },\r |
| 346 | { ORDATA (DEVNO, clk_dib.devno, 6), REG_HRO },\r |
| 347 | { NULL }\r |
| 348 | };\r |
| 349 | \r |
| 350 | MTAB clk_mod[] = {\r |
| 351 | { UNIT_DIAG, UNIT_DIAG, "diagnostic mode", "DIAG", NULL },\r |
| 352 | { UNIT_DIAG, 0, "calibrated", "CALIBRATED", NULL },\r |
| 353 | { MTAB_XTD | MTAB_VDV, 0, "DEVNO", "DEVNO",\r |
| 354 | &hp_setdev, &hp_showdev, &clk_dev },\r |
| 355 | { 0 }\r |
| 356 | };\r |
| 357 | \r |
| 358 | DEVICE clk_dev = {\r |
| 359 | "CLK", &clk_unit, clk_reg, clk_mod,\r |
| 360 | 1, 0, 0, 0, 0, 0,\r |
| 361 | NULL, NULL, &clk_reset,\r |
| 362 | NULL, NULL, NULL,\r |
| 363 | &clk_dib, DEV_DISABLE\r |
| 364 | };\r |
| 365 | \r |
| 366 | /* Paper tape reader IO instructions */\r |
| 367 | \r |
| 368 | int32 ptrio (int32 inst, int32 IR, int32 dat)\r |
| 369 | {\r |
| 370 | int32 dev;\r |
| 371 | \r |
| 372 | dev = IR & I_DEVMASK; /* get device no */\r |
| 373 | switch (inst) { /* case on opcode */\r |
| 374 | \r |
| 375 | case ioFLG: /* flag clear/set */\r |
| 376 | if ((IR & I_HC) == 0) { setFSR (dev); } /* STF */\r |
| 377 | break;\r |
| 378 | \r |
| 379 | case ioSFC: /* skip flag clear */\r |
| 380 | if (FLG (dev) == 0) PC = (PC + 1) & VAMASK;\r |
| 381 | break;\r |
| 382 | \r |
| 383 | case ioSFS: /* skip flag set */\r |
| 384 | if (FLG (dev) != 0) PC = (PC + 1) & VAMASK;\r |
| 385 | break;\r |
| 386 | \r |
| 387 | case ioMIX: /* merge */\r |
| 388 | dat = dat | ptr_unit.buf;\r |
| 389 | break;\r |
| 390 | \r |
| 391 | case ioLIX: /* load */\r |
| 392 | dat = ptr_unit.buf;\r |
| 393 | break;\r |
| 394 | \r |
| 395 | case ioCRS: /* control reset */\r |
| 396 | /* action same as CLC */\r |
| 397 | case ioCTL: /* control clear/set */\r |
| 398 | if (IR & I_CTL) { /* CLC */\r |
| 399 | clrCMD (dev); /* clear cmd, ctl */\r |
| 400 | clrCTL (dev);\r |
| 401 | }\r |
| 402 | else { /* STC */\r |
| 403 | setCMD (dev); /* set cmd, ctl */\r |
| 404 | setCTL (dev);\r |
| 405 | sim_activate (&ptr_unit, ptr_unit.wait);\r |
| 406 | }\r |
| 407 | break;\r |
| 408 | \r |
| 409 | default:\r |
| 410 | break;\r |
| 411 | }\r |
| 412 | \r |
| 413 | if (IR & I_HC) { clrFSR (dev); } /* H/C option */\r |
| 414 | return dat;\r |
| 415 | }\r |
| 416 | \r |
| 417 | /* Unit service */\r |
| 418 | \r |
| 419 | t_stat ptr_svc (UNIT *uptr)\r |
| 420 | {\r |
| 421 | int32 dev, temp;\r |
| 422 | \r |
| 423 | dev = ptr_dib.devno; /* get device no */\r |
| 424 | clrCMD (dev); /* clear cmd */\r |
| 425 | if ((ptr_unit.flags & UNIT_ATT) == 0) /* attached? */\r |
| 426 | return IORETURN (ptr_stopioe, SCPE_UNATT);\r |
| 427 | while ((temp = getc (ptr_unit.fileref)) == EOF) { /* read byte, error? */\r |
| 428 | if (feof (ptr_unit.fileref)) { /* end of file? */\r |
| 429 | if ((ptr_unit.flags & UNIT_DIAG) && (ptr_unit.pos > 0)) {\r |
| 430 | rewind (ptr_unit.fileref); /* rewind if loop mode */\r |
| 431 | ptr_unit.pos = 0;\r |
| 432 | }\r |
| 433 | else {\r |
| 434 | if (ptr_trlcnt >= ptr_trllim) { /* added all trailer? */\r |
| 435 | if (ptr_stopioe) { /* stop on error? */\r |
| 436 | printf ("PTR end of file\n");\r |
| 437 | return SCPE_IOERR;\r |
| 438 | }\r |
| 439 | else return SCPE_OK; /* no, just hang */\r |
| 440 | }\r |
| 441 | ptr_trlcnt++; /* count trailer */\r |
| 442 | temp = 0; /* read a zero */\r |
| 443 | break;\r |
| 444 | }\r |
| 445 | }\r |
| 446 | else { /* no, real error */\r |
| 447 | perror ("PTR I/O error");\r |
| 448 | clearerr (ptr_unit.fileref);\r |
| 449 | return SCPE_IOERR;\r |
| 450 | }\r |
| 451 | }\r |
| 452 | setFSR (dev); /* set flag */\r |
| 453 | ptr_unit.buf = temp & 0377; /* put byte in buf */\r |
| 454 | ptr_unit.pos = ftell (ptr_unit.fileref);\r |
| 455 | \r |
| 456 | if (temp) /* character non-null? */\r |
| 457 | ptr_trlcnt = 0; /* clear trailing null counter */\r |
| 458 | \r |
| 459 | return SCPE_OK;\r |
| 460 | }\r |
| 461 | \r |
| 462 | /* Attach routine - clear the trailer counter */\r |
| 463 | \r |
| 464 | t_stat ptr_attach (UNIT *uptr, char *cptr)\r |
| 465 | {\r |
| 466 | ptr_trlcnt = 0;\r |
| 467 | return attach_unit (uptr, cptr);\r |
| 468 | }\r |
| 469 | \r |
| 470 | /* Reset routine - called from SCP, flags in DIB's */\r |
| 471 | \r |
| 472 | t_stat ptr_reset (DEVICE *dptr)\r |
| 473 | {\r |
| 474 | ptr_dib.cmd = ptr_dib.ctl = 0; /* clear cmd, ctl */\r |
| 475 | ptr_dib.flg = ptr_dib.fbf = ptr_dib.srq = 1; /* set flg, fbf, srq */\r |
| 476 | ptr_unit.buf = 0;\r |
| 477 | sim_cancel (&ptr_unit); /* deactivate unit */\r |
| 478 | return SCPE_OK;\r |
| 479 | }\r |
| 480 | \r |
| 481 | /* Paper tape reader bootstrap routine (HP 12992K ROM) */\r |
| 482 | \r |
| 483 | const uint16 ptr_rom[IBL_LNT] = {\r |
| 484 | 0107700, /*ST CLC 0,C ; intr off */\r |
| 485 | 0002401, /* CLA,RSS ; skip in */\r |
| 486 | 0063756, /*CN LDA M11 ; feed frame */\r |
| 487 | 0006700, /* CLB,CCE ; set E to rd byte */\r |
| 488 | 0017742, /* JSB READ ; get #char */\r |
| 489 | 0007306, /* CMB,CCE,INB,SZB ; 2's comp */\r |
| 490 | 0027713, /* JMP *+5 ; non-zero byte */\r |
| 491 | 0002006, /* INA,SZA ; feed frame ctr */\r |
| 492 | 0027703, /* JMP *-3 */\r |
| 493 | 0102077, /* HLT 77B ; stop */\r |
| 494 | 0027700, /* JMP ST ; next */\r |
| 495 | 0077754, /* STA WC ; word in rec */\r |
| 496 | 0017742, /* JSB READ ; get feed frame */\r |
| 497 | 0017742, /* JSB READ ; get address */\r |
| 498 | 0074000, /* STB 0 ; init csum */\r |
| 499 | 0077755, /* STB AD ; save addr */\r |
| 500 | 0067755, /*CK LDB AD ; check addr */\r |
| 501 | 0047777, /* ADB MAXAD ; below loader */\r |
| 502 | 0002040, /* SEZ ; E =0 => OK */\r |
| 503 | 0027740, /* JMP H55 */\r |
| 504 | 0017742, /* JSB READ ; get word */\r |
| 505 | 0040001, /* ADA 1 ; cont checksum */\r |
| 506 | 0177755, /* STA AD,I ; store word */\r |
| 507 | 0037755, /* ISZ AD */\r |
| 508 | 0000040, /* CLE ; force wd read */\r |
| 509 | 0037754, /* ISZ WC ; block done? */\r |
| 510 | 0027720, /* JMP CK ; no */\r |
| 511 | 0017742, /* JSB READ ; get checksum */\r |
| 512 | 0054000, /* CPB 0 ; ok? */\r |
| 513 | 0027702, /* JMP CN ; next block */\r |
| 514 | 0102011, /* HLT 11 ; bad csum */\r |
| 515 | 0027700, /* JMP ST ; next */\r |
| 516 | 0102055, /*H55 HALT 55 ; bad address */\r |
| 517 | 0027700, /* JMP ST ; next */\r |
| 518 | 0000000, /*RD 0 */\r |
| 519 | 0006600, /* CLB,CME ; E reg byte ptr */\r |
| 520 | 0103710, /* STC RDR,C ; start reader */\r |
| 521 | 0102310, /* SFS RDR ; wait */\r |
| 522 | 0027745, /* JMP *-1 */\r |
| 523 | 0106410, /* MIB RDR ; get byte */\r |
| 524 | 0002041, /* SEZ,RSS ; E set? */\r |
| 525 | 0127742, /* JMP RD,I ; no, done */\r |
| 526 | 0005767, /* BLF,CLE,BLF ; shift byte */\r |
| 527 | 0027744, /* JMP RD+2 ; again */\r |
| 528 | 0000000, /*WC 000000 ; word count */\r |
| 529 | 0000000, /*AD 000000 ; address */\r |
| 530 | 0177765, /*M11 -11 ; feed count */\r |
| 531 | 0, 0, 0, 0, 0, 0, 0, 0, /* unused */\r |
| 532 | 0, 0, 0, 0, 0, 0, 0, /* unused */\r |
| 533 | 0000000 /*MAXAD -ST ; max addr */\r |
| 534 | };\r |
| 535 | \r |
| 536 | t_stat ptr_boot (int32 unitno, DEVICE *dptr)\r |
| 537 | {\r |
| 538 | int32 dev;\r |
| 539 | \r |
| 540 | dev = ptr_dib.devno; /* get device no */\r |
| 541 | if (ibl_copy (ptr_rom, dev)) return SCPE_IERR; /* copy boot to memory */\r |
| 542 | SR = (SR & IBL_OPT) | IBL_PTR | (dev << IBL_V_DEV); /* set SR */\r |
| 543 | return SCPE_OK;\r |
| 544 | }\r |
| 545 | \r |
| 546 | /* Paper tape punch IO instructions */\r |
| 547 | \r |
| 548 | int32 ptpio (int32 inst, int32 IR, int32 dat)\r |
| 549 | {\r |
| 550 | int32 dev;\r |
| 551 | \r |
| 552 | dev = IR & I_DEVMASK; /* get device no */\r |
| 553 | switch (inst) { /* case on opcode */\r |
| 554 | \r |
| 555 | case ioFLG: /* flag clear/set */\r |
| 556 | if ((IR & I_HC) == 0) { setFSR (dev); } /* STF */\r |
| 557 | break;\r |
| 558 | \r |
| 559 | case ioSFC: /* skip flag clear */\r |
| 560 | if (FLG (dev) == 0) PC = (PC + 1) & VAMASK;\r |
| 561 | break;\r |
| 562 | \r |
| 563 | case ioSFS: /* skip flag set */\r |
| 564 | if (FLG (dev) != 0) PC = (PC + 1) & VAMASK;\r |
| 565 | break;\r |
| 566 | \r |
| 567 | case ioLIX: /* load */\r |
| 568 | dat = 0;\r |
| 569 | case ioMIX: /* merge */\r |
| 570 | if ((ptp_unit.flags & UNIT_ATT) == 0)\r |
| 571 | dat = dat | PTP_LOW; /* out of tape? */\r |
| 572 | break;\r |
| 573 | \r |
| 574 | case ioOTX: /* output */\r |
| 575 | ptp_unit.buf = dat;\r |
| 576 | break;\r |
| 577 | \r |
| 578 | case ioCRS: /* control reset */\r |
| 579 | /* action same as CLC */\r |
| 580 | case ioCTL: /* control clear/set */\r |
| 581 | if (IR & I_CTL) { /* CLC */\r |
| 582 | clrCMD (dev); /* clear cmd, ctl */\r |
| 583 | clrCTL (dev);\r |
| 584 | }\r |
| 585 | else { /* STC */\r |
| 586 | setCMD (dev); /* set cmd, ctl */\r |
| 587 | setCTL (dev);\r |
| 588 | sim_activate (&ptp_unit, ptp_unit.wait);\r |
| 589 | }\r |
| 590 | break;\r |
| 591 | \r |
| 592 | default:\r |
| 593 | break;\r |
| 594 | }\r |
| 595 | \r |
| 596 | if (IR & I_HC) { clrFSR (dev); } /* H/C option */\r |
| 597 | return dat;\r |
| 598 | }\r |
| 599 | \r |
| 600 | /* Unit service */\r |
| 601 | \r |
| 602 | t_stat ptp_svc (UNIT *uptr)\r |
| 603 | {\r |
| 604 | int32 dev;\r |
| 605 | \r |
| 606 | dev = ptp_dib.devno; /* get device no */\r |
| 607 | clrCMD (dev); /* clear cmd */\r |
| 608 | setFSR (dev); /* set flag */\r |
| 609 | if ((ptp_unit.flags & UNIT_ATT) == 0) /* attached? */\r |
| 610 | return IORETURN (ptp_stopioe, SCPE_UNATT);\r |
| 611 | if (putc (ptp_unit.buf, ptp_unit.fileref) == EOF) { /* output byte */\r |
| 612 | perror ("PTP I/O error");\r |
| 613 | clearerr (ptp_unit.fileref);\r |
| 614 | return SCPE_IOERR;\r |
| 615 | }\r |
| 616 | ptp_unit.pos = ftell (ptp_unit.fileref); /* update position */\r |
| 617 | return SCPE_OK;\r |
| 618 | }\r |
| 619 | \r |
| 620 | /* Reset routine */\r |
| 621 | \r |
| 622 | t_stat ptp_reset (DEVICE *dptr)\r |
| 623 | {\r |
| 624 | ptp_dib.cmd = ptp_dib.ctl = 0; /* clear cmd, ctl */\r |
| 625 | ptp_dib.flg = ptp_dib.fbf = ptp_dib.srq = 1; /* set flg, fbf, srq */\r |
| 626 | ptp_unit.buf = 0;\r |
| 627 | sim_cancel (&ptp_unit); /* deactivate unit */\r |
| 628 | return SCPE_OK;\r |
| 629 | }\r |
| 630 | \r |
| 631 | /* Terminal IO instructions */\r |
| 632 | \r |
| 633 | int32 ttyio (int32 inst, int32 IR, int32 dat)\r |
| 634 | {\r |
| 635 | int32 dev;\r |
| 636 | \r |
| 637 | dev = IR & I_DEVMASK; /* get device no */\r |
| 638 | switch (inst) { /* case on opcode */\r |
| 639 | \r |
| 640 | case ioFLG: /* flag clear/set */\r |
| 641 | if ((IR & I_HC) == 0) { setFSR (dev); } /* STF */\r |
| 642 | break;\r |
| 643 | \r |
| 644 | case ioSFC: /* skip flag clear */\r |
| 645 | if (FLG (dev) == 0) PC = (PC + 1) & VAMASK;\r |
| 646 | break;\r |
| 647 | \r |
| 648 | case ioSFS: /* skip flag set */\r |
| 649 | if (FLG (dev) != 0) PC = (PC + 1) & VAMASK;\r |
| 650 | break;\r |
| 651 | \r |
| 652 | case ioLIX: /* load */\r |
| 653 | dat = 0;\r |
| 654 | case ioMIX: /* merge */\r |
| 655 | dat = dat | tty_buf;\r |
| 656 | if (!(tty_mode & TM_KBD) && sim_is_active (&tty_unit[TTO]))\r |
| 657 | dat = dat | TP_BUSY;\r |
| 658 | break;\r |
| 659 | \r |
| 660 | case ioOTX: /* output */\r |
| 661 | if (dat & TM_MODE) tty_mode = dat & (TM_KBD|TM_PRI|TM_PUN);\r |
| 662 | tty_buf = dat & 0377;\r |
| 663 | break;\r |
| 664 | \r |
| 665 | case ioCRS: /* control reset */\r |
| 666 | clrCTL (dev); /* clear control */\r |
| 667 | setFSR (dev); /* set flag */\r |
| 668 | tty_mode = TM_KBD; /* set tty, clear print/punch */\r |
| 669 | tty_buf = 0; /* clear buffer */\r |
| 670 | tty_shin = 0377; /* input inactive */\r |
| 671 | tty_lf = 0; /* no lf pending */\r |
| 672 | break;\r |
| 673 | \r |
| 674 | case ioCTL: /* control clear/set */\r |
| 675 | if (IR & I_CTL) { clrCTL (dev); } /* CLC */\r |
| 676 | else { /* STC */\r |
| 677 | setCTL (dev);\r |
| 678 | if (!(tty_mode & TM_KBD)) /* output? */\r |
| 679 | sim_activate (&tty_unit[TTO], tty_unit[TTO].wait);\r |
| 680 | }\r |
| 681 | break;\r |
| 682 | \r |
| 683 | default:\r |
| 684 | break;\r |
| 685 | }\r |
| 686 | \r |
| 687 | if (IR & I_HC) { clrFSR (dev); } /* H/C option */\r |
| 688 | return dat;\r |
| 689 | }\r |
| 690 | \r |
| 691 | /* TTY input service routine.\r |
| 692 | \r |
| 693 | The console input poll routine is scheduled with a ten millisecond period\r |
| 694 | using a calibrated timer, which is the source of event timing for all of the\r |
| 695 | keyboard polling routines. Synchronizing other keyboard polls with the\r |
| 696 | console poll ensures maximum idle time.\r |
| 697 | \r |
| 698 | Several HP operating systems require a CR and LF sequence for line\r |
| 699 | termination. This is awkward on a PC, as there is no LF key (CTRL+J is\r |
| 700 | needed instead). We provide an AUTOLF mode to add a LF automatically to each\r |
| 701 | CR input. When this mode is set, entering CR will set a flag, which will\r |
| 702 | cause a LF to be supplied automatically at the next input poll.\r |
| 703 | \r |
| 704 | The 12531C teleprinter interface and the later 12880A CRT interface provide a\r |
| 705 | clever mechanism to detect a keypress during output. This is used by DOS and\r |
| 706 | RTE to allow the user to interrupt lengthy output operations to enter system\r |
| 707 | commands.\r |
| 708 | \r |
| 709 | Referring to the 12531C schematic, the terminal input enters on pin X\r |
| 710 | ("DATA FROM EIA COMPATIBLE DEVICE"). The signal passes through four\r |
| 711 | transistor inversions (Q8, Q1, Q2, and Q3) to appear on pin 12 of NAND gate\r |
| 712 | U104C. If the flag flip-flop is not set, the terminal input passes to the\r |
| 713 | (inverted) output of U104C and thence to the D input of the first of the\r |
| 714 | flip-flops forming the data register.\r |
| 715 | \r |
| 716 | In the idle condition (no key pressed), the terminal input line is marking\r |
| 717 | (voltage negative), so in passing through a total of five inversions, a\r |
| 718 | logic one is presented at the serial input of the data register. During an\r |
| 719 | output operation, the register is parallel loaded and serially shifted,\r |
| 720 | sending the output data through the register to the device and -- this is\r |
| 721 | the crux -- filling the register with logic ones from U104C.\r |
| 722 | \r |
| 723 | At the end of the output operation, the card flag is set, an interrupt\r |
| 724 | occurs, and the RTE driver is entered. The driver then does an LIA SC to\r |
| 725 | read the contents of the data register. If no key has been pressed during\r |
| 726 | the output operation, the register will read as all ones (octal 377). If,\r |
| 727 | however, any key was struck, at least one zero bit will be present. If the\r |
| 728 | register value doesn't equal 377, the driver sets the system "operator\r |
| 729 | attention" flag, which will cause DOS or RTE to output an asterisk prompt and\r |
| 730 | initiate a terminal read when the current output line is completed.\r |
| 731 | */\r |
| 732 | \r |
| 733 | t_stat tti_svc (UNIT *uptr)\r |
| 734 | {\r |
| 735 | int32 c, dev;\r |
| 736 | \r |
| 737 | uptr->wait = sim_rtcn_calb (POLL_RATE, TMR_POLL); /* calibrate poll timer */\r |
| 738 | sim_activate (uptr, uptr->wait); /* continue poll */\r |
| 739 | \r |
| 740 | dev = tty_dib.devno; /* get device no */\r |
| 741 | tty_shin = 0377; /* assume inactive */\r |
| 742 | if (tty_lf) { /* auto lf pending? */\r |
| 743 | c = 012; /* force lf */\r |
| 744 | tty_lf = 0;\r |
| 745 | }\r |
| 746 | else {\r |
| 747 | if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c; /* no char or error? */\r |
| 748 | if (c & SCPE_BREAK) c = 0; /* break? */\r |
| 749 | else c = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags));\r |
| 750 | tty_lf = ((c & 0177) == 015) && (uptr->flags & UNIT_AUTOLF);\r |
| 751 | }\r |
| 752 | if (tty_mode & TM_KBD) { /* keyboard enabled? */\r |
| 753 | tty_buf = c; /* put char in buf */\r |
| 754 | uptr->pos = uptr->pos + 1;\r |
| 755 | setFSR (dev); /* set flag */\r |
| 756 | if (c) {\r |
| 757 | tto_out (c); /* echo? */\r |
| 758 | return ttp_out (c); /* punch? */\r |
| 759 | }\r |
| 760 | }\r |
| 761 | else tty_shin = c; /* no, char shifts in */\r |
| 762 | return SCPE_OK;\r |
| 763 | }\r |
| 764 | \r |
| 765 | /* TTY output service routine */\r |
| 766 | \r |
| 767 | t_stat tto_svc (UNIT *uptr)\r |
| 768 | {\r |
| 769 | int32 c, dev;\r |
| 770 | t_stat r;\r |
| 771 | \r |
| 772 | c = tty_buf; /* get char */\r |
| 773 | tty_buf = tty_shin; /* shift in */\r |
| 774 | tty_shin = 0377; /* line inactive */\r |
| 775 | if ((r = tto_out (c)) != SCPE_OK) { /* output; error? */\r |
| 776 | sim_activate (uptr, uptr->wait); /* retry */\r |
| 777 | return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */\r |
| 778 | }\r |
| 779 | dev = tty_dib.devno; /* get device no */\r |
| 780 | setFSR (dev); /* set done flag */\r |
| 781 | return ttp_out (c); /* punch if enabled */\r |
| 782 | }\r |
| 783 | \r |
| 784 | t_stat tto_out (int32 c)\r |
| 785 | {\r |
| 786 | t_stat r;\r |
| 787 | \r |
| 788 | if (tty_mode & TM_PRI) { /* printing? */\r |
| 789 | c = sim_tt_outcvt (c, TT_GET_MODE (tty_unit[TTO].flags));\r |
| 790 | if (c >= 0) { /* valid? */\r |
| 791 | if (r = sim_putchar_s (c)) return r; /* output char */\r |
| 792 | tty_unit[TTO].pos = tty_unit[TTO].pos + 1;\r |
| 793 | }\r |
| 794 | }\r |
| 795 | return SCPE_OK;\r |
| 796 | }\r |
| 797 | \r |
| 798 | t_stat ttp_out (int32 c)\r |
| 799 | {\r |
| 800 | if (tty_mode & TM_PUN) { /* punching? */\r |
| 801 | if ((tty_unit[TTP].flags & UNIT_ATT) == 0) /* attached? */\r |
| 802 | return IORETURN (ttp_stopioe, SCPE_UNATT);\r |
| 803 | if (putc (c, tty_unit[TTP].fileref) == EOF) { /* output char */\r |
| 804 | perror ("TTP I/O error");\r |
| 805 | clearerr (tty_unit[TTP].fileref);\r |
| 806 | return SCPE_IOERR;\r |
| 807 | }\r |
| 808 | tty_unit[TTP].pos = ftell (tty_unit[TTP].fileref);\r |
| 809 | }\r |
| 810 | return SCPE_OK;\r |
| 811 | }\r |
| 812 | \r |
| 813 | /* TTY reset routine */\r |
| 814 | \r |
| 815 | t_stat tty_reset (DEVICE *dptr)\r |
| 816 | {\r |
| 817 | tty_dib.cmd = tty_dib.ctl = 0; /* clear cmd, ctl */\r |
| 818 | tty_dib.flg = tty_dib.fbf = tty_dib.srq = 1; /* set flg, fbf, srq */\r |
| 819 | tty_mode = TM_KBD; /* enable input */\r |
| 820 | tty_buf = 0;\r |
| 821 | tty_shin = 0377; /* input inactive */\r |
| 822 | tty_lf = 0; /* no lf pending */\r |
| 823 | tty_unit[TTI].wait = POLL_WAIT; /* reset initial poll */\r |
| 824 | sim_rtcn_init (tty_unit[TTI].wait, TMR_POLL); /* init poll timer */\r |
| 825 | sim_activate (&tty_unit[TTI], tty_unit[TTI].wait); /* activate poll */\r |
| 826 | sim_cancel (&tty_unit[TTO]); /* cancel output */\r |
| 827 | return SCPE_OK;\r |
| 828 | }\r |
| 829 | \r |
| 830 | t_stat tty_set_opt (UNIT *uptr, int32 val, char *cptr, void *desc)\r |
| 831 | {\r |
| 832 | int32 u = uptr - tty_dev.units;\r |
| 833 | \r |
| 834 | if (u > TTO) return SCPE_NOFNC;\r |
| 835 | if ((u == TTI) && (val == TT_MODE_7P))\r |
| 836 | val = TT_MODE_7B;\r |
| 837 | tty_unit[u].flags = (tty_unit[u].flags & ~TT_MODE) | val;\r |
| 838 | return SCPE_OK;\r |
| 839 | }\r |
| 840 | \r |
| 841 | t_stat tty_set_alf (UNIT *uptr, int32 val, char *cptr, void *desc)\r |
| 842 | {\r |
| 843 | int32 u = uptr - tty_dev.units;\r |
| 844 | \r |
| 845 | if (u != TTI) return SCPE_NOFNC;\r |
| 846 | return SCPE_OK;\r |
| 847 | }\r |
| 848 | \r |
| 849 | /* Synchronize polling.\r |
| 850 | \r |
| 851 | Return an event time corresponding either with the amount of time remaining\r |
| 852 | in the current poll (mode = INITIAL) or the amount of time in a full poll\r |
| 853 | period (mode = SERVICE). If the former call is made when the device service\r |
| 854 | routine is started, then making the latter call during unit service will\r |
| 855 | ensure that the polls remain synchronized.\r |
| 856 | */\r |
| 857 | \r |
| 858 | int32 sync_poll (POLLMODE poll_mode)\r |
| 859 | {\r |
| 860 | int32 poll_time;\r |
| 861 | \r |
| 862 | if (poll_mode == INITIAL) {\r |
| 863 | poll_time = sim_is_active (&tty_unit[TTI]);\r |
| 864 | \r |
| 865 | if (poll_time)\r |
| 866 | return poll_time;\r |
| 867 | else\r |
| 868 | return POLL_WAIT;\r |
| 869 | }\r |
| 870 | else\r |
| 871 | return tty_unit[TTI].wait;\r |
| 872 | }\r |
| 873 | \r |
| 874 | \r |
| 875 | /* Clock I/O instructions.\r |
| 876 | \r |
| 877 | The time base generator (CLK) provides periodic interrupts from 100\r |
| 878 | microseconds to 1000 seconds. The CLK uses a calibrated timer to provide the\r |
| 879 | time base. For periods ranging from 1 to 1000 seconds, a 100 millisecond\r |
| 880 | timer is used, and 10 to 10000 ticks are counted before setting the device\r |
| 881 | flag to indicate that the period has expired.\r |
| 882 | \r |
| 883 | If the period is set to ten milliseconds, the console poll timer is used\r |
| 884 | instead of an independent timer. This is to maximize the idle period.\r |
| 885 | \r |
| 886 | In diagnostic mode, the clock period is set to the expected number of CPU\r |
| 887 | instructions, rather than wall-clock time, so that the diagnostic executes as\r |
| 888 | expected.\r |
| 889 | */\r |
| 890 | \r |
| 891 | int32 clkio (int32 inst, int32 IR, int32 dat)\r |
| 892 | {\r |
| 893 | int32 dev;\r |
| 894 | \r |
| 895 | dev = IR & I_DEVMASK; /* get device no */\r |
| 896 | switch (inst) { /* case on opcode */\r |
| 897 | \r |
| 898 | case ioFLG: /* flag clear/set */\r |
| 899 | if ((IR & I_HC) == 0) { setFSR (dev); } /* STF */\r |
| 900 | break;\r |
| 901 | \r |
| 902 | case ioSFC: /* skip flag clear */\r |
| 903 | if (FLG (dev) == 0) PC = (PC + 1) & VAMASK;\r |
| 904 | break;\r |
| 905 | \r |
| 906 | case ioSFS: /* skip flag set */\r |
| 907 | if (FLG (dev) != 0) PC = (PC + 1) & VAMASK;\r |
| 908 | break;\r |
| 909 | \r |
| 910 | case ioMIX: /* merge */\r |
| 911 | dat = dat | clk_error;\r |
| 912 | break;\r |
| 913 | \r |
| 914 | case ioLIX: /* load */\r |
| 915 | dat = clk_error;\r |
| 916 | break;\r |
| 917 | \r |
| 918 | case ioOTX: /* output */\r |
| 919 | clk_select = dat & 07; /* save select */\r |
| 920 | sim_cancel (&clk_unit); /* stop the clock */\r |
| 921 | clrCTL (dev); /* clear control */\r |
| 922 | break;\r |
| 923 | \r |
| 924 | case ioCRS: /* control reset */\r |
| 925 | /* action same as CLC */\r |
| 926 | case ioCTL: /* control clear/set */\r |
| 927 | if (IR & I_CTL) { /* CLC */\r |
| 928 | clrCTL (dev); /* turn off clock */\r |
| 929 | sim_cancel (&clk_unit); /* deactivate unit */\r |
| 930 | }\r |
| 931 | else { /* STC */\r |
| 932 | setCTL (dev); /* set CTL */\r |
| 933 | \r |
| 934 | if (clk_unit.flags & UNIT_DIAG) /* diag mode? */\r |
| 935 | clk_unit.flags = clk_unit.flags & ~UNIT_IDLE; /* not calibrated */\r |
| 936 | else\r |
| 937 | clk_unit.flags = clk_unit.flags | UNIT_IDLE; /* is calibrated */\r |
| 938 | \r |
| 939 | if (!sim_is_active (&clk_unit)) { /* clock running? */\r |
| 940 | clk_tick = clk_delay (0); /* get tick count */\r |
| 941 | \r |
| 942 | if ((clk_unit.flags & UNIT_DIAG) == 0) /* calibrated? */\r |
| 943 | if (clk_select == 2) /* 10 msec. interval? */\r |
| 944 | clk_tick = sync_poll (INITIAL); /* sync poll */\r |
| 945 | else\r |
| 946 | sim_rtcn_init (clk_tick, TMR_CLK); /* initialize timer */\r |
| 947 | \r |
| 948 | sim_activate (&clk_unit, clk_tick); /* start clock */\r |
| 949 | clk_ctr = clk_delay (1); /* set repeat ctr */\r |
| 950 | }\r |
| 951 | clk_error = 0; /* clear error */\r |
| 952 | }\r |
| 953 | break;\r |
| 954 | \r |
| 955 | default:\r |
| 956 | break;\r |
| 957 | }\r |
| 958 | \r |
| 959 | if (IR & I_HC) { clrFSR (dev); } /* H/C option */\r |
| 960 | return dat;\r |
| 961 | }\r |
| 962 | \r |
| 963 | /* CLK unit service.\r |
| 964 | \r |
| 965 | As with the I/O handler, if the time base period is set to ten milliseconds,\r |
| 966 | the console poll timer is used instead of an independent timer.\r |
| 967 | */\r |
| 968 | \r |
| 969 | t_stat clk_svc (UNIT *uptr)\r |
| 970 | {\r |
| 971 | int32 dev;\r |
| 972 | \r |
| 973 | dev = clk_dib.devno; /* get device no */\r |
| 974 | if (!CTL (dev)) return SCPE_OK; /* CTL off? done */\r |
| 975 | \r |
| 976 | if (clk_unit.flags & UNIT_DIAG) /* diag mode? */\r |
| 977 | clk_tick = clk_delay (0); /* get fixed delay */\r |
| 978 | else if (clk_select == 2) /* 10 msec period? */\r |
| 979 | clk_tick = sync_poll (SERVICE); /* sync poll */\r |
| 980 | else\r |
| 981 | clk_tick = sim_rtcn_calb (clk_tps[clk_select], TMR_CLK); /* calibrate delay */\r |
| 982 | \r |
| 983 | sim_activate (uptr, clk_tick); /* reactivate */\r |
| 984 | clk_ctr = clk_ctr - 1; /* decrement counter */\r |
| 985 | if (clk_ctr <= 0) { /* end of interval? */\r |
| 986 | if (FLG (dev)) clk_error = CLK_ERROR; /* overrun? error */\r |
| 987 | else { setFSR (dev); } /* else set flag */\r |
| 988 | clk_ctr = clk_delay (1); /* reset counter */\r |
| 989 | }\r |
| 990 | return SCPE_OK;\r |
| 991 | }\r |
| 992 | \r |
| 993 | /* Reset routine */\r |
| 994 | \r |
| 995 | t_stat clk_reset (DEVICE *dptr)\r |
| 996 | {\r |
| 997 | clk_dib.cmd = clk_dib.ctl = 0; /* clear cmd, ctl */\r |
| 998 | clk_dib.flg = clk_dib.fbf = clk_dib.srq = 1; /* set flg, fbf, srq */\r |
| 999 | clk_error = 0; /* clear error */\r |
| 1000 | clk_select = 0; /* clear select */\r |
| 1001 | clk_ctr = 0; /* clear counter */\r |
| 1002 | sim_cancel (&clk_unit); /* deactivate unit */\r |
| 1003 | return SCPE_OK;\r |
| 1004 | }\r |
| 1005 | \r |
| 1006 | /* Clock delay routine */\r |
| 1007 | \r |
| 1008 | int32 clk_delay (int32 flg)\r |
| 1009 | {\r |
| 1010 | int32 sel = clk_select;\r |
| 1011 | \r |
| 1012 | if ((clk_unit.flags & UNIT_DIAG) && (sel >= 4)) sel = sel - 3;\r |
| 1013 | if (flg) return clk_rpt[sel];\r |
| 1014 | else return clk_time[sel];\r |
| 1015 | }\r |