| 1 | /* i7094_clk.c: IBM 7094 clock\r |
| 2 | \r |
| 3 | Copyright (c) 2003-2006, Robert M. Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | clk RPQ F89349 interval timer\r |
| 27 | Chronolog calendar clock\r |
| 28 | */\r |
| 29 | \r |
| 30 | #include "i7094_defs.h"\r |
| 31 | #include <time.h>\r |
| 32 | \r |
| 33 | uint32 chtr_clk = 0;\r |
| 34 | extern t_uint64 *M;\r |
| 35 | \r |
| 36 | t_stat clk_svc (UNIT *uptr);\r |
| 37 | t_stat clk_reset (DEVICE *dptr);\r |
| 38 | uint8 bcd_2d (uint32 n, uint8 *b2);\r |
| 39 | \r |
| 40 | /* CLK data structures\r |
| 41 | \r |
| 42 | clk_dev CLK device descriptor\r |
| 43 | clk_unit CLK unit\r |
| 44 | clk_reg CLK register list\r |
| 45 | */\r |
| 46 | \r |
| 47 | UNIT clk_unit = { UDATA (&clk_svc, 0, 0), 16000 };\r |
| 48 | \r |
| 49 | REG clk_reg[] = {\r |
| 50 | { FLDATA (TRAP, chtr_clk, 0) },\r |
| 51 | { DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },\r |
| 52 | { NULL }\r |
| 53 | };\r |
| 54 | \r |
| 55 | DEVICE clk_dev = {\r |
| 56 | "CLK", &clk_unit, clk_reg, NULL,\r |
| 57 | 1, 0, 0, 0, 0, 0,\r |
| 58 | NULL, NULL, &clk_reset,\r |
| 59 | NULL, NULL, NULL,\r |
| 60 | NULL, DEV_DISABLE+DEV_DIS\r |
| 61 | };\r |
| 62 | \r |
| 63 | /* Clock unit service */\r |
| 64 | \r |
| 65 | t_stat clk_svc (UNIT *uptr)\r |
| 66 | {\r |
| 67 | t_uint64 ctr;\r |
| 68 | \r |
| 69 | if ((clk_dev.flags & DEV_DIS) == 0) { /* clock enabled? */\r |
| 70 | ctr = ReadP (CLK_CTR);\r |
| 71 | ctr = (ctr + 1) & DMASK; /* increment */\r |
| 72 | WriteP (CLK_CTR, ctr);\r |
| 73 | if ((ctr & MMASK) == 0) chtr_clk = 1; /* overflow? req trap */\r |
| 74 | sim_activate (uptr, sim_rtcn_calb (CLK_TPS, TMR_CLK)); /* reactivate unit */\r |
| 75 | }\r |
| 76 | return SCPE_OK;\r |
| 77 | }\r |
| 78 | \r |
| 79 | /* Chronolog clock */\r |
| 80 | \r |
| 81 | uint32 chrono_rd (uint8 *buf, uint32 bufsiz)\r |
| 82 | {\r |
| 83 | time_t curtim;\r |
| 84 | t_uint64 ctr;\r |
| 85 | struct tm *tptr;\r |
| 86 | \r |
| 87 | if (bufsiz < 12) return 0;\r |
| 88 | curtim = time (NULL); /* get time */\r |
| 89 | tptr = localtime (&curtim); /* decompose */\r |
| 90 | if (tptr == NULL) return 0; /* error? */\r |
| 91 | \r |
| 92 | buf[0] = bcd_2d (tptr->tm_mon + 1, buf + 1);\r |
| 93 | buf[2] = bcd_2d (tptr->tm_mday, buf + 3);\r |
| 94 | buf[4] = bcd_2d (tptr->tm_hour, buf + 5);\r |
| 95 | buf[6] = bcd_2d (tptr->tm_min, buf + 7);\r |
| 96 | buf[8] = bcd_2d (tptr->tm_sec, buf + 9);\r |
| 97 | ctr = ReadP (CLK_CTR);\r |
| 98 | buf[10] = bcd_2d ((uint32) (ctr % 60), buf + 11);\r |
| 99 | return 12;\r |
| 100 | }\r |
| 101 | \r |
| 102 | /* Convert number (0-99) to BCD */\r |
| 103 | \r |
| 104 | uint8 bcd_2d (uint32 n, uint8 *b2)\r |
| 105 | {\r |
| 106 | uint8 d1, d2;\r |
| 107 | \r |
| 108 | d1 = n / 10;\r |
| 109 | d2 = n % 10;\r |
| 110 | if (d1 == 0) d1 = BCD_ZERO;\r |
| 111 | if (d2 == 0) d2 = BCD_ZERO;\r |
| 112 | if (b2 != NULL) *b2 = d2;\r |
| 113 | return d1;\r |
| 114 | }\r |
| 115 | \r |
| 116 | /* Reset routine */\r |
| 117 | \r |
| 118 | t_stat clk_reset (DEVICE *dptr)\r |
| 119 | {\r |
| 120 | chtr_clk = 0;\r |
| 121 | if (clk_dev.flags & DEV_DIS) sim_cancel (&clk_unit);\r |
| 122 | else sim_activate (&clk_unit, sim_rtcn_init (clk_unit.wait, TMR_CLK));\r |
| 123 | return SCPE_OK;\r |
| 124 | }\r |