| 1 | /* i7094_defs.h: IBM 7094 simulator definitions\r |
| 2 | \r |
| 3 | Copyright (c) 2003-2006, Robert M Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | This simulator incorporates prior work by Paul Pierce, Dave Pitts, and Rob\r |
| 27 | Storey. Tom Van Vleck, Stan Dunten, Jerry Saltzer, and other CTSS veterans\r |
| 28 | helped to reconstruct the CTSS hardware RPQ's. Dave Pitts gets special\r |
| 29 | thanks for patiently coaching me through IBSYS debug. */\r |
| 30 | \r |
| 31 | #ifndef _I7094_DEFS_H_\r |
| 32 | #define _I7094_DEFS_H_ 0\r |
| 33 | \r |
| 34 | #include "sim_defs.h" /* simulator defns */\r |
| 35 | \r |
| 36 | /* Simulator stop codes */\r |
| 37 | \r |
| 38 | #define STOP_HALT 1 /* halted */\r |
| 39 | #define STOP_IBKPT 2 /* breakpoint */\r |
| 40 | #define STOP_ILLEG 3 /* illegal instr */\r |
| 41 | #define STOP_DIVCHK 4 /* divide check */\r |
| 42 | #define STOP_XEC 5 /* XCT loop */\r |
| 43 | #define STOP_ASTOP 6 /* address stop */\r |
| 44 | #define STOP_NXCHN 7 /* nx channel */\r |
| 45 | #define STOP_7909 8 /* ill inst to 7909 */\r |
| 46 | #define STOP_NT7909 9 /* ill inst to !7909 */\r |
| 47 | #define STOP_NXDEV 10 /* nx device */\r |
| 48 | #define STOP_ILLCHI 11 /* illegal channel op */\r |
| 49 | #define STOP_WRP 12 /* write protect */\r |
| 50 | #define STOP_ILLIOP 13 /* illegal I/O op */\r |
| 51 | #define STOP_INVFMT 14 /* invalid disk format */\r |
| 52 | #define STOP_NOIFREE 15 /* 7750: no buf for inp */\r |
| 53 | #define STOP_NOOFREE 16 /* 7750: no buf for out */\r |
| 54 | #define STOP_INVLIN 17 /* 7750: invalid line# */\r |
| 55 | #define STOP_INVMSG 18 /* 7750: invalid message */\r |
| 56 | #define STOP_CHBKPT 19 /* channel breakpoint */\r |
| 57 | \r |
| 58 | /* Simulator error codes */\r |
| 59 | \r |
| 60 | #define ERR_STALL 40 /* stall */\r |
| 61 | #define ERR_ENDRC 41 /* end rec */\r |
| 62 | #define ERR_NRCF 42 /* no record found */\r |
| 63 | \r |
| 64 | /* Instruction history - flags in left half of pc entry */\r |
| 65 | \r |
| 66 | #define HIST_PC 0x04000000 /* CPU */\r |
| 67 | #define HIST_V_CH 28 /* chan + 1 */\r |
| 68 | #define HIST_M_CH 0xF\r |
| 69 | #define HIST_CH(x) (((x) >> HIST_V_CH) & HIST_M_CH)\r |
| 70 | \r |
| 71 | typedef struct {\r |
| 72 | uint32 pc;\r |
| 73 | uint32 ea;\r |
| 74 | uint32 rpt;\r |
| 75 | t_uint64 ir;\r |
| 76 | t_uint64 ac;\r |
| 77 | t_uint64 mq;\r |
| 78 | t_uint64 si;\r |
| 79 | t_uint64 opnd;\r |
| 80 | } InstHistory;\r |
| 81 | \r |
| 82 | /* Architectural constants */\r |
| 83 | \r |
| 84 | #define A704_SIZE 14 /* addr width, 704 mode */\r |
| 85 | #define ASIZE 15 /* inst addr width */\r |
| 86 | #define PASIZE 16 /* phys addr width */\r |
| 87 | #define STDMEMSIZE (1u << ASIZE) /* standard memory */\r |
| 88 | #define MAXMEMSIZE (1u << PASIZE) /* maximum memory */\r |
| 89 | #define A704_MASK ((1u << A704_SIZE) - 1)\r |
| 90 | #define PAMASK ((1u << PASIZE) - 1)\r |
| 91 | #define MEMSIZE (cpu_unit.capac)\r |
| 92 | #define BCORE_V (ASIZE) /* (CTSS) A/B core sel */\r |
| 93 | #define BCORE_BASE (1u << BCORE_V) /* (CTSS) B core base */\r |
| 94 | \r |
| 95 | /* Traps */\r |
| 96 | \r |
| 97 | #define TRAP_STD_SAV 000000 /* trap save location */\r |
| 98 | #define TRAP_TRA_PC 000001 /* trap PC: transfer */\r |
| 99 | #define TRAP_STR_PC 000002 /* trap PC: STR */\r |
| 100 | #define TRAP_FP_PC 000010 /* trap PC: flt point */\r |
| 101 | #define TRAP_PROT_SAV 000032 /* protection trap save */\r |
| 102 | #define TRAP_PROT_PC 000033 /* protection trap PC */\r |
| 103 | #define TRAP_704_SAV 040000 /* 704 compat trap */\r |
| 104 | #define TRAP_SEL_PC 040001 /* 704 trap PC: select */\r |
| 105 | #define TRAP_CPY_PC 040002 /* 704 trap PC: copy */\r |
| 106 | \r |
| 107 | #define TRAP_F_MQ 000001 /* MQ error */\r |
| 108 | #define TRAP_F_AC 000002 /* AC error */\r |
| 109 | #define TRAP_F_OVF 000004 /* overflow */\r |
| 110 | #define TRAP_F_SGL 000010 /* single precision */\r |
| 111 | #define TRAP_F_DVC 000020 /* fake: divide check */\r |
| 112 | #define TRAP_F_ODD 000040 /* odd address */\r |
| 113 | #define TRAP_F_BDATA 020000 /* (CTSS) data B core */\r |
| 114 | #define TRAP_F_BINST 040000 /* (CTSS) inst B core */\r |
| 115 | \r |
| 116 | /* Integer */\r |
| 117 | \r |
| 118 | #define DMASK 0777777777777 /* data mask */\r |
| 119 | #define SIGN 0400000000000 /* sign */\r |
| 120 | #define MMASK 0377777777777 /* magnitude mask */\r |
| 121 | #define LMASK 0777777000000 /* left mask */\r |
| 122 | #define RMASK 0000000777777 /* right mask */\r |
| 123 | #define PMASK 0700000000000 /* prefix */\r |
| 124 | #define XMASK 0077777000000 /* decrement */\r |
| 125 | #define TMASK 0000000700000 /* tag */\r |
| 126 | #define AMASK 0000000077777 /* address */\r |
| 127 | #define SCMASK 0000000000377 /* shift count mask */\r |
| 128 | #define B1 0200000000000 /* bit 1 */\r |
| 129 | #define B9 0000400000000 /* bit 9 */\r |
| 130 | \r |
| 131 | /* Accumulator is actually 38b wide */\r |
| 132 | \r |
| 133 | #define AC_S 02000000000000 /* sign */\r |
| 134 | #define AC_Q 01000000000000 /* Q */\r |
| 135 | #define AC_P 00400000000000 /* P */\r |
| 136 | #define AC_MMASK 01777777777777 /* Q+P+magnitude */\r |
| 137 | \r |
| 138 | /* Floating point */\r |
| 139 | \r |
| 140 | #define FP_N_FR 27 /* fraction bits */\r |
| 141 | #define FP_FMASK ((1u << FP_N_FR) - 1)\r |
| 142 | #define FP_N_DFR 54 /* double fraction bits */\r |
| 143 | #define FP_DFMASK ((((t_uint64) 1) << FP_N_DFR) - 1)\r |
| 144 | #define FP_FNORM (((t_uint64) 1u) << (FP_N_DFR - 1)) /* normalized bit */\r |
| 145 | #define FP_FCRY (((t_uint64) 1u) << FP_N_DFR) /* fraction carry */\r |
| 146 | #define FP_BIAS 0200 /* exponent bias */\r |
| 147 | #define FP_V_CH (FP_N_FR) /* exponent */\r |
| 148 | #define FP_M_CH 0377 /* SR char mask */\r |
| 149 | #define FP_M_ACCH 01777 /* AC char mask incl Q,P */\r |
| 150 | \r |
| 151 | /* Instruction format */\r |
| 152 | \r |
| 153 | #define INST_T_DEC 0300000000000 /* if nz, takes decr */\r |
| 154 | #define INST_T_CXR1 0000000100000 /* if nz, update XR1 */\r |
| 155 | #define INST_V_OPD 33 /* decrement opcode */\r |
| 156 | #define INST_M_OPD 07\r |
| 157 | #define INST_V_DEC 18 /* decrement */\r |
| 158 | #define INST_M_DEC 077777\r |
| 159 | #define INST_V_OPC 24 /* normal opcode */\r |
| 160 | #define INST_M_OPC 0777\r |
| 161 | #define INST_V_IND 22 /* indirect */\r |
| 162 | #define INST_IND (3 << INST_V_IND)\r |
| 163 | #define INST_V_CCNT 18 /* convert count */\r |
| 164 | #define INST_M_CCNT 0377\r |
| 165 | #define INST_V_VCNT 18 /* vlm/vdh count */\r |
| 166 | #define INST_M_VCNT 077\r |
| 167 | #define INST_V_TAG 15 /* index */\r |
| 168 | #define INST_M_TAG 07\r |
| 169 | #define INST_V_ADDR 0\r |
| 170 | #define INST_M_ADDR 077777\r |
| 171 | \r |
| 172 | #define GET_OPD(x) ((uint32) (((x) >> INST_V_OPD) & INST_M_OPD))\r |
| 173 | #define GET_DEC(x) ((uint32) (((x) >> INST_V_DEC) & INST_M_DEC))\r |
| 174 | #define GET_OPC(x) (((uint32) (((x) >> INST_V_OPC) & INST_M_OPC)) | \\r |
| 175 | (((x) & SIGN)? 01000: 0))\r |
| 176 | #define TST_IND(x) (((x) & INST_IND) == INST_IND)\r |
| 177 | #define GET_CCNT(x) ((uint32) (((x) >> INST_V_CCNT) & INST_M_CCNT))\r |
| 178 | #define GET_VCNT(x) ((uint32) (((x) >> INST_V_VCNT) & INST_M_VCNT))\r |
| 179 | #define GET_TAG(x) ((uint32) (((x) >> INST_V_TAG) & INST_M_TAG))\r |
| 180 | \r |
| 181 | /* Instruction decode flags */\r |
| 182 | \r |
| 183 | #define I_4X 0x01 /* 7040, 7044 */\r |
| 184 | #define I_9X 0x02 /* 7090, 7094, CTSS */\r |
| 185 | #define I_94 0x04 /* 7094, CTSS */\r |
| 186 | #define I_CT 0x08 /* CTSS */\r |
| 187 | #define I_MODEL 0x0F /* option mask */ \r |
| 188 | #define I_X 0x10 /* indexed */\r |
| 189 | #define I_N 0x20 /* indirect */\r |
| 190 | #define I_R 0x40 /* read */\r |
| 191 | #define I_D 0x80 /* double read */\r |
| 192 | \r |
| 193 | #define I_XN (I_X|I_N)\r |
| 194 | #define I_XNR (I_X|I_N|I_R)\r |
| 195 | #define I_XND (I_X|I_N|I_D)\r |
| 196 | \r |
| 197 | /* Memory protection (CTSS) */\r |
| 198 | \r |
| 199 | #define VA_V_OFF 0 /* offset in block */\r |
| 200 | #define VA_N_OFF 8 /* width of offset */\r |
| 201 | #define VA_M_OFF ((1u << VA_N_OFF) - 1)\r |
| 202 | #define VA_OFF (VA_M_OFF << VA_V_OFF)\r |
| 203 | #define VA_V_BLK (VA_N_OFF) /* block */\r |
| 204 | #define VA_N_BLK (ASIZE - VA_N_OFF) /* width of block */\r |
| 205 | #define VA_M_BLK ((1u << VA_N_BLK) - 1)\r |
| 206 | #define VA_BLK (VA_M_BLK << VA_V_BLK)\r |
| 207 | \r |
| 208 | /* Unsigned operations */\r |
| 209 | \r |
| 210 | #define NEG(x) (~(x) + 1)\r |
| 211 | #define BIT_TST(w,b) (((w) >> (b)) & 1)\r |
| 212 | \r |
| 213 | /* Device information block */\r |
| 214 | \r |
| 215 | typedef struct {\r |
| 216 | t_stat (*chsel)(uint32 ch, uint32 sel, uint32 u);\r |
| 217 | t_stat (*write)(uint32 ch, t_uint64 val, uint32 flags);\r |
| 218 | } DIB;\r |
| 219 | \r |
| 220 | /* BCD digits */\r |
| 221 | \r |
| 222 | #define BCD_MASK 017\r |
| 223 | #define BCD_ZERO 012\r |
| 224 | #define BCD_ONE 001\r |
| 225 | #define BCD_TWO 002\r |
| 226 | #define BCD_AT 014\r |
| 227 | \r |
| 228 | /* Channels */\r |
| 229 | \r |
| 230 | #define NUM_CHAN 8 /* # channels */\r |
| 231 | #define CH_A 0 /* channel A */\r |
| 232 | #define CH_B 1\r |
| 233 | #define CH_C 2\r |
| 234 | #define CH_D 3\r |
| 235 | #define CH_E 4\r |
| 236 | #define CH_F 5\r |
| 237 | #define CH_G 6\r |
| 238 | #define CH_H 7\r |
| 239 | \r |
| 240 | #define REQ_CH(x) (1u << (x))\r |
| 241 | \r |
| 242 | /* All channel commands */\r |
| 243 | \r |
| 244 | #define CHI_IND 0000000400000 /* ch inst indirect */\r |
| 245 | \r |
| 246 | /* Channel selects - all channels */\r |
| 247 | \r |
| 248 | #define CHSL_RDS 0001 /* data selects */\r |
| 249 | #define CHSL_WRS 0002\r |
| 250 | #define CHSL_SNS 0003\r |
| 251 | #define CHSL_CTL 0004\r |
| 252 | #define CHSL_FMT 0005\r |
| 253 | #define CHSL_WEF 0010 /* non-data selects */\r |
| 254 | #define CHSL_WBT 0011 /* 704X only */\r |
| 255 | #define CHSL_BSR 0012\r |
| 256 | #define CHSL_BSF 0013\r |
| 257 | #define CHSL_REW 0014\r |
| 258 | #define CHSL_RUN 0015\r |
| 259 | #define CHSL_SDN 0016\r |
| 260 | #define CHSL_2ND 0020 /* second state */\r |
| 261 | #define CHSL_3RD 0040 /* etc */\r |
| 262 | #define CHSL_4TH 0060\r |
| 263 | #define CHSL_5TH 0100\r |
| 264 | #define CHSL_NDS 0010 /* non-data sel flag */\r |
| 265 | #define CHSL_NUM 16\r |
| 266 | \r |
| 267 | /* Channel commands - 7607/7289 - S12'19 */\r |
| 268 | \r |
| 269 | #define CH6I_NST 0000000200000 /* ch inst no store */\r |
| 270 | \r |
| 271 | #define CH6_IOCD 000\r |
| 272 | #define CH6_TCH 002\r |
| 273 | #define CH6_IORP 004\r |
| 274 | #define CH6_IORT 006\r |
| 275 | #define CH6_IOCP 010\r |
| 276 | #define CH6_IOCT 012\r |
| 277 | #define CH6_IOSP 014\r |
| 278 | #define CH6_IOST 016\r |
| 279 | #define CH6_OPMASK 016 /* without nostore */\r |
| 280 | #define TCH_LIMIT 5 /* TCH autoresolve limit */\r |
| 281 | \r |
| 282 | /* Channel data flags - 7607 */\r |
| 283 | \r |
| 284 | #define CH6DF_EOR 1 /* end of record */\r |
| 285 | #define CH6DF_VLD 2 /* input valid */\r |
| 286 | \r |
| 287 | /* Channel commands - 7909 - S123'19 */\r |
| 288 | \r |
| 289 | #define CH9_WTR 000\r |
| 290 | #define CH9_XMT 001\r |
| 291 | #define CH9_TCH 004\r |
| 292 | #define CH9_LIPT 005\r |
| 293 | #define CH9_CTL 010\r |
| 294 | #define CH9_CTLR 011\r |
| 295 | #define CH9_CTLW 012\r |
| 296 | #define CH9_SNS 013\r |
| 297 | #define CH9_LAR 014\r |
| 298 | #define CH9_SAR 015\r |
| 299 | #define CH9_TWT 016\r |
| 300 | #define CH9_CPYP 020\r |
| 301 | #define CH9_CPYD 024\r |
| 302 | #define CH9_TCM 025\r |
| 303 | #define CH9_LIP 031\r |
| 304 | #define CH9_TDC 032\r |
| 305 | #define CH9_LCC 033\r |
| 306 | #define CH9_SMS 034\r |
| 307 | #define CH9_ICC 035\r |
| 308 | #define CH9_ICCA 037 /* ignores bit <3> */\r |
| 309 | #define CH9_OPMASK 037\r |
| 310 | \r |
| 311 | /* Channel data flags - 7909 */\r |
| 312 | \r |
| 313 | #define CH9DF_STOP 1 /* stop */\r |
| 314 | #define CH9DF_VLD 2 /* input valid */\r |
| 315 | \r |
| 316 | /* Extended parts of the command come from the decrement, stored in ch_wc */\r |
| 317 | \r |
| 318 | #define CH9D_V_MASK 0 /* condition mask */\r |
| 319 | #define CH9D_M_MASK 077\r |
| 320 | #define CH9D_V_COND 12 /* condition select */\r |
| 321 | #define CH9D_M_COND 07\r |
| 322 | #define CH9D_MASK(x) (((x) >> CH9D_V_MASK) & CH9D_M_MASK)\r |
| 323 | #define CH9D_COND(x) (((x) >> CH9D_V_COND) & CH9D_M_COND)\r |
| 324 | \r |
| 325 | #define CH9D_NST 020000 /* no store */\r |
| 326 | #define CH9D_B11 000100\r |
| 327 | \r |
| 328 | /* Or from the effective address, stored in ch_ca */\r |
| 329 | \r |
| 330 | #define CH9A_V_LCC 0 /* counter */\r |
| 331 | #define CH9A_M_LCC 077\r |
| 332 | #define CH9A_V_SMS 0 /* system mask */\r |
| 333 | #define CH9A_M_SMS 0177\r |
| 334 | #define CH9A_LCC(x) (((x) >> CH9A_V_LCC) & CH9A_M_LCC)\r |
| 335 | #define CH9A_SMS(x) (((x) >> CH9A_V_SMS) & CH9A_M_SMS)\r |
| 336 | \r |
| 337 | /* Channel states - common */\r |
| 338 | \r |
| 339 | #define CHXS_IDLE 0 /* idle */\r |
| 340 | #define CHXS_DSX 1 /* executing */\r |
| 341 | \r |
| 342 | /* Channel states - 7607/7289 */\r |
| 343 | \r |
| 344 | #define CH6S_PNDS 2 /* polling NDS */\r |
| 345 | #define CH6S_PDS 3 /* polling DS */\r |
| 346 | #define CH6S_NDS 4 /* nds, executing */\r |
| 347 | #define CH6S_DSW 5 /* ds, chan wait */\r |
| 348 | \r |
| 349 | /* Channel traps - 7909 has only CMD (== TWT) */\r |
| 350 | \r |
| 351 | #define CHTR_V_CME 0 /* cmd/eof enable */\r |
| 352 | #define CHTR_V_CLK 17 /* clock */\r |
| 353 | #define CHTR_V_TRC 18 /* tape check */\r |
| 354 | #define CHTR_V_TWT (CHTR_V_CME)\r |
| 355 | #define CHTR_CLK_SAV 006 /* clock */\r |
| 356 | #define CHTR_CHA_SAV 012 /* start of chan block */\r |
| 357 | #define CHTR_F_CMD 1 /* CMD flag (in decr) */\r |
| 358 | #define CHTR_F_TRC 2 /* TRC flag (in decr) */\r |
| 359 | #define CHTR_F_EOF 4 /* EOF flag (in decr) */\r |
| 360 | \r |
| 361 | /* Channel interrupts - 7909 only */\r |
| 362 | \r |
| 363 | #define CHINT_CHA_SAV 042 /* start of chan block */\r |
| 364 | \r |
| 365 | /* Channel interrupt conditions - 7909 only */\r |
| 366 | \r |
| 367 | #define CHINT_ADPC 001 /* adapter check */\r |
| 368 | #define CHINT_ATN2 002 /* attention 2 - ni */\r |
| 369 | #define CHINT_ATN1 004 /* attention 1 */\r |
| 370 | #define CHINT_UEND 010 /* unusual end */\r |
| 371 | #define CHINT_SEQC 020 /* sequence check */\r |
| 372 | #define CHINT_IOC 040 /* IO check */\r |
| 373 | \r |
| 374 | /* Channel SMS flags - 7909 only */\r |
| 375 | \r |
| 376 | #define CHSMS_SEL2 0001 /* select 2nd - ni */\r |
| 377 | #define CHSMS_IATN2 0002 /* inhibit atn2 - ni */\r |
| 378 | #define CHSMS_IATN1 0004 /* inhibit atn1 */\r |
| 379 | #define CHSMS_IUEND 0010 /* inhibit uend */\r |
| 380 | #define CHSMS_BCD 0020 /* BCD conversion - ni */\r |
| 381 | #define CHSMS_RBCK 0040 /* read backwards - ni */\r |
| 382 | #define CHSMS_ENCI 0100 /* enable noncon - ni */\r |
| 383 | \r |
| 384 | /* Channel flags (7607 in right half, 7909 in left half) */\r |
| 385 | \r |
| 386 | #define CHF_CMD 00000000001 /* cmd done */\r |
| 387 | #define CHF_TWT (CHF_CMD)\r |
| 388 | #define CHF_TRC 00000000002 /* tape check */\r |
| 389 | #define CHF_EOF 00000000004 /* end of file */\r |
| 390 | #define CHF_BOT 00000000010 /* beginning of tape */\r |
| 391 | #define CHF_EOT 00000000020 /* end of tape */\r |
| 392 | #define CHF_LDW 00000000040 /* LCH waiting */\r |
| 393 | #define CHF_EOR 00000000100 /* end of record */\r |
| 394 | #define CHF_IRQ 00001000000 /* intr request */\r |
| 395 | #define CHF_INT 00002000000 /* intr in prog */\r |
| 396 | #define CHF_WRS 00004000000 /* write */\r |
| 397 | #define CHF_RDS 00010000000 /* read */\r |
| 398 | #define CHF_PWR 00020000000 /* prepare to write */\r |
| 399 | #define CHF_PRD 00040000000 /* prepare to read */\r |
| 400 | #define CHF_V_COND 24 /* cond register */\r |
| 401 | #define CHF_M_COND 077\r |
| 402 | #define CHF_ADPC (CHINT_ADPC << CHF_V_COND) /* adapter check */\r |
| 403 | #define CHF_ATN2 (CHINT_ATN2 << CHF_V_COND) /* attention 2 */\r |
| 404 | #define CHF_ATN1 (CHINT_ATN1 << CHF_V_COND) /* attention 1 */\r |
| 405 | #define CHF_UEND (CHINT_UEND << CHF_V_COND) /* unusual end */\r |
| 406 | #define CHF_SEQC (CHINT_SEQC << CHF_V_COND) /* sequence check */\r |
| 407 | #define CHF_IOC (CHINT_IOC << CHF_V_COND) /* IO check */\r |
| 408 | #define CHF_V_LCC 30 /* loop ctrl counter */\r |
| 409 | #define CHF_M_LCC 077\r |
| 410 | \r |
| 411 | #define CHF_CLR_7909 07775000177 /* 7909 clear flags */\r |
| 412 | #define CHF_SDC_7909 07776000000 /* 7909 SDC flags */\r |
| 413 | \r |
| 414 | /* Channel characteristics (in dev.flags) */\r |
| 415 | \r |
| 416 | #define DEV_7909 (1u << (DEV_V_UF + 0))\r |
| 417 | #define DEV_7289 (1u << (DEV_V_UF + 1))\r |
| 418 | #define DEV_CDLP (1u << (DEV_V_UF + 2))\r |
| 419 | #define DEV_7750 (1u << (DEV_V_UF + 3))\r |
| 420 | #define DEV_7631 (1u << (DEV_V_UF + 4))\r |
| 421 | \r |
| 422 | /* Unit addresses - 7607/7289 only */\r |
| 423 | \r |
| 424 | #define U_V_CH 9 /* channel number */\r |
| 425 | #define U_M_CH 077\r |
| 426 | #define U_V_UNIT 0\r |
| 427 | #define U_M_UNIT 0777\r |
| 428 | #define GET_U_CH(x) (((((uint32) (x)) >> U_V_CH) & U_M_CH) - 1)\r |
| 429 | #define GET_U_UNIT(x) ((((uint32) (x)) >> U_V_UNIT) & U_M_UNIT)\r |
| 430 | \r |
| 431 | #define U_MTBCD 0201 /* BCD tape */\r |
| 432 | #define U_MTBIN 0221 /* binary tape */\r |
| 433 | #define U_CDR 0321 /* card reader */\r |
| 434 | #define U_CDP 0341 /* card punch */\r |
| 435 | #define U_LPBCD 0361 /* BCD print */\r |
| 436 | #define U_LPBIN 0362 /* binary print */\r |
| 437 | #define U_DRM 0330 /* 7320A drum */\r |
| 438 | \r |
| 439 | #define MT_NUMDR 10\r |
| 440 | \r |
| 441 | /* CTSS Chronolog clock */\r |
| 442 | \r |
| 443 | #define CHRONO_CH (CH_A) /* channel A */\r |
| 444 | #define CHRONO_UNIT (7) /* unit 7 */\r |
| 445 | \r |
| 446 | /* Interval timer */\r |
| 447 | \r |
| 448 | #define CLK_CTR 05 /* counter */\r |
| 449 | #define CLK_TPS 60 /* 60Hz */\r |
| 450 | #define TMR_CLK 0 /* use timer 0 */\r |
| 451 | #define TMR_COM 1 /* 7750 timer */\r |
| 452 | \r |
| 453 | /* Function prototypes and macros */\r |
| 454 | \r |
| 455 | #define ReadP(p) M[p]\r |
| 456 | #define WriteP(p,d) M[p] = d\r |
| 457 | \r |
| 458 | void cpu_ent_hist (uint32 pc, uint32 ea, t_uint64 ir, t_uint64 opnd);\r |
| 459 | t_stat ch_show_chan (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 460 | t_stat ch6_end_nds (uint32 ch);\r |
| 461 | uint32 ch6_set_flags (uint32 ch, uint32 unit, uint32 flags);\r |
| 462 | t_stat ch6_err_disc (uint32 ch, uint32 unit, uint32 flags);\r |
| 463 | t_stat ch6_req_rd (uint32 ch, uint32 unit, t_uint64 val, uint32 flags);\r |
| 464 | t_stat ch6_req_wr (uint32 ch, uint32 unit);\r |
| 465 | t_bool ch6_qconn (uint32 ch, uint32 unit);\r |
| 466 | t_stat ch9_req_rd (uint32 ch, t_uint64 val);\r |
| 467 | void ch9_set_atn (uint32 ch);\r |
| 468 | void ch9_set_ioc (uint32 ch);\r |
| 469 | void ch9_set_end (uint32 ch, uint32 ireq);\r |
| 470 | t_bool ch9_qconn (uint32 ch);\r |
| 471 | void ch_set_map (void);\r |
| 472 | t_bool ch_qidle (void);\r |
| 473 | \r |
| 474 | #endif\r |