| 1 | /* nova_sys.c: NOVA simulator interface\r |
| 2 | \r |
| 3 | Copyright (c) 1993-2008, Robert M. Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | 04-Jul-07 BKR DEC's IOF/ION changed to DG's INTDS/INTEN mnemonic,\r |
| 27 | Fixed QTY/ADCV device name,\r |
| 28 | RDSW changed to DDG's READS mnemonic,\r |
| 29 | fixed/enhanced 'load' command for DG-compatible binary tape format\r |
| 30 | 26-Mar-04 RMS Fixed warning with -std=c99\r |
| 31 | 14-Jan-04 BKR Added support for QTY and ALM\r |
| 32 | 04-Jan-04 RMS Fixed 64b issues found by VMS 8.1\r |
| 33 | 24-Nov-03 CEO Added symbolic support for LEF instruction\r |
| 34 | 17-Sep-01 RMS Removed multiconsole support\r |
| 35 | 31-May-01 RMS Added multiconsole support\r |
| 36 | 14-Mar-01 RMS Revised load/dump interface (again)\r |
| 37 | 22-Dec-00 RMS Added second terminal support\r |
| 38 | 10-Dec-00 RMS Added Eclipse support\r |
| 39 | 08-Dec-00 BKR Added plotter support\r |
| 40 | 30-Oct-00 RMS Added support for examine to file\r |
| 41 | 15-Oct-00 RMS Added stack, byte, trap instructions\r |
| 42 | 14-Apr-99 RMS Changed t_addr to unsigned\r |
| 43 | 27-Oct-98 RMS V2.4 load interface\r |
| 44 | 24-Sep-97 RMS Fixed bug in device name table (found by Charles Owen)\r |
| 45 | */\r |
| 46 | \r |
| 47 | #include "nova_defs.h"\r |
| 48 | #include <ctype.h>\r |
| 49 | \r |
| 50 | extern DEVICE cpu_dev;\r |
| 51 | extern UNIT cpu_unit;\r |
| 52 | extern DEVICE ptr_dev;\r |
| 53 | extern DEVICE ptp_dev;\r |
| 54 | extern DEVICE plt_dev;\r |
| 55 | extern DEVICE tti_dev;\r |
| 56 | extern DEVICE tto_dev;\r |
| 57 | extern DEVICE tti1_dev;\r |
| 58 | extern DEVICE tto1_dev;\r |
| 59 | extern DEVICE clk_dev;\r |
| 60 | extern DEVICE lpt_dev;\r |
| 61 | extern DEVICE dkp_dev;\r |
| 62 | extern DEVICE dsk_dev;\r |
| 63 | extern DEVICE mta_dev;\r |
| 64 | extern DEVICE qty_dev;\r |
| 65 | extern DEVICE alm_dev;\r |
| 66 | extern REG cpu_reg[];\r |
| 67 | extern uint16 M[];\r |
| 68 | extern int32 saved_PC;\r |
| 69 | extern int32 AMASK;\r |
| 70 | \r |
| 71 | #if defined (ECLIPSE)\r |
| 72 | \r |
| 73 | extern DEVICE map_dev;\r |
| 74 | extern DEVICE fpu_dev;\r |
| 75 | extern DEVICE pit_dev;\r |
| 76 | extern int32 Usermap;\r |
| 77 | extern int32 MapStat;\r |
| 78 | \r |
| 79 | #endif\r |
| 80 | \r |
| 81 | extern int32 sim_switches;\r |
| 82 | \r |
| 83 | \r |
| 84 | /* SCP data structures\r |
| 85 | \r |
| 86 | sim_name simulator name string\r |
| 87 | sim_PC pointer to saved PC register descriptor\r |
| 88 | sim_emax number of words needed for examine\r |
| 89 | sim_devices array of pointers to simulated devices\r |
| 90 | sim_stop_messages array of pointers to stop messages\r |
| 91 | sim_load binary loader\r |
| 92 | */\r |
| 93 | \r |
| 94 | #if defined (ECLIPSE)\r |
| 95 | char sim_name[] = "ECLIPSE";\r |
| 96 | #else\r |
| 97 | char sim_name[] = "NOVA";\r |
| 98 | #endif\r |
| 99 | \r |
| 100 | REG *sim_PC = &cpu_reg[0];\r |
| 101 | \r |
| 102 | int32 sim_emax = 4;\r |
| 103 | \r |
| 104 | DEVICE *sim_devices[] = {\r |
| 105 | &cpu_dev,\r |
| 106 | #if defined (ECLIPSE)\r |
| 107 | &map_dev,\r |
| 108 | &fpu_dev,\r |
| 109 | &pit_dev,\r |
| 110 | #endif\r |
| 111 | &ptr_dev,\r |
| 112 | &ptp_dev,\r |
| 113 | &tti_dev,\r |
| 114 | &tto_dev,\r |
| 115 | &tti1_dev,\r |
| 116 | &tto1_dev,\r |
| 117 | &clk_dev,\r |
| 118 | &plt_dev,\r |
| 119 | &lpt_dev,\r |
| 120 | &dsk_dev,\r |
| 121 | &dkp_dev,\r |
| 122 | &mta_dev,\r |
| 123 | &qty_dev,\r |
| 124 | &alm_dev,\r |
| 125 | NULL\r |
| 126 | };\r |
| 127 | \r |
| 128 | const char *sim_stop_messages[] = {\r |
| 129 | "Unknown error",\r |
| 130 | "Unknown I/O instruction",\r |
| 131 | "HALT instruction",\r |
| 132 | "Breakpoint",\r |
| 133 | "Nested indirect address limit exceeded",\r |
| 134 | "Nested indirect interrupt or trap address limit exceeded",\r |
| 135 | "Read breakpoint",\r |
| 136 | "Write breakpoint"\r |
| 137 | };\r |
| 138 | \r |
| 139 | /* Binary loader\r |
| 140 | \r |
| 141 | Loader format consists of blocks, optionally preceded, separated, and\r |
| 142 | followed by zeroes. Each block consists of:\r |
| 143 | \r |
| 144 | lo_count\r |
| 145 | hi_count\r |
| 146 | lo_origin\r |
| 147 | hi_origin\r |
| 148 | lo_checksum\r |
| 149 | hi_checksum\r |
| 150 | lo_data byte ---\r |
| 151 | hi_data byte |\r |
| 152 | : > -count words\r |
| 153 | lo_data byte |\r |
| 154 | hi_data byte ---\r |
| 155 | \r |
| 156 | If the word count is [0,-20], then the block is normal data.\r |
| 157 | If the word count is [-21,-n], then the block is repeated data.\r |
| 158 | If the word count is 1, the block is the start address.\r |
| 159 | If the word count is >1, the block is an error block.\r |
| 160 | \r |
| 161 | Notes:\r |
| 162 | 'start' block terminates loading.\r |
| 163 | 'start' block starting address 1B0 = do not auto-start, 0B0 = auto-start.\r |
| 164 | 'start' block starting address is saved in 'save_PC' so a "continue"\r |
| 165 | should start the program.\r |
| 166 | \r |
| 167 | specify -i switch ignores checksum errors\r |
| 168 | \r |
| 169 | \r |
| 170 | internal state machine:\r |
| 171 | \r |
| 172 | 0,1 get byte count (low and high), ignore leader bytes (<000>)\r |
| 173 | 2,3 get origin\r |
| 174 | 4,5 get checksum\r |
| 175 | 6,7 process data block\r |
| 176 | 8 process 'ignore' (error) block\r |
| 177 | */\r |
| 178 | \r |
| 179 | t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)\r |
| 180 | {\r |
| 181 | int32 data, csum, count, state, i;\r |
| 182 | int32 origin;\r |
| 183 | int pos ;\r |
| 184 | int block_start ;\r |
| 185 | int done ;\r |
| 186 | \r |
| 187 | if ((*cptr != 0) || (flag != 0))\r |
| 188 | return ( SCPE_ARG ) ;\r |
| 189 | state = 0;\r |
| 190 | block_start = -1 ;\r |
| 191 | done = 0 ;\r |
| 192 | for ( pos = 0 ; (! done) && ((i=getc(fileref)) != EOF) ; ++pos )\r |
| 193 | {\r |
| 194 | i &= 0x00FF ; /* (insure no sign extension) */\r |
| 195 | switch (state) {\r |
| 196 | case 0: /* leader */\r |
| 197 | count = i;\r |
| 198 | state = (count != 0) ;\r |
| 199 | if ( state )\r |
| 200 | block_start = pos ;\r |
| 201 | break;\r |
| 202 | case 1: /* high count */\r |
| 203 | csum = count = (i << 8) | count ;\r |
| 204 | state = 2;\r |
| 205 | break;\r |
| 206 | case 2: /* low origin */\r |
| 207 | origin = i;\r |
| 208 | state = 3;\r |
| 209 | break ;\r |
| 210 | \r |
| 211 | case 3: /* high origin */\r |
| 212 | origin = (i << 8) | origin;\r |
| 213 | csum = csum + origin;\r |
| 214 | state = 4;\r |
| 215 | break;\r |
| 216 | case 4: /* low checksum */\r |
| 217 | csum = csum + i;\r |
| 218 | state = 5;\r |
| 219 | break;\r |
| 220 | case 5: /* high checksum */\r |
| 221 | csum = (csum + (i << 8)) & 0xFFFF ;\r |
| 222 | if (count == 1)\r |
| 223 | {\r |
| 224 | /* 'start' block */\r |
| 225 | /* do any auto-start check or inhibit check */\r |
| 226 | saved_PC = (origin & 077777) ; /* 0B0 = auto-start program */\r |
| 227 | /* 1B0 = do not auto start */\r |
| 228 | state = 0 ; /* indicate okay state */\r |
| 229 | done = 1 ; /* we're done! */\r |
| 230 | if ( ! (origin & 0x8000) )\r |
| 231 | {\r |
| 232 | printf( "auto start @ %05o \n", (origin & 0x7FFF) ) ;\r |
| 233 | }\r |
| 234 | break ;\r |
| 235 | }\r |
| 236 | if ( ((count & 0x8000) == 0) && (count > 1))\r |
| 237 | {\r |
| 238 | /* 'ignore' block */\r |
| 239 | state = 8 ;\r |
| 240 | }\r |
| 241 | /* 'data' or 'repeat' block */\r |
| 242 | count = 0200000 - count ;\r |
| 243 | if ( count <= 020 )\r |
| 244 | {\r |
| 245 | /* 'data' block */\r |
| 246 | state = 6 ;\r |
| 247 | break ;\r |
| 248 | }\r |
| 249 | /* 'repeat' block (multiple data) */\r |
| 250 | \r |
| 251 | if (count > 020) { /* large block */\r |
| 252 | for (count = count - 1; count > 1; count--) {\r |
| 253 | if (origin >= AMASK /* MEMSIZE? */)\r |
| 254 | {\r |
| 255 | return ( SCPE_NXM );\r |
| 256 | }\r |
| 257 | M[origin] = data;\r |
| 258 | origin = origin + 1;\r |
| 259 | }\r |
| 260 | state = 0 ;\r |
| 261 | }\r |
| 262 | state = 0;\r |
| 263 | break;\r |
| 264 | case 6: /* low data */\r |
| 265 | data = i;\r |
| 266 | state = 7;\r |
| 267 | break;\r |
| 268 | case 7: /* high data */\r |
| 269 | data = (i << 8) | data;\r |
| 270 | csum = (csum + data) & 0xFFFF ;\r |
| 271 | \r |
| 272 | if (origin >= AMASK /* MEMSIZE? */)\r |
| 273 | return SCPE_NXM;\r |
| 274 | M[origin] = data;\r |
| 275 | origin = origin + 1;\r |
| 276 | count = count - 1;\r |
| 277 | if (count == 0) {\r |
| 278 | if ( csum )\r |
| 279 | {\r |
| 280 | printf( "checksum error: block start at %d [0x%x] \n", block_start, block_start ) ;\r |
| 281 | printf( "calculated: 0%o [0x%4x]\n", csum, csum ) ;\r |
| 282 | if ( ! (sim_switches & SWMASK('I')) )\r |
| 283 | return SCPE_CSUM;\r |
| 284 | }\r |
| 285 | state = 0;\r |
| 286 | break;\r |
| 287 | }\r |
| 288 | state = 6;\r |
| 289 | break;\r |
| 290 | case 8: /* error (ignore) block */\r |
| 291 | if (i == 0377)\r |
| 292 | state = 0; /* (wait for 'RUBOUT' char) */\r |
| 293 | break;\r |
| 294 | } /* end switch */\r |
| 295 | } /* end while */\r |
| 296 | \r |
| 297 | /* Ok to find end of tape between blocks or in error state */\r |
| 298 | \r |
| 299 | return ( ((state == 0) || (state == 8)) ? SCPE_OK : SCPE_FMT ) ;\r |
| 300 | }\r |
| 301 | \r |
| 302 | \r |
| 303 | /* Symbol tables */\r |
| 304 | \r |
| 305 | #define I_V_FL 18 /* flag bits */\r |
| 306 | #define I_M_FL 037 /* flag width */\r |
| 307 | #define I_V_NPN 000 /* no operands */\r |
| 308 | #define I_V_R 001 /* reg */\r |
| 309 | #define I_V_D 002 /* device */\r |
| 310 | #define I_V_RD 003 /* reg,device */\r |
| 311 | #define I_V_M 004 /* mem addr */\r |
| 312 | #define I_V_RM 005 /* reg,mem addr */\r |
| 313 | #define I_V_RR 006 /* operate */\r |
| 314 | #define I_V_BY 007 /* Nova byte pointer */\r |
| 315 | #define I_V_2AC 010 /* reg,reg */\r |
| 316 | #define I_V_RSI 011 /* reg,short imm */\r |
| 317 | #define I_V_LI 012 /* long imm */\r |
| 318 | #define I_V_RLI 013 /* reg,long imm */\r |
| 319 | #define I_V_LM 014 /* long mem addr */\r |
| 320 | #define I_V_RLM 015 /* reg,long mem addr */\r |
| 321 | #define I_V_FRM 016 /* flt reg,long mem addr */\r |
| 322 | #define I_V_FST 017 /* flt long mem, status */\r |
| 323 | #define I_V_XP 020 /* XOP */\r |
| 324 | #define I_NPN (I_V_NPN << I_V_FL)\r |
| 325 | #define I_R (I_V_R << I_V_FL)\r |
| 326 | #define I_D (I_V_D << I_V_FL)\r |
| 327 | #define I_RD (I_V_RD << I_V_FL)\r |
| 328 | #define I_M (I_V_M << I_V_FL)\r |
| 329 | #define I_RM (I_V_RM << I_V_FL)\r |
| 330 | #define I_RR (I_V_RR << I_V_FL)\r |
| 331 | #define I_BY (I_V_BY << I_V_FL)\r |
| 332 | #define I_2AC (I_V_2AC << I_V_FL)\r |
| 333 | #define I_RSI (I_V_RSI << I_V_FL)\r |
| 334 | #define I_LI (I_V_LI << I_V_FL)\r |
| 335 | #define I_RLI (I_V_RLI << I_V_FL)\r |
| 336 | #define I_LM (I_V_LM << I_V_FL)\r |
| 337 | #define I_RLM (I_V_RLM << I_V_FL)\r |
| 338 | #define I_FRM (I_V_FRM << I_V_FL)\r |
| 339 | #define I_FST (I_V_FST << I_V_FL)\r |
| 340 | #define I_XP (I_V_XP << I_V_FL)\r |
| 341 | \r |
| 342 | static const int32 masks[] = {\r |
| 343 | 0177777, 0163777, 0177700, 0163700,\r |
| 344 | 0174000, 0160000, 0103770, 0163477,\r |
| 345 | 0103777, 0103777, 0177777, 0163777,\r |
| 346 | 0176377, 0162377, 0103777, 0163777,\r |
| 347 | 0100077\r |
| 348 | };\r |
| 349 | \r |
| 350 | static const char *opcode[] = {\r |
| 351 | "JMP", "JSR", "ISZ", "DSZ",\r |
| 352 | "LDA", "STA",\r |
| 353 | #if defined (ECLIPSE)\r |
| 354 | "ADI", "SBI", "DAD", "DSB",\r |
| 355 | "IOR", "XOR", "ANC", "XCH",\r |
| 356 | "SGT", "SGE", "LSH", "DLSH",\r |
| 357 | "HXL", "HXR", "DHXL", "DHXR",\r |
| 358 | "BTO", "BTZ", "SBZ", "SZBO",\r |
| 359 | "LOB", "LRB", "COB", "LDB",\r |
| 360 | "STB", "PSH", "POP",\r |
| 361 | "LMP", "SYC",\r |
| 362 | "PSHR", "POPB", "BAM", "POPJ",\r |
| 363 | "RTN", "BLM", "DIVX",\r |
| 364 | "MUL", "MULS", "DIV", "DIVS",\r |
| 365 | "SAVE", "RSTR",\r |
| 366 | "XOP",\r |
| 367 | "FAS", "FAD", "FSS", "FSD",\r |
| 368 | "FMS", "FMD", "FDS", "FDD",\r |
| 369 | "FAMS", "FAMD", "FSMS", "FSMD",\r |
| 370 | "FMMS", "FMMD", "FDMS", "FDMD",\r |
| 371 | "FLDS", "FLDD", "FSTS", "FSTD",\r |
| 372 | "FLAS", "FLMD", "FFAS", "FFMD",\r |
| 373 | "FNOM", "FRH", "FAB", "FNEG",\r |
| 374 | "FSCAL", "FEXP", "FINT", "FHLV",\r |
| 375 | "FNS", "FSA", "FSEQ", "FSNE",\r |
| 376 | "FSLT", "FSGE", "FSLE", "FSGT",\r |
| 377 | "FSNM", "FSND", "FSNU", "FSNUD",\r |
| 378 | "FSNO", "FSNOD", "FSNUO", "FSNER",\r |
| 379 | "FSST", "FLST",\r |
| 380 | "FTE", "FTD", "FCLE",\r |
| 381 | "FPSH", "FPOP",\r |
| 382 | "FCMP", "FMOV",\r |
| 383 | "CMV", "CMP", "CTR", "CMT",\r |
| 384 | "EJMP", "EJSR", "EISZ", "EDSZ",\r |
| 385 | "ELDA", "ESTA", "ELEF",\r |
| 386 | "ELDB", "ESTB", "DSPA",\r |
| 387 | "PSHJ", "CLM", "SNB",\r |
| 388 | "MSP", "XCT", "HLV",\r |
| 389 | "IORI", "XORI", "ANDI", "ADDI",\r |
| 390 | #endif\r |
| 391 | "COM", "COMZ", "COMO", "COMC",\r |
| 392 | "COML", "COMZL", "COMOL", "COMCL",\r |
| 393 | "COMR", "COMZR", "COMOR", "COMCR",\r |
| 394 | "COMS", "COMZS", "COMOS", "COMCS",\r |
| 395 | "COM#", "COMZ#", "COMO#", "COMC#",\r |
| 396 | "COML#", "COMZL#", "COMOL#", "COMCL#",\r |
| 397 | "COMR#", "COMZR#", "COMOR#", "COMCR#",\r |
| 398 | "COMS#", "COMZS#", "COMOS#", "COMCS#",\r |
| 399 | "NEG", "NEGZ", "NEGO", "NEGC",\r |
| 400 | "NEGL", "NEGZL", "NEGOL", "NEGCL",\r |
| 401 | "NEGR", "NEGZR", "NEGOR", "NEGCR",\r |
| 402 | "NEGS", "NEGZS", "NEGOS", "NEGCS",\r |
| 403 | "NEG#", "NEGZ#", "NEGO#", "NEGC#",\r |
| 404 | "NEGL#", "NEGZL#", "NEGOL#", "NEGCL#",\r |
| 405 | "NEGR#", "NEGZR#", "NEGOR#", "NEGCR#",\r |
| 406 | "NEGS#", "NEGZS#", "NEGOS#", "NEGCS#",\r |
| 407 | "MOV", "MOVZ", "MOVO", "MOVC",\r |
| 408 | "MOVL", "MOVZL", "MOVOL", "MOVCL",\r |
| 409 | "MOVR", "MOVZR", "MOVOR", "MOVCR",\r |
| 410 | "MOVS", "MOVZS", "MOVOS", "MOVCS",\r |
| 411 | "MOV#", "MOVZ#", "MOVO#", "MOVC#",\r |
| 412 | "MOVL#", "MOVZL#", "MOVOL#", "MOVCL#",\r |
| 413 | "MOVR#", "MOVZR#", "MOVOR#", "MOVCR#",\r |
| 414 | "MOVS#", "MOVZS#", "MOVOS#", "MOVCS#",\r |
| 415 | "INC", "INCZ", "INCO", "INCC",\r |
| 416 | "INCL", "INCZL", "INCOL", "INCCL",\r |
| 417 | "INCR", "INCZR", "INCOR", "INCCR",\r |
| 418 | "INCS", "INCZS", "INCOS", "INCCS",\r |
| 419 | "INC#", "INCZ#", "INCO#", "INCC#",\r |
| 420 | "INCL#", "INCZL#", "INCOL#", "INCCL#",\r |
| 421 | "INCR#", "INCZR#", "INCOR#", "INCCR#",\r |
| 422 | "INCS#", "INCZS#", "INCOS#", "INCCS#",\r |
| 423 | "ADC", "ADCZ", "ADCO", "ADCC",\r |
| 424 | "ADCL", "ADCZL", "ADCOL", "ADCCL",\r |
| 425 | "ADCR", "ADCZR", "ADCOR", "ADCCR",\r |
| 426 | "ADCS", "ADCZS", "ADCOS", "ADCCS",\r |
| 427 | "ADC#", "ADCZ#", "ADCO#", "ADCC#",\r |
| 428 | "ADCL#", "ADCZL#", "ADCOL#", "ADCCL#",\r |
| 429 | "ADCR#", "ADCZR#", "ADCOR#", "ADCCR#",\r |
| 430 | "ADCS#", "ADCZS#", "ADCOS#", "ADCCS#",\r |
| 431 | "SUB", "SUBZ", "SUBO", "SUBC",\r |
| 432 | "SUBL", "SUBZL", "SUBOL", "SUBCL",\r |
| 433 | "SUBR", "SUBZR", "SUBOR", "SUBCR",\r |
| 434 | "SUBS", "SUBZS", "SUBOS", "SUBCS",\r |
| 435 | "SUB#", "SUBZ#", "SUBO#", "SUBC#",\r |
| 436 | "SUBL#", "SUBZL#", "SUBOL#", "SUBCL#",\r |
| 437 | "SUBR#", "SUBZR#", "SUBOR#", "SUBCR#",\r |
| 438 | "SUBS#", "SUBZS#", "SUBOS#", "SUBCS#",\r |
| 439 | "ADD", "ADDZ", "ADDO", "ADDC",\r |
| 440 | "ADDL", "ADDZL", "ADDOL", "ADDCL",\r |
| 441 | "ADDR", "ADDZR", "ADDOR", "ADDCR",\r |
| 442 | "ADDS", "ADDZS", "ADDOS", "ADDCS",\r |
| 443 | "ADD#", "ADDZ#", "ADDO#", "ADDC#",\r |
| 444 | "ADDL#", "ADDZL#", "ADDOL#", "ADDCL#",\r |
| 445 | "ADDR#", "ADDZR#", "ADDOR#", "ADDCR#",\r |
| 446 | "ADDS#", "ADDZS#", "ADDOS#", "ADDCS#",\r |
| 447 | "AND", "ANDZ", "ANDO", "ANDC",\r |
| 448 | "ANDL", "ANDZL", "ANDOL", "ANDCL",\r |
| 449 | "ANDR", "ANDZR", "ANDOR", "ANDCR",\r |
| 450 | "ANDS", "ANDZS", "ANDOS", "ANDCS",\r |
| 451 | "AND#", "ANDZ#", "ANDO#", "ANDC#",\r |
| 452 | "ANDL#", "ANDZL#", "ANDOL#", "ANDCL#",\r |
| 453 | "ANDR#", "ANDZR#", "ANDOR#", "ANDCR#",\r |
| 454 | "ANDS#", "ANDZS#", "ANDOS#", "ANDCS#",\r |
| 455 | "INTEN", "INTDS",\r |
| 456 | "READS", "INTA", "MSKO", "IORST", "HALT",\r |
| 457 | #if !defined (ECLIPSE)\r |
| 458 | "MUL", "DIV", "MULS", "DIVS",\r |
| 459 | "PSHA", "POPA", "SAV", "RET",\r |
| 460 | "MTSP", "MTFP", "MFSP", "MFFP",\r |
| 461 | "LDB", "STB",\r |
| 462 | #endif\r |
| 463 | "NIO", "NIOS", "NIOC", "NIOP",\r |
| 464 | "DIA", "DIAS", "DIAC", "DIAP",\r |
| 465 | "DOA", "DOAS", "DOAC", "DOAP",\r |
| 466 | "DIB", "DIBS", "DIBC", "DIBP",\r |
| 467 | "DOB", "DOBS", "DOBC", "DOBP",\r |
| 468 | "DIC", "DICS", "DICC", "DICP",\r |
| 469 | "DOC", "DOCS", "DOCC", "DOCP",\r |
| 470 | "SKPBN", "SKPBZ", "SKPDN", "SKPDZ",\r |
| 471 | #if defined (ECLIPSE)\r |
| 472 | "LEF", "LEF", "LEF", "LEF",\r |
| 473 | #endif\r |
| 474 | NULL\r |
| 475 | };\r |
| 476 | \r |
| 477 | static const int32 opc_val[] = {\r |
| 478 | 0000000+I_M, 0004000+I_M, 0010000+I_M, 0014000+I_M,\r |
| 479 | 0020000+I_RM, 0040000+I_RM,\r |
| 480 | #if defined (ECLIPSE)\r |
| 481 | 0100010+I_RSI, 0100110+I_RSI, 0100210+I_2AC, 0100310+I_2AC,\r |
| 482 | 0100410+I_2AC, 0100510+I_2AC, 0100610+I_2AC, 0100710+I_2AC,\r |
| 483 | 0101010+I_2AC, 0101110+I_2AC, 0101210+I_RSI, 0101310+I_RSI,\r |
| 484 | 0101410+I_RSI, 0101510+I_RSI, 0101610+I_RSI, 0101710+I_RSI,\r |
| 485 | 0102010+I_2AC, 0102110+I_2AC, 0102210+I_2AC, 0102310+I_2AC,\r |
| 486 | 0102410+I_2AC, 0102510+I_2AC, 0102610+I_2AC, 0102710+I_2AC,\r |
| 487 | 0103010+I_2AC, 0103110+I_2AC, 0103210+I_2AC,\r |
| 488 | 0113410+I_NPN, 0103510+I_2AC,\r |
| 489 | 0103710+I_NPN, 0107710+I_NPN, 0113710+I_NPN, 0117710+I_NPN,\r |
| 490 | 0127710+I_NPN, 0133710+I_NPN, 0137710+I_NPN,\r |
| 491 | 0143710+I_NPN, 0147710+I_NPN, 0153710+I_NPN, 0157710+I_NPN,\r |
| 492 | 0163710+I_LI, 0167710+I_NPN,\r |
| 493 | 0100030+I_XP,\r |
| 494 | 0100050+I_2AC, 0100150+I_2AC, 0100250+I_2AC, 0100350+I_2AC,\r |
| 495 | 0100450+I_2AC, 0100550+I_2AC, 0100650+I_2AC, 0100750+I_2AC,\r |
| 496 | 0101050+I_FRM, 0101150+I_FRM, 0101250+I_FRM, 0101350+I_FRM,\r |
| 497 | 0101450+I_FRM, 0101550+I_FRM, 0101650+I_FRM, 0101750+I_FRM,\r |
| 498 | 0102050+I_FRM, 0102150+I_FRM, 0102250+I_FRM, 0102350+I_FRM,\r |
| 499 | 0102450+I_2AC, 0102550+I_FRM, 0102650+I_2AC, 0102750+I_FRM,\r |
| 500 | 0103050+I_R, 0123050+I_R, 0143050+I_R, 0163050+I_R,\r |
| 501 | 0103150+I_R, 0123150+I_R, 0143150+I_R, 0163150+I_R,\r |
| 502 | 0103250+I_NPN, 0107250+I_NPN, 0113250+I_NPN, 0117250+I_NPN,\r |
| 503 | 0123250+I_NPN, 0127250+I_NPN, 0133250+I_NPN, 0137250+I_NPN,\r |
| 504 | 0143250+I_NPN, 0147250+I_NPN, 0153250+I_NPN, 0157250+I_NPN,\r |
| 505 | 0163250+I_NPN, 0167250+I_NPN, 0173250+I_NPN, 0177250+I_NPN,\r |
| 506 | 0103350+I_FST, 0123350+I_FST,\r |
| 507 | 0143350+I_NPN, 0147350+I_NPN, 0153350+I_NPN,\r |
| 508 | 0163350+I_NPN, 0167350+I_NPN,\r |
| 509 | 0103450+I_2AC, 0103550+I_2AC,\r |
| 510 | 0153650+I_NPN, 0157650+I_NPN, 0163650+I_NPN, 0167650+I_NPN,\r |
| 511 | 0102070+I_LM, 0106070+I_LM, 0112070+I_LM, 0116070+I_LM,\r |
| 512 | 0122070+I_RLM, 0142070+I_RLM, 0162070+I_RLM,\r |
| 513 | 0102170+I_RLM, 0122170+I_RLM, 0142170+I_RLM,\r |
| 514 | 0102270+I_LM, 0102370+I_2AC, 0102770+I_2AC,\r |
| 515 | 0103370+I_R, 0123370+I_R, 0143370+I_R,\r |
| 516 | 0103770+I_RLI, 0123770+I_RLI, 0143770+I_RLI, 0163770+I_RLI, \r |
| 517 | #endif\r |
| 518 | 0100000+I_RR, 0100020+I_RR, 0100040+I_RR, 0100060+I_RR,\r |
| 519 | 0100100+I_RR, 0100120+I_RR, 0100140+I_RR, 0100160+I_RR,\r |
| 520 | 0100200+I_RR, 0100220+I_RR, 0100240+I_RR, 0100260+I_RR,\r |
| 521 | 0100300+I_RR, 0100320+I_RR, 0100340+I_RR, 0100360+I_RR,\r |
| 522 | 0100010+I_RR, 0100030+I_RR, 0100050+I_RR, 0100070+I_RR,\r |
| 523 | 0100110+I_RR, 0100130+I_RR, 0100150+I_RR, 0100170+I_RR,\r |
| 524 | 0100210+I_RR, 0100230+I_RR, 0100250+I_RR, 0100270+I_RR,\r |
| 525 | 0100310+I_RR, 0100330+I_RR, 0100350+I_RR, 0100370+I_RR,\r |
| 526 | 0100400+I_RR, 0100420+I_RR, 0100440+I_RR, 0100460+I_RR,\r |
| 527 | 0100500+I_RR, 0100520+I_RR, 0100540+I_RR, 0100560+I_RR,\r |
| 528 | 0100600+I_RR, 0100620+I_RR, 0100640+I_RR, 0100660+I_RR,\r |
| 529 | 0100700+I_RR, 0100720+I_RR, 0100740+I_RR, 0100760+I_RR,\r |
| 530 | 0100410+I_RR, 0100430+I_RR, 0100450+I_RR, 0100470+I_RR,\r |
| 531 | 0100510+I_RR, 0100530+I_RR, 0100550+I_RR, 0100570+I_RR,\r |
| 532 | 0100610+I_RR, 0100630+I_RR, 0100650+I_RR, 0100670+I_RR,\r |
| 533 | 0100710+I_RR, 0100730+I_RR, 0100750+I_RR, 0100770+I_RR,\r |
| 534 | 0101000+I_RR, 0101020+I_RR, 0101040+I_RR, 0101060+I_RR,\r |
| 535 | 0101100+I_RR, 0101120+I_RR, 0101140+I_RR, 0101160+I_RR,\r |
| 536 | 0101200+I_RR, 0101220+I_RR, 0101240+I_RR, 0101260+I_RR,\r |
| 537 | 0101300+I_RR, 0101320+I_RR, 0101340+I_RR, 0101360+I_RR,\r |
| 538 | 0101010+I_RR, 0101030+I_RR, 0101050+I_RR, 0101070+I_RR,\r |
| 539 | 0101110+I_RR, 0101130+I_RR, 0101150+I_RR, 0101170+I_RR,\r |
| 540 | 0101210+I_RR, 0101230+I_RR, 0101250+I_RR, 0101270+I_RR,\r |
| 541 | 0101310+I_RR, 0101330+I_RR, 0101350+I_RR, 0101370+I_RR,\r |
| 542 | 0101400+I_RR, 0101420+I_RR, 0101440+I_RR, 0101460+I_RR,\r |
| 543 | 0101500+I_RR, 0101520+I_RR, 0101540+I_RR, 0101560+I_RR,\r |
| 544 | 0101600+I_RR, 0101620+I_RR, 0101640+I_RR, 0101660+I_RR,\r |
| 545 | 0101700+I_RR, 0101720+I_RR, 0101740+I_RR, 0101760+I_RR,\r |
| 546 | 0101410+I_RR, 0101430+I_RR, 0101450+I_RR, 0101470+I_RR,\r |
| 547 | 0101510+I_RR, 0101530+I_RR, 0101550+I_RR, 0101570+I_RR,\r |
| 548 | 0101610+I_RR, 0101630+I_RR, 0101650+I_RR, 0101670+I_RR,\r |
| 549 | 0101710+I_RR, 0101730+I_RR, 0101750+I_RR, 0101770+I_RR,\r |
| 550 | 0102000+I_RR, 0102020+I_RR, 0102040+I_RR, 0102060+I_RR,\r |
| 551 | 0102100+I_RR, 0102120+I_RR, 0102140+I_RR, 0102160+I_RR,\r |
| 552 | 0102200+I_RR, 0102220+I_RR, 0102240+I_RR, 0102260+I_RR,\r |
| 553 | 0102300+I_RR, 0102320+I_RR, 0102340+I_RR, 0102360+I_RR,\r |
| 554 | 0102010+I_RR, 0102030+I_RR, 0102050+I_RR, 0102070+I_RR,\r |
| 555 | 0102110+I_RR, 0102130+I_RR, 0102150+I_RR, 0102170+I_RR,\r |
| 556 | 0102210+I_RR, 0102230+I_RR, 0102250+I_RR, 0102270+I_RR,\r |
| 557 | 0102310+I_RR, 0102330+I_RR, 0102350+I_RR, 0102370+I_RR,\r |
| 558 | 0102400+I_RR, 0102420+I_RR, 0102440+I_RR, 0102460+I_RR,\r |
| 559 | 0102500+I_RR, 0102520+I_RR, 0102540+I_RR, 0102560+I_RR,\r |
| 560 | 0102600+I_RR, 0102620+I_RR, 0102640+I_RR, 0102660+I_RR,\r |
| 561 | 0102700+I_RR, 0102720+I_RR, 0102740+I_RR, 0102760+I_RR,\r |
| 562 | 0102410+I_RR, 0102430+I_RR, 0102450+I_RR, 0102470+I_RR,\r |
| 563 | 0102510+I_RR, 0102530+I_RR, 0102550+I_RR, 0102570+I_RR,\r |
| 564 | 0102610+I_RR, 0102630+I_RR, 0102650+I_RR, 0102670+I_RR,\r |
| 565 | 0102710+I_RR, 0102730+I_RR, 0102750+I_RR, 0102770+I_RR,\r |
| 566 | 0103000+I_RR, 0103020+I_RR, 0103040+I_RR, 0103060+I_RR,\r |
| 567 | 0103100+I_RR, 0103120+I_RR, 0103140+I_RR, 0103160+I_RR,\r |
| 568 | 0103200+I_RR, 0103220+I_RR, 0103240+I_RR, 0103260+I_RR,\r |
| 569 | 0103300+I_RR, 0103320+I_RR, 0103340+I_RR, 0103360+I_RR,\r |
| 570 | 0103010+I_RR, 0103030+I_RR, 0103050+I_RR, 0103070+I_RR,\r |
| 571 | 0103110+I_RR, 0103130+I_RR, 0103150+I_RR, 0103170+I_RR,\r |
| 572 | 0103210+I_RR, 0103230+I_RR, 0103250+I_RR, 0103270+I_RR,\r |
| 573 | 0103310+I_RR, 0103330+I_RR, 0103350+I_RR, 0103370+I_RR,\r |
| 574 | 0103400+I_RR, 0103420+I_RR, 0103440+I_RR, 0103460+I_RR,\r |
| 575 | 0103500+I_RR, 0103520+I_RR, 0103540+I_RR, 0103560+I_RR,\r |
| 576 | 0103600+I_RR, 0103620+I_RR, 0103640+I_RR, 0103660+I_RR,\r |
| 577 | 0103700+I_RR, 0103720+I_RR, 0103740+I_RR, 0103760+I_RR,\r |
| 578 | 0103410+I_RR, 0103430+I_RR, 0103450+I_RR, 0103470+I_RR,\r |
| 579 | 0103510+I_RR, 0103530+I_RR, 0103550+I_RR, 0103570+I_RR,\r |
| 580 | 0103610+I_RR, 0103630+I_RR, 0103650+I_RR, 0103670+I_RR,\r |
| 581 | 0103710+I_RR, 0103730+I_RR, 0103750+I_RR, 0103770+I_RR,\r |
| 582 | 0060177+I_NPN, 0060277+I_NPN,\r |
| 583 | 0060477+I_R, 0061477+I_R, 0062077+I_R, 0062677+I_NPN, 0063077+I_NPN,\r |
| 584 | #if !defined (ECLIPSE)\r |
| 585 | 0073301+I_NPN, 0073101+I_NPN, 0077201+I_NPN, 0077001+I_NPN,\r |
| 586 | 0061401+I_R, 0061601+I_R, 0062401+I_NPN, 0062601+I_NPN,\r |
| 587 | 0061001+I_R, 0060001+I_R, 0061201+I_R, 0060201+I_R,\r |
| 588 | 0060401+I_BY, 0062001+I_BY,\r |
| 589 | #endif\r |
| 590 | 0060000+I_RD, 0060100+I_RD, 0060200+I_RD, 0060300+I_RD,\r |
| 591 | 0060400+I_RD, 0060500+I_RD, 0060600+I_RD, 0060700+I_RD,\r |
| 592 | 0061000+I_RD, 0061100+I_RD, 0061200+I_RD, 0061300+I_RD,\r |
| 593 | 0061400+I_RD, 0061500+I_RD, 0061600+I_RD, 0061700+I_RD,\r |
| 594 | 0062000+I_RD, 0062100+I_RD, 0062200+I_RD, 0062300+I_RD,\r |
| 595 | 0062400+I_RD, 0062500+I_RD, 0062600+I_RD, 0062700+I_RD,\r |
| 596 | 0063000+I_RD, 0063100+I_RD, 0063200+I_RD, 0063300+I_RD,\r |
| 597 | 0063400+I_D, 0063500+I_D, 0063600+I_D, 0063700+I_D,\r |
| 598 | #if defined (ECLIPSE)\r |
| 599 | 0064000+I_D, 0070000+I_D, 0074000+I_D, 0076000+I_D,\r |
| 600 | #endif\r |
| 601 | -1\r |
| 602 | };\r |
| 603 | \r |
| 604 | static const char *skip[] = {\r |
| 605 | "SKP", "SZC", "SNC", "SZR", "SNR", "SEZ", "SBN",\r |
| 606 | NULL\r |
| 607 | };\r |
| 608 | \r |
| 609 | static const char *device[] = {\r |
| 610 | #if defined (ECLIPSE)\r |
| 611 | "ERCC", "MAP",\r |
| 612 | #endif\r |
| 613 | "TTI", "TTO", "PTR", "PTP", "RTC", "PLT", "CDR", "LPT",\r |
| 614 | "DSK", "MTA", "DCM", "QTY" /* "ADCV" */, "DKP", "CAS",\r |
| 615 | "TTI1", "TTO1", "CPU",\r |
| 616 | NULL\r |
| 617 | };\r |
| 618 | \r |
| 619 | static const int32 dev_val[] = {\r |
| 620 | #if defined (ECLIPSE)\r |
| 621 | 002, 003,\r |
| 622 | #endif\r |
| 623 | 010, 011, 012, 013, 014, 015, 016, 017,\r |
| 624 | 020, 022, 024, 030, 033, 034, \r |
| 625 | 050, 051, 077,\r |
| 626 | -1\r |
| 627 | };\r |
| 628 | \r |
| 629 | /* Address decode\r |
| 630 | \r |
| 631 | Inputs:\r |
| 632 | *of = output stream\r |
| 633 | addr = current PC\r |
| 634 | ind = indirect flag\r |
| 635 | mode = addressing mode\r |
| 636 | disp = displacement\r |
| 637 | ext = true if extended address\r |
| 638 | cflag = true if decoding for CPU\r |
| 639 | Outputs:\r |
| 640 | return = error code\r |
| 641 | */\r |
| 642 | \r |
| 643 | t_stat fprint_addr (FILE *of, t_addr addr, int32 ind, int32 mode,\r |
| 644 | int32 disp, t_bool ext, int32 cflag)\r |
| 645 | {\r |
| 646 | int32 dsign, dmax;\r |
| 647 | \r |
| 648 | if (ext) dmax = AMASK + 1; /* get max disp */\r |
| 649 | else dmax = I_M_DISP + 1;\r |
| 650 | dsign = dmax >> 1; /* get disp sign */\r |
| 651 | if (ind) fprintf (of, "@"); /* indirect? */\r |
| 652 | switch (mode & 03) { /* mode */\r |
| 653 | \r |
| 654 | case 0: /* absolute */\r |
| 655 | fprintf (of, "%-o", disp);\r |
| 656 | break;\r |
| 657 | \r |
| 658 | case 1: /* PC rel */\r |
| 659 | if (disp & dsign) {\r |
| 660 | if (cflag) fprintf (of, "%-o", (addr - (dmax - disp)) & AMASK);\r |
| 661 | else fprintf (of, ".-%-o", dmax - disp);\r |
| 662 | }\r |
| 663 | else {\r |
| 664 | if (cflag) fprintf (of, "%-o", (addr + disp) & AMASK);\r |
| 665 | else fprintf (of, ".+%-o", disp);\r |
| 666 | }\r |
| 667 | break;\r |
| 668 | \r |
| 669 | case 2: /* AC2 rel */\r |
| 670 | if (disp & dsign) fprintf (of, "-%-o,2", dmax - disp);\r |
| 671 | else fprintf (of, "%-o,2", disp);\r |
| 672 | break;\r |
| 673 | \r |
| 674 | case 3: /* AC3 rel */\r |
| 675 | if (disp & dsign) fprintf (of, "-%-o,3", dmax - disp);\r |
| 676 | else fprintf (of, "%-o,3", disp);\r |
| 677 | break;\r |
| 678 | } /* end switch */\r |
| 679 | \r |
| 680 | return SCPE_OK;\r |
| 681 | }\r |
| 682 | \r |
| 683 | /* Symbolic output\r |
| 684 | \r |
| 685 | Inputs:\r |
| 686 | *of = output stream\r |
| 687 | addr = current PC\r |
| 688 | *val = pointer to values\r |
| 689 | *uptr = pointer to unit\r |
| 690 | sw = switches\r |
| 691 | Outputs:\r |
| 692 | status = error code\r |
| 693 | */\r |
| 694 | \r |
| 695 | t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,\r |
| 696 | UNIT *uptr, int32 sw)\r |
| 697 | {\r |
| 698 | int32 cflag, i, j, c1, c2, inst, inst1, dv, src, dst, skp;\r |
| 699 | int32 ind, mode, disp, dev;\r |
| 700 | int32 byac, extind, extdisp, xop;\r |
| 701 | \r |
| 702 | cflag = (uptr == NULL) || (uptr == &cpu_unit);\r |
| 703 | c1 = ((int32) val[0] >> 8) & 0177;\r |
| 704 | c2 = (int32) val[0] & 0177;\r |
| 705 | if (sw & SWMASK ('A')) { /* ASCII? */\r |
| 706 | fprintf (of, (c2 < 040)? "<%03o>": "%c", c2);\r |
| 707 | return SCPE_OK;\r |
| 708 | }\r |
| 709 | if (sw & SWMASK ('C')) { /* character? */\r |
| 710 | fprintf (of, (c1 < 040)? "<%03o>": "%c", c1);\r |
| 711 | fprintf (of, (c2 < 040)? "<%03o>": "%c", c2);\r |
| 712 | return SCPE_OK;\r |
| 713 | }\r |
| 714 | if (!(sw & SWMASK ('M'))) return SCPE_ARG; /* mnemonic? */\r |
| 715 | \r |
| 716 | /* Instruction decode */\r |
| 717 | \r |
| 718 | inst = (int32) val[0];\r |
| 719 | inst1 = (int32) val[1];\r |
| 720 | for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */\r |
| 721 | j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */\r |
| 722 | if ((opc_val[i] & 0177777) == (inst & masks[j])) { /* match? */\r |
| 723 | src = I_GETSRC (inst); /* opr fields */\r |
| 724 | dst = I_GETDST (inst);\r |
| 725 | skp = I_GETSKP (inst);\r |
| 726 | ind = inst & I_IND; /* mem ref fields */\r |
| 727 | mode = I_GETMODE (inst);\r |
| 728 | disp = I_GETDISP (inst);\r |
| 729 | dev = I_GETDEV (inst); /* IOT fields */\r |
| 730 | byac = I_GETPULSE (inst); /* byte fields */\r |
| 731 | xop = I_GETXOP (inst); /* XOP fields */\r |
| 732 | extind = inst1 & A_IND; /* extended fields */\r |
| 733 | extdisp = inst1 & AMASK;\r |
| 734 | for (dv = 0; (dev_val[dv] >= 0) && (dev_val[dv] != dev); dv++) ;\r |
| 735 | \r |
| 736 | switch (j) { /* switch on class */\r |
| 737 | \r |
| 738 | case I_V_NPN: /* no operands */\r |
| 739 | fprintf (of, "%s", opcode[i]); /* opcode */\r |
| 740 | break;\r |
| 741 | \r |
| 742 | case I_V_R: /* reg only */\r |
| 743 | fprintf (of, "%s %-o", opcode[i], dst);\r |
| 744 | break;\r |
| 745 | \r |
| 746 | case I_V_D: /* dev only */\r |
| 747 | #if defined (ECLIPSE)\r |
| 748 | if (Usermap && (MapStat & 0100)) { /* the evil LEF mode */\r |
| 749 | fprintf (of, "LEF %-o,", dst);\r |
| 750 | fprint_addr (of, addr, ind, mode, disp, FALSE, cflag);\r |
| 751 | break;\r |
| 752 | }\r |
| 753 | #endif\r |
| 754 | if (dev_val[dv] >= 0)\r |
| 755 | fprintf (of, "%s %s", opcode[i], device[dv]);\r |
| 756 | else fprintf (of, "%s %-o", opcode[i], dev);\r |
| 757 | break;\r |
| 758 | \r |
| 759 | case I_V_RD: /* reg, dev */\r |
| 760 | if (dev_val[dv] >= 0)\r |
| 761 | fprintf (of, "%s %-o,%s", opcode[i], dst, device[dv]);\r |
| 762 | else fprintf (of, "%s %-o,%-o", opcode[i], dst, dev);\r |
| 763 | break;\r |
| 764 | \r |
| 765 | case I_V_M: /* addr only */\r |
| 766 | fprintf (of, "%s ", opcode[i]);\r |
| 767 | fprint_addr (of, addr, ind, mode, disp, FALSE, cflag);\r |
| 768 | break;\r |
| 769 | \r |
| 770 | case I_V_RM: /* reg, addr */\r |
| 771 | fprintf (of, "%s %-o,", opcode[i], dst);\r |
| 772 | fprint_addr (of, addr, ind, mode, disp, FALSE, cflag);\r |
| 773 | break;\r |
| 774 | \r |
| 775 | case I_V_RR: /* operate */\r |
| 776 | fprintf (of, "%s %-o,%-o", opcode[i], src, dst);\r |
| 777 | if (skp) fprintf (of, ",%s", skip[skp-1]);\r |
| 778 | break;\r |
| 779 | \r |
| 780 | case I_V_BY: /* byte */\r |
| 781 | fprintf (of, "%s %-o,%-o", opcode[i], byac, dst);\r |
| 782 | break;\r |
| 783 | \r |
| 784 | case I_V_2AC: /* reg, reg */\r |
| 785 | fprintf (of, "%s %-o,%-o", opcode[i], src, dst);\r |
| 786 | break;\r |
| 787 | \r |
| 788 | case I_V_RSI: /* reg, short imm */\r |
| 789 | fprintf (of, "%s %-o,%-o", opcode[i], src + 1, dst);\r |
| 790 | break;\r |
| 791 | \r |
| 792 | case I_V_LI: /* long imm */\r |
| 793 | fprintf (of, "%s %-o", opcode[i], inst1);\r |
| 794 | return -1;\r |
| 795 | \r |
| 796 | case I_V_RLI: /* reg, long imm */\r |
| 797 | fprintf (of, "%s %-o,%-o", opcode[i], inst1, dst);\r |
| 798 | return -1;\r |
| 799 | \r |
| 800 | case I_V_LM: /* long addr */\r |
| 801 | fprintf (of, "%s ", opcode[i]);\r |
| 802 | fprint_addr (of, addr, extind, mode, extdisp, TRUE, cflag);\r |
| 803 | return -1;\r |
| 804 | \r |
| 805 | case I_V_RLM: /* reg, long addr */\r |
| 806 | fprintf (of, "%s %-o,", opcode[i], dst);\r |
| 807 | fprint_addr (of, addr, extind, mode, extdisp, TRUE, cflag);\r |
| 808 | return -1;\r |
| 809 | \r |
| 810 | case I_V_FRM: /* flt reg, long addr */\r |
| 811 | fprintf (of, "%s %-o,", opcode[i], dst);\r |
| 812 | fprint_addr (of, addr, extind, src, extdisp, TRUE, cflag);\r |
| 813 | return -1;\r |
| 814 | \r |
| 815 | case I_V_FST: /* flt status */\r |
| 816 | fprintf (of, "%s ", opcode[i]);\r |
| 817 | fprint_addr (of, addr, extind, dst, extdisp, AMASK + 1, cflag);\r |
| 818 | return -1;\r |
| 819 | \r |
| 820 | case I_V_XP: /* XOP */\r |
| 821 | fprintf (of, "%s %-o,%-o,%-o", opcode[i], src, dst, xop);\r |
| 822 | break; /* end case */\r |
| 823 | \r |
| 824 | default:\r |
| 825 | fprintf (of, "??? [%-o]", inst);\r |
| 826 | break;\r |
| 827 | }\r |
| 828 | return SCPE_OK;\r |
| 829 | } /* end if */\r |
| 830 | } /* end for */\r |
| 831 | return SCPE_ARG;\r |
| 832 | }\r |
| 833 | \r |
| 834 | /* Address parse\r |
| 835 | \r |
| 836 | Inputs:\r |
| 837 | *cptr = pointer to input string\r |
| 838 | addr = current PC\r |
| 839 | ext = extended address\r |
| 840 | cflag = true if parsing for CPU\r |
| 841 | val[3] = output array\r |
| 842 | Outputs:\r |
| 843 | optr = pointer to next char in input string\r |
| 844 | NULL if error\r |
| 845 | */\r |
| 846 | \r |
| 847 | #define A_FL 001 /* CPU flag */\r |
| 848 | #define A_NX 002 /* index seen */\r |
| 849 | #define A_PER 004 /* period seen */\r |
| 850 | #define A_NUM 010 /* number seen */\r |
| 851 | #define A_SI 020 /* sign seen */\r |
| 852 | #define A_MI 040 /* - seen */\r |
| 853 | \r |
| 854 | char *get_addr (char *cptr, t_addr addr, t_bool ext, int32 cflag, int32 *val)\r |
| 855 | {\r |
| 856 | int32 d, r, x, pflag;\r |
| 857 | char gbuf[CBUFSIZE];\r |
| 858 | int32 dmax, dsign;\r |
| 859 | \r |
| 860 | if (ext) dmax = AMASK + 1; /* get max disp */\r |
| 861 | else dmax = I_M_DISP + 1;\r |
| 862 | dsign = dmax >> 1; /* get disp sign */\r |
| 863 | val[0] = 0; /* no indirect */\r |
| 864 | val[1] = 0; /* PC rel */\r |
| 865 | val[2] = 0; /* no addr */\r |
| 866 | \r |
| 867 | pflag = cflag & A_FL; /* isolate flag */\r |
| 868 | if (*cptr == '@') { /* indirect? */\r |
| 869 | val[0] = 1;\r |
| 870 | cptr++;\r |
| 871 | } \r |
| 872 | if (*cptr == '.') { /* relative? */\r |
| 873 | pflag = pflag | A_PER;\r |
| 874 | x = 1; /* "index" is PC */\r |
| 875 | cptr++;\r |
| 876 | }\r |
| 877 | if (*cptr == '+') { /* + sign? */\r |
| 878 | pflag = pflag | A_SI;\r |
| 879 | cptr++;\r |
| 880 | }\r |
| 881 | else if (*cptr == '-') { /* - sign? */\r |
| 882 | pflag = pflag | A_MI | A_SI;\r |
| 883 | cptr++;\r |
| 884 | } \r |
| 885 | if (*cptr != 0) { /* number? */\r |
| 886 | cptr = get_glyph (cptr, gbuf, ','); /* get glyph */\r |
| 887 | d = (int32) get_uint (gbuf, 8, AMASK, &r);\r |
| 888 | if (r != SCPE_OK) return NULL;\r |
| 889 | pflag = pflag | A_NUM;\r |
| 890 | }\r |
| 891 | if (*cptr != 0) { /* index? */\r |
| 892 | cptr = get_glyph (cptr, gbuf, 0); /* get glyph */\r |
| 893 | x = (int32) get_uint (gbuf, 8, I_M_DST, &r);\r |
| 894 | if ((r != SCPE_OK) || (x < 2)) return NULL;\r |
| 895 | pflag = pflag | A_NX;\r |
| 896 | }\r |
| 897 | \r |
| 898 | switch (pflag) { /* case on flags */\r |
| 899 | \r |
| 900 | case A_NUM: case A_NUM+A_SI: /* ~CPU, (+)num */\r |
| 901 | if (d < dmax) val[2] = d;\r |
| 902 | else return NULL;\r |
| 903 | break;\r |
| 904 | \r |
| 905 | case A_NUM+A_FL: case A_NUM+A_SI+A_FL: /* CPU, (+)num */\r |
| 906 | if (d < dmax) val[2] = d;\r |
| 907 | else if (((d >= (((int32) addr - dsign) & AMASK)) &&\r |
| 908 | (d < (((int32) addr + dsign) & AMASK))) ||\r |
| 909 | (d >= ((int32) addr + (-dsign & AMASK)))) {\r |
| 910 | val[1] = 1; /* PC rel */\r |
| 911 | val[2] = (d - addr) & (dmax - 1);\r |
| 912 | }\r |
| 913 | else return NULL;\r |
| 914 | break;\r |
| 915 | \r |
| 916 | case A_PER: case A_PER+A_FL: /* . */\r |
| 917 | case A_PER+A_SI+A_NUM: case A_PER+A_SI+A_NUM+A_FL: /* . + num */\r |
| 918 | case A_PER+A_SI+A_MI+A_NUM: /* . - num */\r |
| 919 | case A_PER+A_SI+A_MI+A_NUM+A_FL:\r |
| 920 | case A_NX+A_NUM: case A_NX+A_NUM+A_FL: /* num, ndx */\r |
| 921 | case A_NX+A_SI+A_NUM: case A_NX+A_SI+A_NUM+A_FL: /* +num, ndx */\r |
| 922 | case A_NX+A_SI+A_MI+A_NUM: /* -num, ndx */\r |
| 923 | case A_NX+A_SI+A_MI+A_NUM+A_FL:\r |
| 924 | val[1] = x; /* set mode */\r |
| 925 | if (((pflag & A_MI) == 0) && (d < dsign)) val[2] = d;\r |
| 926 | else if ((pflag & A_MI) && (d <= dsign)) val[2] = (dmax - d);\r |
| 927 | else return NULL;\r |
| 928 | break;\r |
| 929 | \r |
| 930 | default:\r |
| 931 | return NULL;\r |
| 932 | } /* end case */\r |
| 933 | \r |
| 934 | return cptr;\r |
| 935 | }\r |
| 936 | \r |
| 937 | /* Parse two registers \r |
| 938 | \r |
| 939 | Inputs:\r |
| 940 | *cptr = input string\r |
| 941 | term = second terminating character\r |
| 942 | val = output array\r |
| 943 | Outputs:\r |
| 944 | optr = pointer to next char in input string\r |
| 945 | NULL if error\r |
| 946 | */\r |
| 947 | \r |
| 948 | char *get_2reg (char *cptr, char term, int32 *val)\r |
| 949 | {\r |
| 950 | char gbuf[CBUFSIZE];\r |
| 951 | t_stat r;\r |
| 952 | \r |
| 953 | cptr = get_glyph (cptr, gbuf, ','); /* get register */\r |
| 954 | val[0] = (int32) get_uint (gbuf, 8, I_M_SRC, &r);\r |
| 955 | if (r != SCPE_OK) return NULL;\r |
| 956 | cptr = get_glyph (cptr, gbuf, term); /* get register */\r |
| 957 | val[1] = (int32) get_uint (gbuf, 8, I_M_DST, &r);\r |
| 958 | if (r != SCPE_OK) return NULL;\r |
| 959 | return cptr;\r |
| 960 | }\r |
| 961 | \r |
| 962 | /* Symbolic input\r |
| 963 | \r |
| 964 | Inputs:\r |
| 965 | *cptr = pointer to input string\r |
| 966 | addr = current PC\r |
| 967 | *uptr = pointer to unit\r |
| 968 | *val = pointer to output values\r |
| 969 | sw = switches\r |
| 970 | Outputs:\r |
| 971 | status = error status\r |
| 972 | */\r |
| 973 | \r |
| 974 | t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)\r |
| 975 | {\r |
| 976 | int32 cflag, d, i, j, amd[3];\r |
| 977 | t_stat r, rtn;\r |
| 978 | char gbuf[CBUFSIZE];\r |
| 979 | \r |
| 980 | cflag = (uptr == NULL) || (uptr == &cpu_unit);\r |
| 981 | while (isspace (*cptr)) cptr++; /* absorb spaces */\r |
| 982 | if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */\r |
| 983 | if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */\r |
| 984 | val[0] = (t_value) cptr[0];\r |
| 985 | return SCPE_OK;\r |
| 986 | }\r |
| 987 | if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* ASCII string? */\r |
| 988 | if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */\r |
| 989 | val[0] = ((t_value) cptr[0] << 8) + (t_value) cptr[1];\r |
| 990 | return SCPE_OK;\r |
| 991 | }\r |
| 992 | \r |
| 993 | /* Instruction parse */\r |
| 994 | \r |
| 995 | rtn = SCPE_OK; /* assume 1 word */\r |
| 996 | cptr = get_glyph (cptr, gbuf, 0); /* get opcode */\r |
| 997 | for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;\r |
| 998 | if (opcode[i] == NULL) return SCPE_ARG;\r |
| 999 | val[0] = opc_val[i] & 0177777; /* get value */\r |
| 1000 | j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */\r |
| 1001 | \r |
| 1002 | switch (j) { /* case on class */\r |
| 1003 | \r |
| 1004 | case I_V_NPN: /* no operand */\r |
| 1005 | break;\r |
| 1006 | \r |
| 1007 | case I_V_R: /* IOT reg */\r |
| 1008 | cptr = get_glyph (cptr, gbuf, 0); /* get register */\r |
| 1009 | d = (int32) get_uint (gbuf, 8, I_M_DST, &r);\r |
| 1010 | if (r != SCPE_OK) return SCPE_ARG;\r |
| 1011 | val[0] = val[0] | (d << I_V_DST); /* put in place */\r |
| 1012 | break;\r |
| 1013 | \r |
| 1014 | case I_V_RD: /* IOT reg,dev */\r |
| 1015 | cptr = get_glyph (cptr, gbuf, ','); /* get register */\r |
| 1016 | d = (int32) get_uint (gbuf, 8, I_M_DST, &r);\r |
| 1017 | if (r != SCPE_OK) return SCPE_ARG;\r |
| 1018 | val[0] = val[0] | (d << I_V_DST); /* put in place */\r |
| 1019 | case I_V_D: /* IOT dev */\r |
| 1020 | cptr = get_glyph (cptr, gbuf, 0); /* get device */\r |
| 1021 | for (i = 0; (device[i] != NULL) &&\r |
| 1022 | (strcmp (device[i], gbuf) != 0); i++);\r |
| 1023 | if (device[i] != NULL) val[0] = val[0] | dev_val[i];\r |
| 1024 | else {\r |
| 1025 | d = (int32) get_uint (gbuf, 8, I_M_DEV, &r);\r |
| 1026 | if (r != SCPE_OK) return SCPE_ARG;\r |
| 1027 | val[0] = val[0] | (d << I_V_DEV);\r |
| 1028 | }\r |
| 1029 | break;\r |
| 1030 | \r |
| 1031 | case I_V_RM: /* reg, addr */\r |
| 1032 | cptr = get_glyph (cptr, gbuf, ','); /* get register */\r |
| 1033 | d = (int32) get_uint (gbuf, 8, I_M_DST, &r);\r |
| 1034 | if (r != SCPE_OK) return SCPE_ARG;\r |
| 1035 | val[0] = val[0] | (d << I_V_DST); /* put in place */\r |
| 1036 | case I_V_M: /* addr */\r |
| 1037 | cptr = get_addr (cptr, addr, FALSE, cflag, amd);\r |
| 1038 | if (cptr == NULL) return SCPE_ARG;\r |
| 1039 | val[0] = val[0] | (amd[0] << I_V_IND) | (amd[1] << I_V_MODE) | amd[2];\r |
| 1040 | break;\r |
| 1041 | \r |
| 1042 | case I_V_RR: /* operate */\r |
| 1043 | cptr = get_2reg (cptr, ',', amd); /* get 2 reg */\r |
| 1044 | if (cptr == NULL) return SCPE_ARG;\r |
| 1045 | val[0] = val[0] | (amd[0] << I_V_SRC) | (amd[1] << I_V_DST);\r |
| 1046 | if (*cptr != 0) { /* skip? */\r |
| 1047 | cptr = get_glyph (cptr, gbuf, 0); /* get skip */\r |
| 1048 | for (i = 0; (skip[i] != NULL) &&\r |
| 1049 | (strcmp (skip[i], gbuf) != 0); i++) ;\r |
| 1050 | if (skip[i] == NULL) return SCPE_ARG;\r |
| 1051 | val[0] = val[0] | (i + 1);\r |
| 1052 | } /* end if */\r |
| 1053 | break;\r |
| 1054 | \r |
| 1055 | case I_V_BY: /* byte */\r |
| 1056 | cptr = get_2reg (cptr, 0, amd); /* get 2 reg */\r |
| 1057 | if (cptr == NULL) return SCPE_ARG;\r |
| 1058 | val[0] = val[0] | (amd[0] << I_V_PULSE) | (amd[1] << I_V_DST);\r |
| 1059 | break;\r |
| 1060 | \r |
| 1061 | case I_V_2AC: /* reg, reg */\r |
| 1062 | cptr = get_2reg (cptr, 0, amd); /* get 2 reg */\r |
| 1063 | if (cptr == NULL) return SCPE_ARG;\r |
| 1064 | val[0] = val[0] | (amd[0] << I_V_SRC) | (amd[1] << I_V_DST);\r |
| 1065 | break;\r |
| 1066 | \r |
| 1067 | case I_V_RSI: /* reg, short imm */\r |
| 1068 | cptr = get_glyph (cptr, gbuf, ','); /* get immediate */\r |
| 1069 | d = (int32) get_uint (gbuf, 8, I_M_SRC + 1, &r);\r |
| 1070 | if ((d == 0) || (r != SCPE_OK)) return SCPE_ARG;\r |
| 1071 | val[0] = val[0] | ((d - 1) << I_V_SRC); /* put in place */\r |
| 1072 | cptr = get_glyph (cptr, gbuf, 0); /* get register */\r |
| 1073 | d = (int32) get_uint (gbuf, 8, I_M_DST, &r);\r |
| 1074 | if (r != SCPE_OK) return SCPE_ARG;\r |
| 1075 | val[0] = val[0] | (d << I_V_DST); /* put in place */\r |
| 1076 | break;\r |
| 1077 | \r |
| 1078 | case I_V_RLI: /* reg, long imm */\r |
| 1079 | cptr = get_glyph (cptr, gbuf, ','); /* get immediate */\r |
| 1080 | val[1] = (int32) get_uint (gbuf, 8, DMASK, &r);\r |
| 1081 | if (r != SCPE_OK) return SCPE_ARG;\r |
| 1082 | cptr = get_glyph (cptr, gbuf, 0); /* get register */\r |
| 1083 | d = (int32) get_uint (gbuf, 8, I_M_DST, &r);\r |
| 1084 | if (r != SCPE_OK) return SCPE_ARG;\r |
| 1085 | val[0] = val[0] | (d << I_V_DST); /* put in place */\r |
| 1086 | rtn = -1;\r |
| 1087 | break;\r |
| 1088 | \r |
| 1089 | case I_V_LI: /* long imm */\r |
| 1090 | cptr = get_glyph (cptr, gbuf, 0); /* get immediate */\r |
| 1091 | val[1] = (int32) get_uint (gbuf, 8, DMASK, &r);\r |
| 1092 | if (r != SCPE_OK) return SCPE_ARG;\r |
| 1093 | rtn = -1;\r |
| 1094 | break;\r |
| 1095 | \r |
| 1096 | case I_V_RLM: /* reg, long mem */\r |
| 1097 | cptr = get_glyph (cptr, gbuf, ','); /* get register */\r |
| 1098 | d = (int32) get_uint (gbuf, 8, I_M_DST, &r);\r |
| 1099 | if (r != SCPE_OK) return SCPE_ARG;\r |
| 1100 | val[0] = val[0] | (d << I_V_DST); /* put in place */\r |
| 1101 | case I_V_LM: /* long mem */\r |
| 1102 | cptr = get_addr (cptr, addr, TRUE, cflag, amd);\r |
| 1103 | if (cptr == NULL) return SCPE_ARG;\r |
| 1104 | val[0] = val[0] | (amd[1] << I_V_MODE);\r |
| 1105 | val[1] = (amd[0] << A_V_IND) | amd[2];\r |
| 1106 | rtn = -1;\r |
| 1107 | break;\r |
| 1108 | \r |
| 1109 | case I_V_FRM: /* flt reg, long mem */\r |
| 1110 | cptr = get_glyph (cptr, gbuf, ','); /* get register */\r |
| 1111 | d = (int32) get_uint (gbuf, 8, I_M_DST, &r);\r |
| 1112 | if (r != SCPE_OK) return SCPE_ARG;\r |
| 1113 | val[0] = val[0] | (d << I_V_DST); /* put in place */\r |
| 1114 | cptr = get_addr (cptr, addr, TRUE, cflag, amd);\r |
| 1115 | if (cptr == NULL) return SCPE_ARG;\r |
| 1116 | val[0] = val[0] | (amd[1] << I_V_SRC);\r |
| 1117 | val[1] = (amd[0] << A_V_IND) | amd[2];\r |
| 1118 | rtn = -1;\r |
| 1119 | break;\r |
| 1120 | \r |
| 1121 | case I_V_FST: /* flt status */\r |
| 1122 | cptr = get_addr (cptr, addr, TRUE, cflag, amd);\r |
| 1123 | if (cptr == NULL) return SCPE_ARG;\r |
| 1124 | val[0] = val[0] | (amd[1] << I_V_DST);\r |
| 1125 | val[1] = (amd[0] << A_V_IND) | amd[2];\r |
| 1126 | rtn = -1;\r |
| 1127 | break;\r |
| 1128 | \r |
| 1129 | case I_V_XP: /* XOP */\r |
| 1130 | cptr = get_2reg (cptr, ',', amd); /* get 2 reg */\r |
| 1131 | if (cptr == NULL) return SCPE_ARG;\r |
| 1132 | val[0] = val[0] | (amd[0] << I_V_SRC) | (amd[1] << I_V_DST); \r |
| 1133 | cptr = get_glyph (cptr, gbuf, 0); /* get argument */\r |
| 1134 | d = (int32) get_uint (gbuf, 8, I_M_XOP, &r);\r |
| 1135 | if (r != SCPE_OK) return SCPE_ARG;\r |
| 1136 | val[0] = val[0] | (d << I_V_XOP);\r |
| 1137 | break;\r |
| 1138 | } /* end case */\r |
| 1139 | \r |
| 1140 | if (*cptr != 0) return SCPE_ARG; /* any leftovers? */\r |
| 1141 | return rtn;\r |
| 1142 | }\r |