| 1 | /* pdp1_clk.c: PDP-1D clock simulator\r |
| 2 | \r |
| 3 | Copyright (c) 2006, Robert M. Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | bused in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | clk PDP-1D clock\r |
| 27 | \r |
| 28 | Note that the clock is run at 1/8 of real speed (125Hz instead of 1Khz), to\r |
| 29 | provide for eventual implementation of idling.\r |
| 30 | */\r |
| 31 | \r |
| 32 | #include "pdp1_defs.h"\r |
| 33 | \r |
| 34 | #define CLK_HWRE_TPS 1000 /* hardware freq */\r |
| 35 | #define CLK_TPS 125 /* sim freq */\r |
| 36 | #define CLK_CNTS (CLK_HWRE_TPS / CLK_TPS) /* counts per tick */\r |
| 37 | #define CLK_C1MIN (1000 * 60) /* counts per min */\r |
| 38 | #define CLK_C32MS 32 /* counts per 32ms */\r |
| 39 | \r |
| 40 | int32 clk32ms_sbs = 0; /* 32ms SBS level */\r |
| 41 | int32 clk1min_sbs = 0; /* 1min SBS level */\r |
| 42 | int32 clk_cntr = 0;\r |
| 43 | int32 tmxr_poll = 5000;\r |
| 44 | \r |
| 45 | extern int32 stop_inst;\r |
| 46 | \r |
| 47 | t_stat clk_svc (UNIT *uptr);\r |
| 48 | t_stat clk_reset (DEVICE *dptr);\r |
| 49 | \r |
| 50 | /* CLK data structures\r |
| 51 | \r |
| 52 | clk_dev CLK device descriptor\r |
| 53 | clk_unit CLK unit\r |
| 54 | clk_reg CLK register list\r |
| 55 | */\r |
| 56 | \r |
| 57 | UNIT clk_unit = {\r |
| 58 | UDATA (&clk_svc, 0, 0), 5000\r |
| 59 | };\r |
| 60 | \r |
| 61 | REG clk_reg[] = {\r |
| 62 | { ORDATA (CNTR, clk_cntr, 16) },\r |
| 63 | { DRDATA (SBS32LVL, clk32ms_sbs, 4), REG_HRO },\r |
| 64 | { DRDATA (SBS1MLVL, clk1min_sbs, 4), REG_HRO },\r |
| 65 | { NULL }\r |
| 66 | };\r |
| 67 | \r |
| 68 | MTAB clk_mod[] = {\r |
| 69 | { MTAB_XTD|MTAB_VDV, 0, "SBS32MSLVL", "SBS32MSLVL",\r |
| 70 | &dev_set_sbs, &dev_show_sbs, (void *) &clk32ms_sbs },\r |
| 71 | { MTAB_XTD|MTAB_VDV, 0, "SBS1MINLVL", "SBS1MINLVL",\r |
| 72 | &dev_set_sbs, &dev_show_sbs, (void *) &clk1min_sbs },\r |
| 73 | { 0 }\r |
| 74 | };\r |
| 75 | \r |
| 76 | DEVICE clk_dev = {\r |
| 77 | "CLK", &clk_unit, clk_reg, clk_mod,\r |
| 78 | 1, 10, 31, 1, 8, 8,\r |
| 79 | NULL, NULL, &clk_reset,\r |
| 80 | NULL, NULL, NULL,\r |
| 81 | NULL, DEV_DISABLE | DEV_DIS\r |
| 82 | };\r |
| 83 | \r |
| 84 | /* Clock IOT routine */\r |
| 85 | \r |
| 86 | int32 clk (int32 inst, int32 dev, int32 dat)\r |
| 87 | {\r |
| 88 | int32 used, incr;\r |
| 89 | \r |
| 90 | if (clk_dev.flags & DEV_DIS) /* disabled? */\r |
| 91 | return (stop_inst << IOT_V_REASON) | dat; /* illegal inst */\r |
| 92 | used = tmxr_poll - (sim_is_active (&clk_unit) - 1);\r |
| 93 | incr = (used * CLK_CNTS) / tmxr_poll;\r |
| 94 | return clk_cntr + incr;\r |
| 95 | }\r |
| 96 | \r |
| 97 | /* Unit service, generate appropriate interrupts */\r |
| 98 | \r |
| 99 | t_stat clk_svc (UNIT *uptr)\r |
| 100 | {\r |
| 101 | if (clk_dev.flags & DEV_DIS) return SCPE_OK; /* disabled? */\r |
| 102 | tmxr_poll = sim_rtcn_calb (CLK_TPS, TMR_CLK); /* calibrate clock */\r |
| 103 | sim_activate (&clk_unit, tmxr_poll); /* reactivate unit */\r |
| 104 | clk_cntr = clk_cntr + CLK_CNTS; /* incr counter */\r |
| 105 | if ((clk_cntr % CLK_C32MS) == 0) /* 32ms interval? */\r |
| 106 | dev_req_int (clk32ms_sbs); /* req intr */\r |
| 107 | if (clk_cntr >= CLK_C1MIN) { /* 1min interval? */\r |
| 108 | dev_req_int (clk1min_sbs); /* req intr */\r |
| 109 | clk_cntr = 0; /* reset counter */\r |
| 110 | }\r |
| 111 | return SCPE_OK;\r |
| 112 | }\r |
| 113 | \r |
| 114 | /* Reset routine */\r |
| 115 | \r |
| 116 | t_stat clk_reset (DEVICE *dptr)\r |
| 117 | {\r |
| 118 | if (clk_dev.flags & DEV_DIS) sim_cancel (&clk_unit); /* disabled? */\r |
| 119 | else {\r |
| 120 | tmxr_poll = sim_rtcn_init (clk_unit.wait, TMR_CLK);\r |
| 121 | sim_activate_abs (&clk_unit, tmxr_poll); /* activate unit */\r |
| 122 | }\r |
| 123 | clk_cntr = 0; /* clear counter */\r |
| 124 | return SCPE_OK;\r |
| 125 | }\r |