| 1 | /* pdp10_defs.h: PDP-10 simulator definitions\r |
| 2 | \r |
| 3 | Copyright (c) 1993-2007, Robert M Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | 01-Feb-07 RMS Added CD support\r |
| 27 | 29-Oct-06 RMS Added clock coscheduling function\r |
| 28 | 29-Dec-03 RMS Added Q18 definition for PDP11 compatibility\r |
| 29 | 19-May-03 RMS Revised for new conditional compilation scheme\r |
| 30 | 09-Jan-03 RMS Added DEUNA/DELUA support\r |
| 31 | 29-Sep-02 RMS Added variable vector, RX211 support\r |
| 32 | 22-Apr-02 RMS Removed magtape record length error\r |
| 33 | 20-Jan-02 RMS Added multiboard DZ11 support\r |
| 34 | 23-Oct-01 RMS New IO page address constants\r |
| 35 | 19-Oct-01 RMS Added DZ11 definitions\r |
| 36 | 07-Sep-01 RMS Revised for PDP-11 multi-level interrupts\r |
| 37 | 31-Aug-01 RMS Changed int64 to t_int64 for Windoze\r |
| 38 | 29-Aug-01 RMS Corrected models and dates (found by Lars Brinkhoff)\r |
| 39 | 01-Jun-01 RMS Updated DZ11 vector definitions\r |
| 40 | 19-May-01 RMS Added workaround for TOPS-20 V4.1 boot bug\r |
| 41 | */\r |
| 42 | \r |
| 43 | #ifndef _PDP10_DEFS_H_\r |
| 44 | #define _PDP10_DEFS_H_ 0\r |
| 45 | \r |
| 46 | #ifndef VM_PDP10\r |
| 47 | #define VM_PDP10 0\r |
| 48 | #endif\r |
| 49 | \r |
| 50 | #include "sim_defs.h" /* simulator defns */\r |
| 51 | \r |
| 52 | /* Digital Equipment Corporation's 36b family had six implementations:\r |
| 53 | \r |
| 54 | name mips comments\r |
| 55 | \r |
| 56 | PDP-6 0.25 Original 36b implementation, 1964\r |
| 57 | KA10 0.38 First PDP-10, flip chips, 1967\r |
| 58 | KI10 0.72 First paging system, flip chip + MSI, 1972\r |
| 59 | KL10 1.8 First ECL system, ECL 10K, 1975\r |
| 60 | KL10B 1.8 Expanded addressing, ECL 10K, 1978\r |
| 61 | KS10 0.3 Last 36b system, 2901 based, 1979\r |
| 62 | \r |
| 63 | In addition, it ran four major (incompatible) operating systems:\r |
| 64 | \r |
| 65 | name company comments\r |
| 66 | \r |
| 67 | TOPS-10 DEC Original timesharing system\r |
| 68 | ITS MIT "Incompatible Timesharing System"\r |
| 69 | TENEX BBN ARPA-sponsored, became\r |
| 70 | TOPS-20 DEC Commercial version of TENEX\r |
| 71 | \r |
| 72 | All of the implementations differ from one another, in instruction set,\r |
| 73 | I/O structure, and memory management. Further, each of the operating\r |
| 74 | systems customized the microcode of the paging systems (KI10, KL10, KS10)\r |
| 75 | for additional instructions and specialized memory management. As a\r |
| 76 | result, there is no "reference implementation" for the 36b family that\r |
| 77 | will run all programs and all operating systems. The conditionalization\r |
| 78 | and generality needed to support the full matrix of models and operating\r |
| 79 | systems, and to support 36b hardware on 32b data types, is beyond the\r |
| 80 | scope of this project.\r |
| 81 | \r |
| 82 | Instead, this simulator emulates one model -- the KS10. It has the best\r |
| 83 | documentation and allows reuse of some of the Unibus peripheral emulators\r |
| 84 | written for the PDP-11 simulator. Further, the simulator requires that\r |
| 85 | the underlying compiler support 64b integer data types, allowing 36b data\r |
| 86 | to be maintained in a single data item. Lastly, the simulator implements\r |
| 87 | the maximum memory size, so that NXM's never happen.\r |
| 88 | */\r |
| 89 | \r |
| 90 | /* Data types */\r |
| 91 | \r |
| 92 | typedef int32 a10; /* PDP-10 addr (30b) */\r |
| 93 | typedef t_int64 d10; /* PDP-10 data (36b) */\r |
| 94 | \r |
| 95 | /* Abort codes, used to sort out longjmp's back to the main loop\r |
| 96 | Codes > 0 are simulator stop codes\r |
| 97 | Codes < 0 are internal aborts\r |
| 98 | Code = 0 stops execution for an interrupt check\r |
| 99 | */\r |
| 100 | \r |
| 101 | #define STOP_HALT 1 /* halted */\r |
| 102 | #define STOP_IBKPT 2 /* breakpoint */\r |
| 103 | #define STOP_ILLEG 3 /* illegal instr */\r |
| 104 | #define STOP_ILLINT 4 /* illegal intr inst */\r |
| 105 | #define STOP_PAGINT 5 /* page fail in intr */\r |
| 106 | #define STOP_ZERINT 6 /* zero vec in intr */\r |
| 107 | #define STOP_NXMPHY 7 /* nxm on phys ref */\r |
| 108 | #define STOP_IND 8 /* indirection loop */\r |
| 109 | #define STOP_XCT 9 /* XCT loop */\r |
| 110 | #define STOP_ILLIOC 10 /* invalid UBA num */\r |
| 111 | #define STOP_ASTOP 11 /* address stop */\r |
| 112 | #define STOP_UNKNOWN 12 /* unknown stop */\r |
| 113 | #define PAGE_FAIL -1 /* page fail */\r |
| 114 | #define INTERRUPT -2 /* interrupt */\r |
| 115 | #define ABORT(x) longjmp (save_env, (x)) /* abort */\r |
| 116 | #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */\r |
| 117 | \r |
| 118 | /* Return codes from eXTEND */\r |
| 119 | \r |
| 120 | #define XT_MUUO 0 /* invalid operation */\r |
| 121 | #define XT_SKIP 1 /* skip return */\r |
| 122 | #define XT_NOSK 2 /* no skip return */\r |
| 123 | \r |
| 124 | /* Operating system flags, kept in cpu_unit.flags */\r |
| 125 | \r |
| 126 | #define UNIT_V_ITS (UNIT_V_UF) /* ITS */\r |
| 127 | #define UNIT_V_T20 (UNIT_V_UF + 1) /* TOPS-20 */\r |
| 128 | #define UNIT_V_KLAD (UNIT_V_UF + 2) /* diagnostics */\r |
| 129 | #define UNIT_ITS (1 << UNIT_V_ITS)\r |
| 130 | #define UNIT_T20 (1 << UNIT_V_T20)\r |
| 131 | #define UNIT_KLAD (1 << UNIT_V_KLAD)\r |
| 132 | #define Q_T10 ((cpu_unit.flags & (UNIT_ITS|UNIT_T20|UNIT_KLAD)) == 0)\r |
| 133 | #define Q_ITS (cpu_unit.flags & UNIT_ITS)\r |
| 134 | #define Q_T20 (cpu_unit.flags & UNIT_T20)\r |
| 135 | #define Q_KLAD (cpu_unit.flags & UNIT_KLAD)\r |
| 136 | #define Q_IDLE (sim_idle_enab)\r |
| 137 | \r |
| 138 | /* Architectural constants */\r |
| 139 | \r |
| 140 | #define PASIZE 20 /* phys addr width */\r |
| 141 | #define MAXMEMSIZE (1 << PASIZE) /* maximum memory */\r |
| 142 | #define PAMASK ((1 << PASIZE) - 1)\r |
| 143 | #define MEMSIZE MAXMEMSIZE /* fixed, KISS */\r |
| 144 | #define MEM_ADDR_NXM(x) ((x) >= MEMSIZE)\r |
| 145 | #define VASIZE 18 /* virtual addr width */\r |
| 146 | #define AMASK ((1 << VASIZE) - 1) /* virtual addr mask */\r |
| 147 | #define LMASK 0777777000000 /* left mask */\r |
| 148 | #define LSIGN 0400000000000 /* left sign */\r |
| 149 | #define RMASK 0000000777777 /* right mask */\r |
| 150 | #define RSIGN 0000000400000 /* right sign */\r |
| 151 | #define DMASK 0777777777777 /* data mask */\r |
| 152 | #define SIGN 0400000000000 /* sign */\r |
| 153 | #define MMASK 0377777777777 /* magnitude mask */\r |
| 154 | #define ONES 0777777777777\r |
| 155 | #define MAXPOS 0377777777777\r |
| 156 | #define MAXNEG 0400000000000\r |
| 157 | \r |
| 158 | /* Instruction format */\r |
| 159 | \r |
| 160 | #define INST_V_OP 27 /* opcode */\r |
| 161 | #define INST_M_OP 0777\r |
| 162 | #define INST_V_DEV 26\r |
| 163 | #define INST_M_DEV 0177 /* device */\r |
| 164 | #define INST_V_AC 23 /* AC */\r |
| 165 | #define INST_M_AC 017\r |
| 166 | #define INST_V_IND 22 /* indirect */\r |
| 167 | #define INST_IND (1 << INST_V_IND)\r |
| 168 | #define INST_V_XR 18 /* index */\r |
| 169 | #define INST_M_XR 017\r |
| 170 | #define OP_JRST 0254 /* JRST */\r |
| 171 | #define AC_XPCW 07 /* XPCW */\r |
| 172 | #define OP_JSR 0264 /* JSR */\r |
| 173 | #define GET_OP(x) ((int32) (((x) >> INST_V_OP) & INST_M_OP))\r |
| 174 | #define GET_DEV(x) ((int32) (((x) >> INST_V_DEV) & INST_M_DEV))\r |
| 175 | #define GET_AC(x) ((int32) (((x) >> INST_V_AC) & INST_M_AC))\r |
| 176 | #define TST_IND(x) ((x) & INST_IND)\r |
| 177 | #define GET_XR(x) ((int32) (((x) >> INST_V_XR) & INST_M_XR))\r |
| 178 | #define GET_ADDR(x) ((a10) ((x) & AMASK))\r |
| 179 | \r |
| 180 | /* Byte pointer format */\r |
| 181 | \r |
| 182 | #define BP_V_P 30 /* position */\r |
| 183 | #define BP_M_P 077\r |
| 184 | #define BP_P 0770000000000\r |
| 185 | #define BP_V_S 24 /* size */\r |
| 186 | #define BP_M_S 077\r |
| 187 | #define BP_S 0007700000000\r |
| 188 | #define GET_P(x) ((int32) (((x) >> BP_V_P) & BP_M_P))\r |
| 189 | #define GET_S(x) ((int32) (((x) >> BP_V_S) & BP_M_S))\r |
| 190 | #define PUT_P(b,x) (((b) & ~BP_P) | ((((t_int64) (x)) & BP_M_P) << BP_V_P))\r |
| 191 | \r |
| 192 | /* Flags (stored in their own halfword) */\r |
| 193 | \r |
| 194 | #define F_V_AOV 17 /* arithmetic ovflo */\r |
| 195 | #define F_V_C0 16 /* carry 0 */\r |
| 196 | #define F_V_C1 15 /* carry 1 */\r |
| 197 | #define F_V_FOV 14 /* floating ovflo */\r |
| 198 | #define F_V_FPD 13 /* first part done */\r |
| 199 | #define F_V_USR 12 /* user mode */\r |
| 200 | #define F_V_UIO 11 /* user I/O mode */\r |
| 201 | #define F_V_PUB 10 /* public mode */\r |
| 202 | #define F_V_AFI 9 /* addr fail inhibit */\r |
| 203 | #define F_V_T2 8 /* trap 2 */\r |
| 204 | #define F_V_T1 7 /* trap 1 */\r |
| 205 | #define F_V_FXU 6 /* floating exp unflo */\r |
| 206 | #define F_V_DCK 5 /* divide check */\r |
| 207 | #define F_AOV (1 << F_V_AOV)\r |
| 208 | #define F_C0 (1 << F_V_C0)\r |
| 209 | #define F_C1 (1 << F_V_C1)\r |
| 210 | #define F_FOV (1 << F_V_FOV)\r |
| 211 | #define F_FPD (1 << F_V_FPD)\r |
| 212 | #define F_USR (1 << F_V_USR)\r |
| 213 | #define F_UIO (1 << F_V_UIO)\r |
| 214 | #define F_PUB (1 << F_V_PUB)\r |
| 215 | #define F_AFI (1 << F_V_AFI)\r |
| 216 | #define F_T2 (1 << F_V_T2)\r |
| 217 | #define F_T1 (1 << F_V_T1)\r |
| 218 | #define F_TR (F_T1 | F_T2)\r |
| 219 | #define F_FXU (1 << F_V_FXU)\r |
| 220 | #define F_DCK (1 << F_V_DCK)\r |
| 221 | #define F_1PR (F_AFI) /* ITS: 1-proceed */\r |
| 222 | #define F_MASK 0777740 /* all flags */\r |
| 223 | #define SETF(x) flags = flags | (x)\r |
| 224 | #define CLRF(x) flags = flags & ~(x)\r |
| 225 | #define TSTF(x) (flags & (x))\r |
| 226 | #define GET_TRAPS(x) (((x) & (F_T2 | F_T1)) >> F_V_T1)\r |
| 227 | \r |
| 228 | /* Priority interrupt system */\r |
| 229 | \r |
| 230 | #define PI_CPRQ 020000 /* drop prog req */\r |
| 231 | #define PI_INIT 010000 /* clear pi system */\r |
| 232 | #define PI_SPRQ 004000 /* set prog req */\r |
| 233 | #define PI_SENB 002000 /* set enables */\r |
| 234 | #define PI_CENB 001000 /* clear enables */\r |
| 235 | #define PI_CON 000400 /* turn off pi system */\r |
| 236 | #define PI_SON 000200 /* turn on pi system */\r |
| 237 | #define PI_M_LVL 000177 /* level mask */\r |
| 238 | #define PI_V_PRQ 18 /* in CONI */\r |
| 239 | #define PI_V_ACT 8\r |
| 240 | #define PI_V_ON 7\r |
| 241 | #define PI_V_ENB 0\r |
| 242 | \r |
| 243 | /* Arithmetic processor flags */\r |
| 244 | \r |
| 245 | #define APR_SENB 0100000 /* set enable */\r |
| 246 | #define APR_CENB 0040000 /* clear enable */\r |
| 247 | #define APR_CFLG 0020000 /* clear flag */\r |
| 248 | #define APR_SFLG 0010000 /* set flag */\r |
| 249 | #define APR_IRQ 0000010 /* int request */\r |
| 250 | #define APR_M_LVL 0000007 /* pi level */\r |
| 251 | #define APR_V_FLG 4 /* system flags */\r |
| 252 | #define APR_M_FLG 0377\r |
| 253 | #define APRF_ITC (002000 >> APR_V_FLG) /* int console flag */\r |
| 254 | #define APRF_NXM (000400 >> APR_V_FLG) /* nxm flag */\r |
| 255 | #define APRF_TIM (000040 >> APR_V_FLG) /* timer request */\r |
| 256 | #define APRF_CON (000020 >> APR_V_FLG) /* console int */\r |
| 257 | #define APR_GETF(x) (((x) >> APR_V_FLG) & APR_M_FLG)\r |
| 258 | \r |
| 259 | /* Virtual address, DEC paging */\r |
| 260 | \r |
| 261 | #define PAG_V_OFF 0 /* offset - must be 0 */\r |
| 262 | #define PAG_N_OFF 9 /* page offset width */\r |
| 263 | #define PAG_SIZE 01000 /* page offset size */\r |
| 264 | #define PAG_M_OFF 0777 /* mask for offset */\r |
| 265 | #define PAG_V_PN PAG_N_OFF /* page number */\r |
| 266 | #define PAG_N_PPN (PASIZE - PAG_N_OFF) /* phys pageno width */\r |
| 267 | #define PAG_M_PPN 03777 /* phys pageno mask */\r |
| 268 | #define PAG_PPN 03777000\r |
| 269 | #define PAG_N_VPN (VASIZE - PAG_N_OFF) /* virt pageno width */\r |
| 270 | #define PAG_M_VPN 0777 /* virt pageno mask */\r |
| 271 | #define PAG_VPN 0777000\r |
| 272 | #define PAG_GETOFF(x) ((x) & PAG_M_OFF)\r |
| 273 | #define PAG_GETVPN(x) (((x) >> PAG_V_PN) & PAG_M_VPN)\r |
| 274 | #define PAG_XPTEPA(p,x) (((p) + PAG_GETOFF (x)) & PAMASK)\r |
| 275 | #define PAG_PTEPA(p,x) (((((int32) (p)) & PTE_PPMASK) << PAG_V_PN) + PAG_GETOFF (x))\r |
| 276 | \r |
| 277 | /* Page table entry, TOPS-10 paging */\r |
| 278 | \r |
| 279 | #define PTE_T10_A 0400000 /* T10: access */\r |
| 280 | #define PTE_T10_P 0200000 /* T10: public */\r |
| 281 | #define PTE_T10_W 0100000 /* T10: writeable */\r |
| 282 | #define PTE_T10_S 0040000 /* T10: software */\r |
| 283 | #define PTE_T10_C 0020000 /* T10: cacheable */\r |
| 284 | #define PTE_PPMASK PAG_M_PPN\r |
| 285 | \r |
| 286 | /* Page table entry, TOPS-20 paging */\r |
| 287 | \r |
| 288 | #define PTE_T20_V_TYP 33 /* T20: pointer type */\r |
| 289 | #define PTE_T20_M_TYP 07\r |
| 290 | #define T20_NOA 0 /* no access */\r |
| 291 | #define T20_IMM 1 /* immediate */\r |
| 292 | #define T20_SHR 2 /* shared */\r |
| 293 | #define T20_IND 3 /* indirect */\r |
| 294 | #define PTE_T20_W 0020000000000 /* T20: writeable */\r |
| 295 | #define PTE_T20_C 0004000000000 /* T20: cacheable */\r |
| 296 | #define PTE_T20_STM 0000077000000 /* T20: storage medium */\r |
| 297 | #define PTE_T20_V_PMI 18 /* page map index */\r |
| 298 | #define PTE_T20_M_PMI 0777\r |
| 299 | #define T20_GETTYP(x) ((int32) (((x) >> PTE_T20_V_TYP) & PTE_T20_M_TYP))\r |
| 300 | #define T20_GETPMI(x) ((int32) (((x) >> PTE_T20_V_PMI) & PTE_T20_M_PMI))\r |
| 301 | \r |
| 302 | /* CST entry, TOPS-20 paging */\r |
| 303 | \r |
| 304 | #define CST_AGE 0770000000000 /* age field */\r |
| 305 | #define CST_M 0000000000001 /* modified */\r |
| 306 | \r |
| 307 | /* Page fail word, DEC paging */\r |
| 308 | \r |
| 309 | #define PF_USER 0400000000000 /* user mode */\r |
| 310 | #define PF_HARD 0200000000000 /* nx I/O reg */\r |
| 311 | #define PF_NXM 0370000000000 /* nx memory */\r |
| 312 | #define PF_T10_A 0100000000000 /* T10: pte A bit */\r |
| 313 | #define PF_T10_W 0040000000000 /* T10: pte W bit */\r |
| 314 | #define PF_T10_S 0020000000000 /* T10: pte S bit */\r |
| 315 | #define PF_T20_DN 0100000000000 /* T20: eval done */\r |
| 316 | #define PF_T20_M 0040000000000 /* T20: modified */\r |
| 317 | #define PF_T20_W 0020000000000 /* T20: writeable */\r |
| 318 | #define PF_WRITE 0010000000000 /* write reference */\r |
| 319 | #define PF_PUB 0004000000000 /* pte public bit */\r |
| 320 | #define PF_C 0002000000000 /* pte C bit */\r |
| 321 | #define PF_VIRT 0001000000000 /* pfl: virt ref */\r |
| 322 | #define PF_NXMP 0001000000000 /* nxm: phys ref */\r |
| 323 | #define PF_IO 0000200000000 /* I/O reference */\r |
| 324 | #define PF_BYTE 0000020000000 /* I/O byte ref */\r |
| 325 | \r |
| 326 | /* Virtual address, ITS paging */\r |
| 327 | \r |
| 328 | #define ITS_V_OFF 0 /* offset - must be 0 */\r |
| 329 | #define ITS_N_OFF 10 /* page offset width */\r |
| 330 | #define ITS_SIZE 02000 /* page offset size */\r |
| 331 | #define ITS_M_OFF 01777 /* mask for offset */\r |
| 332 | #define ITS_V_PN ITS_N_OFF /* page number */\r |
| 333 | #define ITS_N_PPN (PASIZE- ITS_N_OFF) /* phys pageno width */\r |
| 334 | #define ITS_M_PPN 01777 /* phys pageno mask */\r |
| 335 | #define ITS_PPN 03776000\r |
| 336 | #define ITS_N_VPN (VASIZE - ITS_N_OFF) /* virt pageno width */\r |
| 337 | #define ITS_M_VPN 0377 /* virt pageno mask */\r |
| 338 | #define ITS_VPN 0776000\r |
| 339 | #define ITS_GETVPN(x) (((x) >> ITS_V_PN) & ITS_M_VPN)\r |
| 340 | \r |
| 341 | /* Page table entry, ITS paging */\r |
| 342 | \r |
| 343 | #define PTE_ITS_V_ACC 16 /* access field */\r |
| 344 | #define PTE_ITS_M_ACC 03\r |
| 345 | #define ITS_ACC_NO 0 /* no access */\r |
| 346 | #define ITS_ACC_RO 1 /* read only */\r |
| 347 | #define ITS_ACC_RWF 2 /* read-write first */\r |
| 348 | #define ITS_ACC_RW 3 /* read write */\r |
| 349 | #define PTE_ITS_AGE 0020000 /* age */\r |
| 350 | #define PTE_ITS_C 0010000 /* cacheable */\r |
| 351 | #define PTE_ITS_PPMASK ITS_M_PPN\r |
| 352 | #define ITS_GETACC(x) (((x) >> PTE_ITS_V_ACC) & PTE_ITS_M_ACC)\r |
| 353 | \r |
| 354 | /* Page fail word, ITS paging */\r |
| 355 | \r |
| 356 | #define PF_ITS_WRITE 0010000000000 /* write reference */\r |
| 357 | #define PF_ITS_V_ACC 28 /* access from PTE */\r |
| 358 | \r |
| 359 | /* Page table fill operations */\r |
| 360 | \r |
| 361 | #define PTF_RD 0 /* read check */\r |
| 362 | #define PTF_WR 1 /* write check */\r |
| 363 | #define PTF_MAP 2 /* map instruction */\r |
| 364 | #define PTF_CON 4 /* console access */\r |
| 365 | \r |
| 366 | /* User base register */\r |
| 367 | \r |
| 368 | #define UBR_SETACB 0400000000000 /* set AC blocks */\r |
| 369 | #define UBR_SETUBR 0100000000000 /* set UBR */\r |
| 370 | #define UBR_V_CURAC 27 /* current AC block */\r |
| 371 | #define UBR_V_PRVAC 24 /* previous AC block */\r |
| 372 | #define UBR_M_AC 07\r |
| 373 | #define UBR_ACBMASK 0007700000000\r |
| 374 | #define UBR_V_UBR 0 /* user base register */\r |
| 375 | #define UBR_N_UBR 11\r |
| 376 | #define UBR_M_UBR 03777\r |
| 377 | #define UBR_UBRMASK 0000000003777\r |
| 378 | #define UBR_GETCURAC(x) ((int32) (((x) >> UBR_V_CURAC) & UBR_M_AC))\r |
| 379 | #define UBR_GETPRVAC(x) ((int32) (((x) >> UBR_V_PRVAC) & UBR_M_AC))\r |
| 380 | #define UBR_GETUBR(x) ((int32) (((x) >> UBR_V_UBR) & PAG_M_PPN))\r |
| 381 | #define UBRWORD (ubr | UBR_SETACB | UBR_SETUBR)\r |
| 382 | \r |
| 383 | /* Executive base register */\r |
| 384 | \r |
| 385 | #define EBR_V_T20P 14 /* TOPS20 paging */\r |
| 386 | #define EBR_T20P (1u << EBR_V_T20P)\r |
| 387 | #define EBR_V_PGON 13 /* enable paging */\r |
| 388 | #define EBR_PGON (1u << EBR_V_PGON)\r |
| 389 | #define EBR_V_EBR 0 /* exec base register */\r |
| 390 | #define EBR_N_EBR 11\r |
| 391 | #define EBR_M_EBR 03777\r |
| 392 | #define EBR_MASK (EBR_T20P | EBR_PGON | (EBR_M_EBR << EBR_V_EBR))\r |
| 393 | #define EBR_GETEBR(x) ((int32) (((x) >> EBR_V_EBR) & PAG_M_PPN))\r |
| 394 | #define PAGING (ebr & EBR_PGON)\r |
| 395 | #define T20PAG (ebr & EBR_T20P)\r |
| 396 | \r |
| 397 | /* AC and mapping contexts\r |
| 398 | \r |
| 399 | There are only two real contexts for selecting the AC block and\r |
| 400 | the memory map: current and previous. However, PXCT allows the\r |
| 401 | choice of current versus previous to be made selectively for\r |
| 402 | various parts of an instruction. The PXCT flags are kept in a\r |
| 403 | dynamic CPU variable.\r |
| 404 | */\r |
| 405 | \r |
| 406 | #define EA_PXCT 010 /* eff addr calc */\r |
| 407 | #define OPND_PXCT 004 /* operand, bdst */\r |
| 408 | #define EABP_PXCT 002 /* bp eff addr calc */\r |
| 409 | #define BSTK_PXCT 001 /* stk, bp op, bsrc */\r |
| 410 | #define XSRC_PXCT 002 /* extend source */\r |
| 411 | #define XDST_PXCT 001 /* extend destination */\r |
| 412 | #define MM_CUR 000 /* current context */\r |
| 413 | #define MM_EA (pflgs & EA_PXCT)\r |
| 414 | #define MM_OPND (pflgs & OPND_PXCT)\r |
| 415 | #define MM_EABP (pflgs & EABP_PXCT)\r |
| 416 | #define MM_BSTK (pflgs & BSTK_PXCT)\r |
| 417 | \r |
| 418 | /* Accumulator access. The AC blocks are kept in array acs[AC_NBLK * AC_NUM].\r |
| 419 | Two pointers are provided to the bases of the current and previous blocks.\r |
| 420 | Macro AC selects the current AC block; macro XR selects current or previous,\r |
| 421 | depending on whether the selected bit in the "pxct in progress" flag is set.\r |
| 422 | */\r |
| 423 | \r |
| 424 | #define AC_NUM 16 /* # AC's/block */\r |
| 425 | #define AC_NBLK 8 /* # AC blocks */\r |
| 426 | #define AC(r) (ac_cur[r]) /* AC select current */\r |
| 427 | #define XR(r,prv) ((prv)? ac_prv[r]: ac_cur[r]) /* AC select context */\r |
| 428 | #define ADDAC(x,i) (((x) + (i)) & INST_M_AC)\r |
| 429 | #define P1 ADDAC (ac, 1)\r |
| 430 | \r |
| 431 | /* User process table entries */\r |
| 432 | \r |
| 433 | #define UPT_T10_UMAP 0000 /* T10: user map */\r |
| 434 | #define UPT_T10_X340 0400 /* T10: exec 340-377 */\r |
| 435 | #define UPT_TRBASE 0420 /* trap base */\r |
| 436 | #define UPT_MUUO 0424 /* MUUO block */\r |
| 437 | #define UPT_MUPC 0425 /* caller's PC */\r |
| 438 | #define UPT_T10_CTX 0426 /* T10: context */\r |
| 439 | #define UPT_T20_UEA 0426 /* T20: address */\r |
| 440 | #define UPT_T20_CTX 0427 /* T20: context */\r |
| 441 | #define UPT_ENPC 0430 /* MUUO new PC, exec */\r |
| 442 | #define UPT_1PO 0432 /* ITS 1-proc: old PC */\r |
| 443 | #define UPT_1PN 0433 /* ITS 1-proc: new PC */\r |
| 444 | #define UPT_UNPC 0434 /* MUUO new PC, user */\r |
| 445 | #define UPT_NPCT 1 /* PC offset if trap */\r |
| 446 | #define UPT_T10_PAG 0500 /* T10: page fail blk */\r |
| 447 | #define UPT_T20_PFL 0500 /* T20: page fail wd */\r |
| 448 | #define UPT_T20_OFL 0501 /* T20: flags */\r |
| 449 | #define UPT_T20_OPC 0502 /* T20: old PC */\r |
| 450 | #define UPT_T20_NPC 0503 /* T20: new PC */\r |
| 451 | #define UPT_T20_SCTN 0540 /* T20: section 0 ptr */\r |
| 452 | \r |
| 453 | /* Exec process table entries */\r |
| 454 | \r |
| 455 | #define EPT_PIIT 0040 /* PI interrupt table */\r |
| 456 | #define EPT_UBIT 0100 /* Unibus intr table */\r |
| 457 | #define EPT_T10_X400 0200 /* T10: exec 400-777 */\r |
| 458 | #define EPT_TRBASE 0420 /* trap base */\r |
| 459 | #define EPT_ITS_PAG 0440 /* ITS: page fail blk */\r |
| 460 | #define EPT_T20_SCTN 0540 /* T20: section 0 ptr */\r |
| 461 | #define EPT_T10_X000 0600 /* T10: exec 0 - 337 */\r |
| 462 | \r |
| 463 | /* Microcode constants */\r |
| 464 | \r |
| 465 | #define UC_INHCST 0400000000000 /* inhibit CST update */\r |
| 466 | #define UC_UBABLT 0040000000000 /* BLTBU and BLTUB */\r |
| 467 | #define UC_KIPAGE 0020000000000 /* "KI" paging */\r |
| 468 | #define UC_KLPAGE 0010000000000 /* "KL" paging */\r |
| 469 | #define UC_VERDEC (0130 << 18) /* ucode version */\r |
| 470 | #define UC_VERITS (262u << 18)\r |
| 471 | #define UC_SERDEC 4097 /* serial number */\r |
| 472 | #define UC_SERITS 1729\r |
| 473 | #define UC_AIDDEC (UC_INHCST | UC_UBABLT | UC_KIPAGE | UC_KLPAGE | \\r |
| 474 | UC_VERDEC | UC_SERDEC)\r |
| 475 | #define UC_AIDITS (UC_KIPAGE | UC_VERITS | UC_SERITS)\r |
| 476 | #define UC_HSBDEC 0376000 /* DEC initial HSB */\r |
| 477 | #define UC_HSBITS 0000500 /* ITS initial HSB */\r |
| 478 | \r |
| 479 | /* Front end communications region */\r |
| 480 | \r |
| 481 | #define FE_SWITCH 030 /* halt switch */\r |
| 482 | #define FE_KEEPA 031 /* keep alive */\r |
| 483 | #define FE_CTYIN 032 /* console in */\r |
| 484 | #define FE_CTYOUT 033 /* console out */\r |
| 485 | #define FE_KLININ 034 /* KLINIK in */\r |
| 486 | #define FE_KLINOUT 035 /* KLINIK out */\r |
| 487 | #define FE_RHBASE 036 /* boot: RH11 addr */\r |
| 488 | #define FE_UNIT 037 /* boot: unit num */\r |
| 489 | #define FE_MTFMT 040 /* boot: magtape params */\r |
| 490 | #define FE_CVALID 0400 /* char valid flag */\r |
| 491 | \r |
| 492 | /* Halfword operations */\r |
| 493 | \r |
| 494 | #define ADDL(x,y) (((x) + ((y) << 18)) & LMASK)\r |
| 495 | #define ADDR(x,y) (((x) + (y)) & RMASK)\r |
| 496 | #define INCL(x) ADDL (x, 1)\r |
| 497 | #define INCR(x) ADDR (x, 1)\r |
| 498 | #define AOB(x) (INCL (x) | INCR(x))\r |
| 499 | #define SUBL(x,y) (((x) - ((y) << 18)) & LMASK)\r |
| 500 | #define SUBR(x,y) (((x) - (y)) & RMASK)\r |
| 501 | #define DECL(x) SUBL (x, 1)\r |
| 502 | #define DECR(x) SUBR (x, 1)\r |
| 503 | #define SOB(x) (DECL (x) | DECR(x))\r |
| 504 | #define LLZ(x) ((x) & LMASK)\r |
| 505 | #define RLZ(x) (((x) << 18) & LMASK)\r |
| 506 | #define RRZ(x) ((x) & RMASK)\r |
| 507 | #define LRZ(x) (((x) >> 18) & RMASK)\r |
| 508 | #define LIT8(x) (((x) & RSIGN)? \\r |
| 509 | (((x) & 0377)? (-(x) & 0377): 0400): ((x) & 0377))\r |
| 510 | \r |
| 511 | /* Fullword operations */\r |
| 512 | \r |
| 513 | #define INC(x) (((x) + 1) & DMASK)\r |
| 514 | #define DEC(x) (((x) - 1) & DMASK)\r |
| 515 | #define SWP(x) ((((x) << 18) & LMASK) | (((x) >> 18) & RMASK))\r |
| 516 | #define XWD(x,y) (((((d10) (x)) << 18) & LMASK) | (((d10) (y)) & RMASK))\r |
| 517 | #define SETS(x) ((x) | SIGN)\r |
| 518 | #define CLRS(x) ((x) & ~SIGN)\r |
| 519 | #define TSTS(x) ((x) & SIGN)\r |
| 520 | #define NEG(x) (-(x) & DMASK)\r |
| 521 | #define ABS(x) (TSTS (x)? NEG(x): (x))\r |
| 522 | #define SXT(x) (TSTS (x)? (x) | ~DMASK: (x))\r |
| 523 | \r |
| 524 | /* Doubleword operations (on 2-word arrays) */\r |
| 525 | \r |
| 526 | #define DMOVN(rs) rs[1] = (-rs[1]) & MMASK; \\r |
| 527 | rs[0] = (~rs[0] + (rs[1] == 0)) & DMASK\r |
| 528 | #define MKDNEG(rs) rs[1] = SETS (-rs[1]) & DMASK; \\r |
| 529 | rs[0] = (~rs[0] + (rs[1] == MAXNEG)) & DMASK\r |
| 530 | #define DCMPGE(a,b) ((a[0] > b[0]) || ((a[0] == b[0]) && (a[1] >= b[1])))\r |
| 531 | \r |
| 532 | /* Address operations */\r |
| 533 | \r |
| 534 | #define ADDA(x,i) (((x) + (i)) & AMASK)\r |
| 535 | #define INCA(x) ADDA (x, 1)\r |
| 536 | \r |
| 537 | /* Unibus adapter control/status register */\r |
| 538 | \r |
| 539 | #define UBCS_TMO 0400000 /* timeout */\r |
| 540 | #define UBCS_BMD 0200000 /* bad mem data NI */\r |
| 541 | #define UBCS_PAR 0100000 /* parity error NI */\r |
| 542 | #define UBCS_NXD 0040000 /* nx device */\r |
| 543 | #define UBCS_HI 0004000 /* irq on BR7 or BR6 */\r |
| 544 | #define UBCS_LO 0002000 /* irq on BR5 or BR4 */\r |
| 545 | #define UBCS_PWR 0001000 /* power low NI */\r |
| 546 | #define UBCS_DXF 0000200 /* disable xfer NI*/\r |
| 547 | #define UBCS_INI 0000100 /* Unibus init */\r |
| 548 | #define UBCS_RDZ 0030500 /* read as zero */\r |
| 549 | #define UBCS_RDW 0000277 /* read/write bits */\r |
| 550 | #define UBCS_V_LHI 3 /* hi pri irq level */\r |
| 551 | #define UBCS_V_LLO 0 /* lo pri irq level */\r |
| 552 | #define UBCS_M_PRI 07\r |
| 553 | #define UBCS_GET_HI(x) (((x) >> UBCS_V_LHI) & UBCS_M_PRI)\r |
| 554 | #define UBCS_GET_LO(x) (((x) >> UBCS_V_LLO) & UBCS_M_PRI)\r |
| 555 | \r |
| 556 | /* Unibus adapter page map */\r |
| 557 | \r |
| 558 | #define UBANUM 2 /* # of Unibus adapters */\r |
| 559 | #define UMAP_ASIZE 6 /* address size */\r |
| 560 | #define UMAP_MEMSIZE (1 << UMAP_ASIZE) /* length */\r |
| 561 | #define UMAP_AMASK (UMAP_MEMSIZE - 1)\r |
| 562 | #define UMAP_V_RRV 30 /* read reverse */\r |
| 563 | #define UMAP_V_DSB 29 /* 16b on NPR read */\r |
| 564 | #define UMAP_V_FST 28 /* fast transfer */\r |
| 565 | #define UMAP_V_VLD 27 /* valid flag */\r |
| 566 | #define UMAP_RRV (1 << UMAP_V_RRV)\r |
| 567 | #define UMAP_DSB (1 << UMAP_V_DSB)\r |
| 568 | #define UMAP_FST (1 << UMAP_V_FST)\r |
| 569 | #define UMAP_VLD (1 << UMAP_V_VLD)\r |
| 570 | #define UMAP_V_FLWR 14 /* flags as written */\r |
| 571 | #define UMAP_V_FLRD 27 /* flags as stored */\r |
| 572 | #define UMAP_M_FL 017\r |
| 573 | #define UMAP_V_PNWR 0 /* page num, write */\r |
| 574 | #define UMAP_V_PNRD 9 /* page num, read */\r |
| 575 | #define UMAP_M_PN 03777\r |
| 576 | #define UMAP_MASK ((UMAP_M_FL << UMAP_V_FLRD) | (UMAP_M_PN << UMAP_V_PNRD))\r |
| 577 | #define UMAP_POSFL(x) (((x) & (UMAP_M_FL << UMAP_V_FLWR)) \\r |
| 578 | << (UMAP_V_FLRD - UMAP_V_FLWR))\r |
| 579 | #define UMAP_POSPN(x) (((x) & (UMAP_M_PN << UMAP_V_PNWR)) \\r |
| 580 | << (UMAP_V_PNRD - UMAP_V_PNWR))\r |
| 581 | \r |
| 582 | /* Unibus I/O constants */\r |
| 583 | \r |
| 584 | #define READ 0 /* PDP11 compatible */\r |
| 585 | /* #define READC 1 /* console read */\r |
| 586 | #define WRITE 2\r |
| 587 | /* #define WRITEC 3 /* console write */\r |
| 588 | #define WRITEB 4\r |
| 589 | #define IO_V_UBA 18 /* UBA in I/O addr */\r |
| 590 | #define IO_N_UBA 16 /* max num of UBA's */\r |
| 591 | #define IO_M_UBA (IO_N_UBA - 1)\r |
| 592 | #define IO_UBA1 (1 << IO_V_UBA)\r |
| 593 | #define IO_UBA3 (3 << IO_V_UBA)\r |
| 594 | #define GET_IOUBA(x) (((x) >> IO_V_UBA) & IO_M_UBA)\r |
| 595 | \r |
| 596 | /* Device information block */\r |
| 597 | \r |
| 598 | #define VEC_DEVMAX 8 /* max device vec */\r |
| 599 | \r |
| 600 | struct pdp_dib {\r |
| 601 | uint32 ba; /* base addr */\r |
| 602 | uint32 lnt; /* length */\r |
| 603 | t_stat (*rd)(int32 *dat, int32 ad, int32 md);\r |
| 604 | t_stat (*wr)(int32 dat, int32 ad, int32 md);\r |
| 605 | int32 vnum; /* vectors: number */\r |
| 606 | int32 vloc; /* locator */\r |
| 607 | int32 vec; /* value */\r |
| 608 | int32 (*ack[VEC_DEVMAX])(void); /* ack routines */\r |
| 609 | };\r |
| 610 | \r |
| 611 | typedef struct pdp_dib DIB;\r |
| 612 | \r |
| 613 | /* I/O system parameters */\r |
| 614 | \r |
| 615 | #define DZ_MUXES 4 /* max # of muxes */\r |
| 616 | #define DZ_LINES 8 /* lines per mux */\r |
| 617 | #define DIB_MAX 100 /* max DIBs */\r |
| 618 | \r |
| 619 | #define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */\r |
| 620 | #define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */\r |
| 621 | #define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus, mem <= 256KB */\r |
| 622 | #define DEV_V_FLTA (DEV_V_UF + 3) /* float addr */\r |
| 623 | #define DEV_UBUS (1u << DEV_V_UBUS)\r |
| 624 | #define DEV_QBUS (1u << DEV_V_QBUS)\r |
| 625 | #define DEV_Q18 (1u << DEV_V_Q18)\r |
| 626 | #define DEV_FLTA (1u << DEV_V_FLTA)\r |
| 627 | \r |
| 628 | #define UNIBUS TRUE /* 18b only */\r |
| 629 | \r |
| 630 | #define DEV_RDX 8 /* default device radix */\r |
| 631 | \r |
| 632 | /* I/O page layout */\r |
| 633 | \r |
| 634 | #define IOPAGEBASE 0760000 /* I/O page base */\r |
| 635 | #define IOBA_UBMAP 0763000\r |
| 636 | \r |
| 637 | #define IOBA_UBMAP1 (IO_UBA1 + IOBA_UBMAP) /* Unibus 1 map */\r |
| 638 | #define IOLN_UBMAP1 0100\r |
| 639 | #define IOBA_UBCS1 (IO_UBA1 + 0763100) /* Unibus 1 c/s reg */\r |
| 640 | #define IOLN_UBCS1 001\r |
| 641 | #define IOBA_UBMNT1 (IO_UBA1 + 0763101) /* Unibus 1 maint reg */\r |
| 642 | #define IOLN_UBMNT1 001\r |
| 643 | #define IOBA_RP (IO_UBA1 + 0776700) /* RH11/disk */\r |
| 644 | #define IOLN_RP 050\r |
| 645 | \r |
| 646 | #define IOBA_DZ (IO_UBA3 + 0760010) /* DZ11 */\r |
| 647 | #define IOLN_DZ 010\r |
| 648 | #define IOBA_TCU (IO_UBA3 + 0760770) /* TCU150 */\r |
| 649 | #define IOLN_TCU 006\r |
| 650 | #define IOBA_UBMAP3 (IO_UBA3 + IOBA_UBMAP) /* Unibus 3 map */\r |
| 651 | #define IOLN_UBMAP3 0100\r |
| 652 | #define IOBA_UBCS3 (IO_UBA3 + 0763100) /* Unibus 3 c/s reg */\r |
| 653 | #define IOLN_UBCS3 001\r |
| 654 | #define IOBA_UBMNT3 (IO_UBA3 + 0763101) /* Unibus 3 maint reg */\r |
| 655 | #define IOLN_UBMNT3 001\r |
| 656 | #define IOBA_XU (IO_UBA3 + 0774510) /* DEUNA/DELUA */\r |
| 657 | #define IOLN_XU 010\r |
| 658 | #define IOBA_CR (IO_UBA3 + 0777160) /* CD/CR/CM */\r |
| 659 | #define IOLN_CR 010\r |
| 660 | #define IOBA_RY (IO_UBA3 + 0777170) /* RX211 */\r |
| 661 | #define IOLN_RY 004\r |
| 662 | #define IOBA_TU (IO_UBA3 + 0772440) /* RH11/tape */\r |
| 663 | #define IOLN_TU 034\r |
| 664 | #define IOBA_LP20 (IO_UBA3 + 0775400) /* LP20 */\r |
| 665 | #define IOLN_LP20 020\r |
| 666 | #define IOBA_PTR (IO_UBA3 + 017550) /* PC11 reader */\r |
| 667 | #define IOLN_PTR 004\r |
| 668 | #define IOBA_PTP (IO_UBA3 + 017554) /* PC11 punch */\r |
| 669 | #define IOLN_PTP 004\r |
| 670 | \r |
| 671 | /* Common Unibus CSR flags */\r |
| 672 | \r |
| 673 | #define CSR_V_GO 0 /* go */\r |
| 674 | #define CSR_V_IE 6 /* interrupt enable */\r |
| 675 | #define CSR_V_DONE 7 /* done */\r |
| 676 | #define CSR_V_BUSY 11 /* busy */\r |
| 677 | #define CSR_V_ERR 15 /* error */\r |
| 678 | #define CSR_GO (1u << CSR_V_GO)\r |
| 679 | #define CSR_IE (1u << CSR_V_IE)\r |
| 680 | #define CSR_DONE (1u << CSR_V_DONE)\r |
| 681 | #define CSR_BUSY (1u << CSR_V_BUSY)\r |
| 682 | #define CSR_ERR (1u << CSR_V_ERR)\r |
| 683 | \r |
| 684 | /* I/O system definitions, lifted from the PDP-11 simulator\r |
| 685 | Interrupt assignments, priority is right to left\r |
| 686 | \r |
| 687 | <3:0> = BR7\r |
| 688 | <7:4> = BR6\r |
| 689 | <19:8> = BR5\r |
| 690 | <30:20> = BR4\r |
| 691 | */\r |
| 692 | \r |
| 693 | #define INT_V_RP 6 /* RH11/RP,RM drives */\r |
| 694 | #define INT_V_TU 7 /* RH11/TM03/TU45 */\r |
| 695 | #define INT_V_XU 15 /* DEUNA/DELUA */\r |
| 696 | #define INT_V_DZRX 16 /* DZ11 */\r |
| 697 | #define INT_V_DZTX 17\r |
| 698 | #define INT_V_RY 18 /* RX211 */\r |
| 699 | #define INT_V_PTR 24 /* PC11 */\r |
| 700 | #define INT_V_PTP 25\r |
| 701 | #define INT_V_LP20 26 /* LPT20 */\r |
| 702 | #define INT_V_CR 27 /* CD20 (CD11) */\r |
| 703 | \r |
| 704 | #define INT_RP (1u << INT_V_RP)\r |
| 705 | #define INT_TU (1u << INT_V_TU)\r |
| 706 | #define INT_XU (1u << INT_V_XU)\r |
| 707 | #define INT_DZRX (1u << INT_V_DZRX)\r |
| 708 | #define INT_DZTX (1u << INT_V_DZTX)\r |
| 709 | #define INT_RY (1u << INT_V_RY)\r |
| 710 | #define INT_PTR (1u << INT_V_PTR)\r |
| 711 | #define INT_PTP (1u << INT_V_PTP)\r |
| 712 | #define INT_LP20 (1u << INT_V_LP20)\r |
| 713 | #define INT_CR (1u << INT_V_CR)\r |
| 714 | \r |
| 715 | #define IPL_RP 6 /* int levels */\r |
| 716 | #define IPL_TU 6\r |
| 717 | #define IPL_XU 5\r |
| 718 | #define IPL_DZRX 5\r |
| 719 | #define IPL_DZTX 5\r |
| 720 | #define IPL_RY 5\r |
| 721 | #define IPL_PTR 4\r |
| 722 | #define IPL_PTP 4\r |
| 723 | #define IPL_LP20 4\r |
| 724 | #define IPL_CR 4\r |
| 725 | \r |
| 726 | #define INT_UB1 INT_RP /* on Unibus 1 */\r |
| 727 | #define INT_UB3 (0xFFFFFFFFu & ~INT_UB1) /* on Unibus 3 */\r |
| 728 | \r |
| 729 | #define INT_IPL7 0x0000000F /* int level masks */\r |
| 730 | #define INT_IPL6 0x000000F0\r |
| 731 | #define INT_IPL5 0x000FFF00\r |
| 732 | #define INT_IPL4 0x3FF00000\r |
| 733 | \r |
| 734 | #define VEC_Q 0000 /* vector base */\r |
| 735 | #define VEC_PTR 0070 /* interrupt vectors */\r |
| 736 | #define VEC_PTP 0074\r |
| 737 | #define VEC_XU 0120\r |
| 738 | #define VEC_TU 0224\r |
| 739 | #define VEC_CR 0230\r |
| 740 | #define VEC_RP 0254\r |
| 741 | #define VEC_RY 0264\r |
| 742 | #define VEC_DZRX 0340\r |
| 743 | #define VEC_DZTX 0344\r |
| 744 | #define VEC_LP20 0754\r |
| 745 | \r |
| 746 | #define IVCL(dv) (INT_V_##dv)\r |
| 747 | #define IREQ(dv) int_req\r |
| 748 | #define SET_INT(dv) IREQ(dv) = IREQ(dv) | (INT_##dv)\r |
| 749 | #define CLR_INT(dv) IREQ(dv) = IREQ(dv) & ~(INT_##dv)\r |
| 750 | \r |
| 751 | /* Function prototypes */\r |
| 752 | \r |
| 753 | int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);\r |
| 754 | int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);\r |
| 755 | int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf);\r |
| 756 | int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf);\r |
| 757 | \r |
| 758 | t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 759 | t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 760 | t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 761 | t_stat set_vec (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 762 | t_stat show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 763 | t_stat auto_config (char *name, int32 num);\r |
| 764 | \r |
| 765 | int32 clk_cosched (int32 wait);\r |
| 766 | \r |
| 767 | /* Global data */\r |
| 768 | \r |
| 769 | extern t_bool sim_idle_enab;\r |
| 770 | \r |
| 771 | #endif\r |