| 1 | /* pdp10_fe.c: PDP-10 front end (console terminal) simulator\r |
| 2 | \r |
| 3 | Copyright (c) 1993-2007, Robert M Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | fe KS10 console front end\r |
| 27 | \r |
| 28 | 18-Jun-07 RMS Added UNIT_IDLE flag to console input\r |
| 29 | 17-Oct-06 RMS Synced keyboard to clock for idling\r |
| 30 | 28-May-04 RMS Removed SET FE CTRL-C\r |
| 31 | 29-Dec-03 RMS Added console backpressure support\r |
| 32 | 25-Apr-03 RMS Revised for extended file support\r |
| 33 | 22-Dec-02 RMS Added break support\r |
| 34 | 30-May-02 RMS Widened COUNT to 32b\r |
| 35 | 30-Nov-01 RMS Added extended SET/SHOW support\r |
| 36 | 23-Oct-01 RMS New IO page address constants\r |
| 37 | 07-Sep-01 RMS Moved function prototypes\r |
| 38 | */\r |
| 39 | \r |
| 40 | #include "pdp10_defs.h"\r |
| 41 | #define UNIT_DUMMY (1 << UNIT_V_UF)\r |
| 42 | \r |
| 43 | extern d10 *M;\r |
| 44 | extern int32 apr_flg;\r |
| 45 | extern int32 tmxr_poll;\r |
| 46 | t_stat fei_svc (UNIT *uptr);\r |
| 47 | t_stat feo_svc (UNIT *uptr);\r |
| 48 | t_stat fe_reset (DEVICE *dptr);\r |
| 49 | t_stat fe_stop_os (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 50 | \r |
| 51 | /* FE data structures\r |
| 52 | \r |
| 53 | fe_dev FE device descriptor\r |
| 54 | fe_unit FE unit descriptor\r |
| 55 | fe_reg FE register list\r |
| 56 | */\r |
| 57 | \r |
| 58 | #define fei_unit fe_unit[0]\r |
| 59 | #define feo_unit fe_unit[1]\r |
| 60 | \r |
| 61 | UNIT fe_unit[] = {\r |
| 62 | { UDATA (&fei_svc, UNIT_IDLE, 0), 0 },\r |
| 63 | { UDATA (&feo_svc, 0, 0), SERIAL_OUT_WAIT }\r |
| 64 | };\r |
| 65 | \r |
| 66 | REG fe_reg[] = {\r |
| 67 | { ORDATA (IBUF, fei_unit.buf, 8) },\r |
| 68 | { DRDATA (ICOUNT, fei_unit.pos, T_ADDR_W), REG_RO + PV_LEFT },\r |
| 69 | { DRDATA (ITIME, fei_unit.wait, 24), PV_LEFT },\r |
| 70 | { ORDATA (OBUF, feo_unit.buf, 8) },\r |
| 71 | { DRDATA (OCOUNT, feo_unit.pos, T_ADDR_W), REG_RO + PV_LEFT },\r |
| 72 | { DRDATA (OTIME, feo_unit.wait, 24), REG_NZ + PV_LEFT },\r |
| 73 | { NULL }\r |
| 74 | };\r |
| 75 | \r |
| 76 | MTAB fe_mod[] = {\r |
| 77 | { UNIT_DUMMY, 0, NULL, "STOP", &fe_stop_os },\r |
| 78 | { 0 }\r |
| 79 | };\r |
| 80 | \r |
| 81 | DEVICE fe_dev = {\r |
| 82 | "FE", fe_unit, fe_reg, fe_mod,\r |
| 83 | 2, 10, 31, 1, 8, 8,\r |
| 84 | NULL, NULL, &fe_reset,\r |
| 85 | NULL, NULL, NULL\r |
| 86 | };\r |
| 87 | \r |
| 88 | /* Front end processor (console terminal)\r |
| 89 | \r |
| 90 | Communications between the KS10 and its front end is based on an in-memory\r |
| 91 | status block and two interrupt lines: interrupt-to-control (APR_ITC) and\r |
| 92 | interrupt-from-console (APR_CON). When the KS10 wants to print a character\r |
| 93 | on the terminal,\r |
| 94 | \r |
| 95 | 1. It places a character, plus the valid flag, in FE_CTYOUT.\r |
| 96 | 2. It interrupts the front end processor.\r |
| 97 | 3. The front end processor types the character and then zeroes FE_CTYOUT.\r |
| 98 | 4. The front end procesor interrupts the KS10.\r |
| 99 | \r |
| 100 | When the front end wants to send an input character to the KS10,\r |
| 101 | \r |
| 102 | 1. It places a character, plus the valid flag, in FE_CTYIN.\r |
| 103 | 2. It interrupts the KS10.\r |
| 104 | 3. It waits for the KS10 to take the character and clear the valid flag.\r |
| 105 | 4. It can then send more input (the KS10 may signal this by interrupting\r |
| 106 | the front end).\r |
| 107 | \r |
| 108 | Note that the protocol has both ambiguity (interrupt to the KS10 may mean\r |
| 109 | character printed, or input character available, or both) and lack of\r |
| 110 | symmetry (the KS10 does not inform the front end that it has taken an\r |
| 111 | input character). \r |
| 112 | */\r |
| 113 | \r |
| 114 | void fe_intr (void)\r |
| 115 | {\r |
| 116 | if (M[FE_CTYOUT] & FE_CVALID) { /* char to print? */\r |
| 117 | feo_unit.buf = (int32) M[FE_CTYOUT] & 0177; /* pick it up */\r |
| 118 | feo_unit.pos = feo_unit.pos + 1;\r |
| 119 | sim_activate (&feo_unit, feo_unit.wait); /* sched completion */\r |
| 120 | }\r |
| 121 | else if ((M[FE_CTYIN] & FE_CVALID) == 0) { /* input char taken? */\r |
| 122 | sim_cancel (&fei_unit); /* sched immediate */\r |
| 123 | sim_activate (&fei_unit, 0); /* keyboard poll */\r |
| 124 | }\r |
| 125 | return;\r |
| 126 | }\r |
| 127 | \r |
| 128 | t_stat feo_svc (UNIT *uptr)\r |
| 129 | {\r |
| 130 | t_stat r;\r |
| 131 | \r |
| 132 | if ((r = sim_putchar_s (uptr->buf)) != SCPE_OK) { /* output; error? */\r |
| 133 | sim_activate (uptr, uptr->wait); /* try again */\r |
| 134 | return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */\r |
| 135 | }\r |
| 136 | M[FE_CTYOUT] = 0; /* clear char */\r |
| 137 | apr_flg = apr_flg | APRF_CON; /* interrupt KS10 */\r |
| 138 | return SCPE_OK;\r |
| 139 | }\r |
| 140 | \r |
| 141 | t_stat fei_svc (UNIT *uptr)\r |
| 142 | {\r |
| 143 | int32 temp;\r |
| 144 | \r |
| 145 | sim_activate (uptr, KBD_WAIT (uptr->wait, tmxr_poll)); /* continue poll */\r |
| 146 | if ((temp = sim_poll_kbd ()) < SCPE_KFLAG) return temp; /* no char or error? */\r |
| 147 | if (temp & SCPE_BREAK) return SCPE_OK; /* ignore break */\r |
| 148 | uptr->buf = temp & 0177;\r |
| 149 | uptr->pos = uptr->pos + 1;\r |
| 150 | M[FE_CTYIN] = uptr->buf | FE_CVALID; /* put char in mem */\r |
| 151 | apr_flg = apr_flg | APRF_CON; /* interrupt KS10 */\r |
| 152 | return SCPE_OK;\r |
| 153 | }\r |
| 154 | \r |
| 155 | /* Reset */\r |
| 156 | \r |
| 157 | t_stat fe_reset (DEVICE *dptr)\r |
| 158 | {\r |
| 159 | fei_unit.buf = feo_unit.buf = 0;\r |
| 160 | M[FE_CTYIN] = M[FE_CTYOUT] = 0;\r |
| 161 | apr_flg = apr_flg & ~(APRF_ITC | APRF_CON);\r |
| 162 | sim_activate_abs (&fei_unit, KBD_WAIT (fei_unit.wait, tmxr_poll));\r |
| 163 | return SCPE_OK;\r |
| 164 | }\r |
| 165 | \r |
| 166 | /* Stop operating system */\r |
| 167 | \r |
| 168 | t_stat fe_stop_os (UNIT *uptr, int32 val, char *cptr, void *desc)\r |
| 169 | {\r |
| 170 | M[FE_SWITCH] = IOBA_RP; /* tell OS to stop */\r |
| 171 | return SCPE_OK;\r |
| 172 | }\r |