| 1 | /* pdp11_cpumod.c: PDP-11 CPU model-specific features\r |
| 2 | \r |
| 3 | Copyright (c) 2004-2008, Robert M Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | system PDP-11 model-specific registers\r |
| 27 | \r |
| 28 | 20-May-08 RMS Added JCSR default for KDJ11B, KDJ11E\r |
| 29 | 22-Apr-08 RMS Fixed write behavior of 11/70 MBRK, LOSIZE, HISIZE\r |
| 30 | (found by Walter Mueller)\r |
| 31 | 29-Apr-07 RMS Don't run bus setup routine during RESTORE\r |
| 32 | 30-Aug-05 RMS Added additional 11/60 registers\r |
| 33 | 16-Aug-05 RMS Fixed C++ declaration and cast problems\r |
| 34 | 15-Feb-05 RMS Fixed bug in SHOW MODEL (from Sergey Okhapkin)\r |
| 35 | 19-Jan-05 RMS Added variable SYSID, MBRK write (from Tim Chapman)\r |
| 36 | \r |
| 37 | This module includes CPU- and system-specific registers, such as the Unibus\r |
| 38 | map and control registers on 22b Unibus systems, the board registers for the\r |
| 39 | F11- and J11-based systems, and the system registers for the PDP-11/44,\r |
| 40 | PDP-11/45, PDP-11/60, and PDP-11/70. Most registers are implemented at\r |
| 41 | a minimum level: just enough to satisfy the machine identification code\r |
| 42 | in the various operating systems.\r |
| 43 | */\r |
| 44 | \r |
| 45 | #include "pdp11_defs.h"\r |
| 46 | #include "pdp11_cpumod.h"\r |
| 47 | #include <time.h>\r |
| 48 | \r |
| 49 | /* Byte write macros for system registers */\r |
| 50 | \r |
| 51 | #define ODD_IGN(cur) \\r |
| 52 | if ((access == WRITEB) && (pa & 1)) return SCPE_OK\r |
| 53 | #define ODD_WO(cur) \\r |
| 54 | if ((access == WRITEB) && (pa & 1)) cur = cur << 8\r |
| 55 | #define ODD_MRG(prv,cur) \\r |
| 56 | if (access == WRITEB) cur = \\r |
| 57 | ((pa & 1)? (((prv) & 0377) | ((cur) & 0177400)) : \\r |
| 58 | (((prv) & 0177400) | ((cur) & 0377)))\r |
| 59 | \r |
| 60 | int32 SR = 0; /* switch register */\r |
| 61 | int32 DR = 0; /* display register */\r |
| 62 | int32 MBRK = 0; /* 11/70 microbreak */\r |
| 63 | int32 SYSID = 0x1234; /* 11/70 system ID */\r |
| 64 | int32 WCS = 0; /* 11/60 WCS control */\r |
| 65 | int32 CPUERR = 0; /* CPU error reg */\r |
| 66 | int32 MEMERR = 0; /* memory error reg */\r |
| 67 | int32 CCR = 0; /* cache control reg */\r |
| 68 | int32 HITMISS = 0; /* hit/miss reg */\r |
| 69 | int32 MAINT = 0; /* maint reg */\r |
| 70 | int32 JCSR = 0; /* J11 control */\r |
| 71 | int32 JCSR_dflt = 0; /* J11 boot ctl def */\r |
| 72 | int32 JPCR = 0; /* J11 page ctrl */\r |
| 73 | int32 JASR = 0; /* J11 addtl status */\r |
| 74 | int32 UDCR = 0; /* UBA diag ctrl */\r |
| 75 | int32 UDDR = 0; /* UBA diag data */\r |
| 76 | int32 UCSR = 0; /* UBA control */\r |
| 77 | int32 uba_last = 0; /* UBA last mapped */\r |
| 78 | int32 ub_map[UBM_LNT_LW] = { 0 }; /* UBA map array */\r |
| 79 | int32 toy_state = 0;\r |
| 80 | uint8 toy_data[TOY_LNT] = { 0 };\r |
| 81 | static int32 clk_tps_map[4] = { 60, 60, 50, 800 };\r |
| 82 | \r |
| 83 | extern uint16 *M;\r |
| 84 | extern int32 R[8];\r |
| 85 | extern DEVICE cpu_dev, *sim_devices[];\r |
| 86 | extern UNIT cpu_unit;\r |
| 87 | extern FILE *sim_log;\r |
| 88 | extern int32 STKLIM, PIRQ;\r |
| 89 | extern uint32 cpu_model, cpu_type, cpu_opt;\r |
| 90 | extern int32 clk_fie, clk_fnxm, clk_tps, clk_default;\r |
| 91 | extern int32 sim_switches;\r |
| 92 | \r |
| 93 | t_stat CPU24_rd (int32 *data, int32 addr, int32 access);\r |
| 94 | t_stat CPU24_wr (int32 data, int32 addr, int32 access);\r |
| 95 | t_stat CPU44_rd (int32 *data, int32 addr, int32 access);\r |
| 96 | t_stat CPU44_wr (int32 data, int32 addr, int32 access);\r |
| 97 | t_stat CPU45_rd (int32 *data, int32 addr, int32 access);\r |
| 98 | t_stat CPU45_wr (int32 data, int32 addr, int32 access);\r |
| 99 | t_stat CPU60_rd (int32 *data, int32 addr, int32 access);\r |
| 100 | t_stat CPU60_wr (int32 data, int32 addr, int32 access);\r |
| 101 | t_stat CPU70_rd (int32 *data, int32 addr, int32 access);\r |
| 102 | t_stat CPU70_wr (int32 data, int32 addr, int32 access);\r |
| 103 | t_stat CPUJ_rd (int32 *data, int32 addr, int32 access);\r |
| 104 | t_stat CPUJ_wr (int32 data, int32 addr, int32 access);\r |
| 105 | t_stat REG_rd (int32 *data, int32 addr, int32 access);\r |
| 106 | t_stat REG_wr (int32 data, int32 addr, int32 access);\r |
| 107 | t_stat SR_rd (int32 *data, int32 addr, int32 access);\r |
| 108 | t_stat DR_wr (int32 data, int32 addr, int32 access);\r |
| 109 | t_stat CTLFB_rd (int32 *data, int32 addr, int32 access);\r |
| 110 | t_stat CTLFB_wr (int32 data, int32 addr, int32 access);\r |
| 111 | t_stat CTLJB_rd (int32 *data, int32 addr, int32 access);\r |
| 112 | t_stat CTLJB_wr (int32 data, int32 addr, int32 access);\r |
| 113 | t_stat CTLJD_rd (int32 *data, int32 addr, int32 access);\r |
| 114 | t_stat CTLJD_wr (int32 data, int32 addr, int32 access);\r |
| 115 | t_stat CTLJE_rd (int32 *data, int32 addr, int32 access);\r |
| 116 | t_stat CTLJE_wr (int32 data, int32 addr, int32 access);\r |
| 117 | t_stat UBA24_rd (int32 *data, int32 addr, int32 access);\r |
| 118 | t_stat UBA24_wr (int32 data, int32 addr, int32 access);\r |
| 119 | t_stat UBAJ_rd (int32 *data, int32 addr, int32 access);\r |
| 120 | t_stat UBAJ_wr (int32 data, int32 addr, int32 access);\r |
| 121 | t_stat sys_reset (DEVICE *dptr);\r |
| 122 | int32 toy_read (void);\r |
| 123 | void toy_write (int32 bit);\r |
| 124 | uint8 toy_set (int32 val);\r |
| 125 | t_stat sys_set_jclk_dflt (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 126 | t_stat sys_show_jclk_dflt (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 127 | \r |
| 128 | extern t_stat PSW_rd (int32 *data, int32 addr, int32 access);\r |
| 129 | extern t_stat PSW_wr (int32 data, int32 addr, int32 access);\r |
| 130 | extern t_stat APR_rd (int32 *data, int32 addr, int32 access);\r |
| 131 | extern t_stat APR_wr (int32 data, int32 addr, int32 access);\r |
| 132 | extern t_stat MMR012_rd (int32 *data, int32 addr, int32 access);\r |
| 133 | extern t_stat MMR012_wr (int32 data, int32 addr, int32 access);\r |
| 134 | extern t_stat MMR3_rd (int32 *data, int32 addr, int32 access);\r |
| 135 | extern t_stat MMR3_wr (int32 data, int32 addr, int32 access);\r |
| 136 | extern t_stat ubm_rd (int32 *data, int32 addr, int32 access);\r |
| 137 | extern t_stat ubm_wr (int32 data, int32 addr, int32 access);\r |
| 138 | extern void put_PIRQ (int32 val);\r |
| 139 | \r |
| 140 | /* Fixed I/O address table entries */\r |
| 141 | \r |
| 142 | DIB psw_dib = { IOBA_PSW, IOLN_PSW, &PSW_rd, &PSW_wr, 0 };\r |
| 143 | DIB cpuj_dib = { IOBA_CPU, IOLN_CPU, &CPUJ_rd, &CPUJ_wr, 0 };\r |
| 144 | DIB cpu24_dib = { IOBA_CPU, IOLN_CPU, &CPU24_rd, &CPU24_wr, 0 };\r |
| 145 | DIB cpu44_dib = { IOBA_CPU, IOLN_CPU, &CPU44_rd, &CPU44_wr, 0 };\r |
| 146 | DIB cpu45_dib = { IOBA_CPU, IOLN_CPU, &CPU45_rd, &CPU45_wr, 0 };\r |
| 147 | DIB cpu60_dib = { IOBA_CPU, IOLN_CPU, &CPU60_rd, &CPU60_wr, 0 };\r |
| 148 | DIB cpu70_dib = { IOBA_CPU, IOLN_CPU, &CPU70_rd, &CPU70_wr, 0 };\r |
| 149 | DIB reg_dib = { IOBA_GPR, IOLN_GPR, ®_rd, ®_wr, 0 };\r |
| 150 | DIB ctlfb_dib = { IOBA_CTL, IOLN_CTL, &CTLFB_rd, &CTLFB_wr };\r |
| 151 | DIB ctljb_dib = { IOBA_CTL, IOLN_CTL, &CTLJB_rd, &CTLJB_wr };\r |
| 152 | DIB ctljd_dib = { IOBA_CTL, IOLN_CTL, &CTLJD_rd, &CTLJD_wr };\r |
| 153 | DIB ctlje_dib = { IOBA_CTL, IOLN_CTL, &CTLJE_rd, &CTLJE_wr };\r |
| 154 | DIB uba24_dib = { IOBA_UCTL, IOLN_UCTL, &UBA24_rd, &UBA24_wr };\r |
| 155 | DIB ubaj_dib = {IOBA_UCTL, IOLN_UCTL, &UBAJ_rd, &UBAJ_wr };\r |
| 156 | DIB supv_dib = { IOBA_SUP, IOLN_SUP, &APR_rd, &APR_wr, 0 };\r |
| 157 | DIB kipdr_dib = { IOBA_KIPDR, IOLN_KIPDR, &APR_rd, &APR_wr, 0 };\r |
| 158 | DIB kdpdr_dib = { IOBA_KDPDR, IOLN_KDPDR, &APR_rd, &APR_wr, 0 };\r |
| 159 | DIB kipar_dib = { IOBA_KIPAR, IOLN_KIPAR, &APR_rd, &APR_wr, 0 };\r |
| 160 | DIB kdpar_dib = { IOBA_KDPAR, IOLN_KDPAR, &APR_rd, &APR_wr, 0 };\r |
| 161 | DIB uipdr_dib = { IOBA_UIPDR, IOLN_UIPDR, &APR_rd, &APR_wr, 0 };\r |
| 162 | DIB udpdr_dib = { IOBA_UDPDR, IOLN_UDPDR, &APR_rd, &APR_wr, 0 };\r |
| 163 | DIB uipar_dib = { IOBA_UIPAR, IOLN_UIPAR, &APR_rd, &APR_wr, 0 };\r |
| 164 | DIB udpar_dib = { IOBA_UDPAR, IOLN_UDPAR, &APR_rd, &APR_wr, 0 };\r |
| 165 | DIB sr_dib = { IOBA_SR, IOLN_SR, &SR_rd, NULL, 0 };\r |
| 166 | DIB dr_dib = { IOBA_SR, IOLN_SR, NULL, &DR_wr, 0 };\r |
| 167 | DIB mmr012_dib = { IOBA_MMR012, IOLN_MMR012, &MMR012_rd, &MMR012_wr, 0 };\r |
| 168 | DIB mmr3_dib = { IOBA_MMR3, IOLN_MMR3, &MMR3_rd, &MMR3_wr, 0 };\r |
| 169 | DIB ubm_dib = { IOBA_UBM, IOLN_UBM, &ubm_rd, &ubm_wr, 0 };\r |
| 170 | \r |
| 171 | CPUTAB cpu_tab[MOD_MAX] = {\r |
| 172 | { "11/03", SOP_1103, OPT_1103, MEMSIZE64K, PSW_1103,\r |
| 173 | 0, 0, 0, 0, 0 },\r |
| 174 | { "11/04", SOP_1104, OPT_1104, MEMSIZE64K, PSW_1104,\r |
| 175 | 0, 0, 0, 0, 0 },\r |
| 176 | { "11/05", SOP_1105, OPT_1105, MEMSIZE64K, PSW_1105,\r |
| 177 | 0, 0, 0, 0, 0 },\r |
| 178 | { "11/20", SOP_1120, OPT_1120, MEMSIZE64K, PSW_1120,\r |
| 179 | 0, 0, 0, 0, 0 },\r |
| 180 | { "11/23", SOP_1123, OPT_1123, MAXMEMSIZE, PSW_F,\r |
| 181 | MFPT_F, PAR_F, PDR_F, MM0_F, MM3_F },\r |
| 182 | { "11/23+", SOP_1123P, OPT_1123P, MAXMEMSIZE, PSW_F,\r |
| 183 | MFPT_F, PAR_F, PDR_F, MM0_F, MM3_F },\r |
| 184 | { "11/24", SOP_1124, OPT_1124, MAXMEMSIZE, PSW_F,\r |
| 185 | MFPT_F, PAR_F, PDR_F, MM0_F, MM3_F },\r |
| 186 | { "11/34", SOP_1134, OPT_1134, UNIMEMSIZE, PSW_1134,\r |
| 187 | 0, PAR_1134, PDR_1134, MM0_1134, 0 },\r |
| 188 | { "11/40", SOP_1140, OPT_1140, UNIMEMSIZE, PSW_1140,\r |
| 189 | 0, PAR_1140, PDR_1140, MM0_1140, 0 },\r |
| 190 | { "11/44", SOP_1144, OPT_1144, MAXMEMSIZE, PSW_1144,\r |
| 191 | MFPT_44, PAR_1144, PDR_1144, MM0_1144, MM3_1144 },\r |
| 192 | { "11/45", SOP_1145, OPT_1145, UNIMEMSIZE, PSW_1145,\r |
| 193 | 0, PAR_1145, PDR_1145, MM0_1145, MM3_1145 },\r |
| 194 | { "11/60", SOP_1160, OPT_1160, UNIMEMSIZE, PSW_1160,\r |
| 195 | 0, PAR_1160, PDR_1160, MM0_1160, 0 },\r |
| 196 | { "11/70", SOP_1170, OPT_1170, MAXMEMSIZE, PSW_1170,\r |
| 197 | 0, PAR_1170, PDR_1170, MM0_1170, MM3_1170 },\r |
| 198 | { "11/73", SOP_1173, OPT_1173, MAXMEMSIZE, PSW_J,\r |
| 199 | MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },\r |
| 200 | { "11/53", SOP_1153, OPT_1153, MAXMEMSIZE, PSW_J,\r |
| 201 | MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },\r |
| 202 | { "11/73B", SOP_1173B, OPT_1173B, MAXMEMSIZE, PSW_J,\r |
| 203 | MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },\r |
| 204 | { "11/83", SOP_1183, OPT_1183, MAXMEMSIZE, PSW_J,\r |
| 205 | MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },\r |
| 206 | { "11/84", SOP_1184, OPT_1184, MAXMEMSIZE, PSW_J,\r |
| 207 | MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },\r |
| 208 | { "11/93", SOP_1193, OPT_1193, MAXMEMSIZE, PSW_J,\r |
| 209 | MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J },\r |
| 210 | { "11/94", SOP_1194, OPT_1194, MAXMEMSIZE, PSW_J,\r |
| 211 | MFPT_J, PAR_J, PDR_J, MM0_J, MM3_J }\r |
| 212 | };\r |
| 213 | \r |
| 214 | CNFTAB cnf_tab[] = {\r |
| 215 | { HAS_PSW, 0, &psw_dib }, /* PSW */\r |
| 216 | { CPUT_J, 0, &cpuj_dib }, /* CPU control */\r |
| 217 | { CPUT_24, 0, &cpu24_dib },\r |
| 218 | { CPUT_44, 0, &cpu44_dib },\r |
| 219 | { CPUT_45, 0, &cpu45_dib },\r |
| 220 | { CPUT_60, 0, &cpu60_dib },\r |
| 221 | { CPUT_70, 0, &cpu70_dib },\r |
| 222 | { HAS_IOSR, 0, ®_dib },\r |
| 223 | { CPUT_23P, 0, &ctlfb_dib }, /* board ctls */\r |
| 224 | { CPUT_JB, 0, &ctljb_dib },\r |
| 225 | { CPUT_53, 0, &ctljd_dib },\r |
| 226 | { CPUT_JE, 0, &ctlje_dib },\r |
| 227 | { CPUT_24, 0, &uba24_dib }, /* UBA */\r |
| 228 | { CPUT_JU, 0, &ubaj_dib },\r |
| 229 | { 0, OPT_MMU, &kipdr_dib }, /* MMU */\r |
| 230 | { 0, OPT_MMU, &kipar_dib },\r |
| 231 | { 0, OPT_MMU, &uipdr_dib },\r |
| 232 | { 0, OPT_MMU, &uipar_dib },\r |
| 233 | { 0, OPT_MMU, &mmr012_dib }, /* MMR0-2 */\r |
| 234 | { HAS_MMR3, 0, &mmr3_dib }, /* MMR3 */\r |
| 235 | { 0, OPT_UBM, &ubm_dib }, /* Unibus map */\r |
| 236 | { HAS_SID, 0, &kdpdr_dib }, /* supv, I/D */\r |
| 237 | { HAS_SID, 0, &kdpar_dib },\r |
| 238 | { HAS_SID, 0, &supv_dib },\r |
| 239 | { HAS_SID, 0, &udpdr_dib },\r |
| 240 | { HAS_SID, 0, &udpar_dib },\r |
| 241 | { HAS_SR, 0, &sr_dib }, /* SR */\r |
| 242 | { HAS_DR, 0, &dr_dib }, /* DR */\r |
| 243 | { 0, 0, NULL }\r |
| 244 | };\r |
| 245 | \r |
| 246 | static const char *opt_name[] = {\r |
| 247 | "Unibus", "Qbus", "EIS", "NOEIS", "FIS", "NOFIS",\r |
| 248 | "FPP", "NOFPP", "CIS", "NOCIS", "MMU", "NOMMU",\r |
| 249 | "RH11", "RH70", "PARITY", "NOPARITY", "Unibus map", "No map", NULL\r |
| 250 | };\r |
| 251 | \r |
| 252 | static const char *jcsr_val[4] = {\r |
| 253 | "LINE", "50HZ", "60HZ", "800HZ"\r |
| 254 | };\r |
| 255 | \r |
| 256 | /* SYSTEM data structures\r |
| 257 | \r |
| 258 | sys_dev SYSTEM device descriptor\r |
| 259 | sys_unit SYSTEM unit descriptor\r |
| 260 | sys_reg SYSTEM register list\r |
| 261 | */\r |
| 262 | \r |
| 263 | UNIT sys_unit = { UDATA (NULL, 0, 0) };\r |
| 264 | \r |
| 265 | REG sys_reg[] = {\r |
| 266 | { ORDATA (SR, SR, 16) },\r |
| 267 | { ORDATA (DR, DR, 16) },\r |
| 268 | { ORDATA (MEMERR, MEMERR, 16) },\r |
| 269 | { ORDATA (CCR, CCR, 16) },\r |
| 270 | { ORDATA (MAINT, MAINT, 16) },\r |
| 271 | { ORDATA (HITMISS, HITMISS, 16) },\r |
| 272 | { ORDATA (CPUERR, CPUERR, 16) },\r |
| 273 | { ORDATA (MBRK, MBRK, 16) },\r |
| 274 | { ORDATA (WCS, WCS, 16) },\r |
| 275 | { ORDATA (SYSID, SYSID, 16) },\r |
| 276 | { ORDATA (JCSR, JCSR, 16) },\r |
| 277 | { ORDATA (JCSR_DFLT, JCSR_dflt, 16), REG_HRO },\r |
| 278 | { ORDATA (JPCR, JPCR, 16) },\r |
| 279 | { ORDATA (JASR, JASR, 16) },\r |
| 280 | { ORDATA (UDCR, UDCR, 16) },\r |
| 281 | { ORDATA (UDDR, UDDR, 16) },\r |
| 282 | { ORDATA (UCSR, UCSR, 16) },\r |
| 283 | { ORDATA (ULAST, uba_last, 23) },\r |
| 284 | { BRDATA (UBMAP, ub_map, 8, 22, UBM_LNT_LW) },\r |
| 285 | { DRDATA (TOY_STATE, toy_state, 6), REG_HRO },\r |
| 286 | { BRDATA (TOY_DATA, toy_data, 8, 8, TOY_LNT), REG_HRO },\r |
| 287 | { NULL}\r |
| 288 | };\r |
| 289 | \r |
| 290 | MTAB sys_mod[] = {\r |
| 291 | { MTAB_XTD|MTAB_VDV|MTAB_NMO, 0, "JCLK_DFLT", "JCLK_DFLT",\r |
| 292 | &sys_set_jclk_dflt, &sys_show_jclk_dflt },\r |
| 293 | { 0 }\r |
| 294 | };\r |
| 295 | \r |
| 296 | DEVICE sys_dev = {\r |
| 297 | "SYSTEM", &sys_unit, sys_reg, sys_mod,\r |
| 298 | 1, 0, 0, 0, 0, 0,\r |
| 299 | NULL, NULL, &sys_reset,\r |
| 300 | NULL, NULL, NULL,\r |
| 301 | NULL, 0, 0,\r |
| 302 | NULL, NULL, NULL\r |
| 303 | };\r |
| 304 | \r |
| 305 | /* Switch and display registers - many */\r |
| 306 | \r |
| 307 | t_stat SR_rd (int32 *data, int32 pa, int32 access)\r |
| 308 | {\r |
| 309 | *data = SR;\r |
| 310 | return SCPE_OK;\r |
| 311 | }\r |
| 312 | \r |
| 313 | t_stat DR_wr (int32 data, int32 pa, int32 access)\r |
| 314 | {\r |
| 315 | DR = data;\r |
| 316 | return SCPE_OK;\r |
| 317 | }\r |
| 318 | \r |
| 319 | /* GPR's - 11/04, 11/05 */\r |
| 320 | \r |
| 321 | t_stat REG_rd (int32 *data, int32 pa, int32 access)\r |
| 322 | {\r |
| 323 | *data = R[pa & 07];\r |
| 324 | return SCPE_OK;\r |
| 325 | }\r |
| 326 | \r |
| 327 | t_stat REG_wr (int32 data, int32 pa, int32 access)\r |
| 328 | {\r |
| 329 | int32 reg = pa & 07;\r |
| 330 | \r |
| 331 | if (access == WRITE) R[reg] = data;\r |
| 332 | else if (pa & 1) R[reg] = (R[reg] & 0377) | (data << 8);\r |
| 333 | else R[reg] = (R[reg] & ~0377) | data;\r |
| 334 | return SCPE_OK;\r |
| 335 | }\r |
| 336 | \r |
| 337 | /* CPU control registers - 11/24 */\r |
| 338 | \r |
| 339 | t_stat CPU24_rd (int32 *data, int32 pa, int32 access)\r |
| 340 | {\r |
| 341 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 342 | \r |
| 343 | case 013: /* CPUERR */\r |
| 344 | *data = 0;\r |
| 345 | return SCPE_OK;\r |
| 346 | } /* end switch PA */\r |
| 347 | \r |
| 348 | *data = 0;\r |
| 349 | return SCPE_NXM; /* unimplemented */\r |
| 350 | }\r |
| 351 | \r |
| 352 | t_stat CPU24_wr (int32 data, int32 pa, int32 access)\r |
| 353 | {\r |
| 354 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 355 | \r |
| 356 | case 013: /* CPUERR */\r |
| 357 | return SCPE_OK;\r |
| 358 | } /* end switch pa */\r |
| 359 | \r |
| 360 | return SCPE_NXM; /* unimplemented */\r |
| 361 | }\r |
| 362 | \r |
| 363 | /* CPU control registers - 11/44 */\r |
| 364 | \r |
| 365 | t_stat CPU44_rd (int32 *data, int32 pa, int32 access)\r |
| 366 | {\r |
| 367 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 368 | \r |
| 369 | case 002: /* MEMERR */\r |
| 370 | *data = MEMERR;\r |
| 371 | return SCPE_OK;\r |
| 372 | \r |
| 373 | case 003: /* CCR */\r |
| 374 | *data = CCR & CCR44_RD;\r |
| 375 | return SCPE_OK;\r |
| 376 | \r |
| 377 | case 004: /* MAINT */\r |
| 378 | *data = MAINT & CMR44_RD;\r |
| 379 | return SCPE_OK;\r |
| 380 | \r |
| 381 | case 005: /* Hit/miss */\r |
| 382 | *data = HITMISS;\r |
| 383 | return SCPE_OK;\r |
| 384 | \r |
| 385 | case 006: /* CDR */\r |
| 386 | *data = 0;\r |
| 387 | return SCPE_OK;\r |
| 388 | \r |
| 389 | case 013: /* CPUERR */\r |
| 390 | if (CPUERR & CPUE_YEL) /* 11/44 stack err */\r |
| 391 | CPUERR = (CPUERR & ~CPUE_YEL) | CPUE_RED; /* in <2> not <3> */\r |
| 392 | if (CPUERR & (CPUE_ODD|CPUE_NXM|CPUE_TMO)) /* additional flag */\r |
| 393 | CPUERR = CPUERR | CPUE44_BUSE;\r |
| 394 | *data = CPUERR & CPUE_IMP;\r |
| 395 | return SCPE_OK;\r |
| 396 | \r |
| 397 | case 015: /* PIRQ */\r |
| 398 | *data = PIRQ;\r |
| 399 | return SCPE_OK;\r |
| 400 | } /* end switch PA */\r |
| 401 | \r |
| 402 | *data = 0;\r |
| 403 | return SCPE_NXM; /* unimplemented */\r |
| 404 | }\r |
| 405 | \r |
| 406 | t_stat CPU44_wr (int32 data, int32 pa, int32 access)\r |
| 407 | {\r |
| 408 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 409 | \r |
| 410 | case 002: /* MEMERR */\r |
| 411 | MEMERR = 0;\r |
| 412 | return SCPE_OK;\r |
| 413 | \r |
| 414 | case 003: /* CCR */\r |
| 415 | ODD_MRG (CCR, data);\r |
| 416 | CCR = data & CCR44_WR;\r |
| 417 | return SCPE_OK;\r |
| 418 | \r |
| 419 | case 004: /* MAINT */\r |
| 420 | ODD_MRG (MAINT, data);\r |
| 421 | MAINT = data & CMR44_WR;\r |
| 422 | return SCPE_OK;\r |
| 423 | \r |
| 424 | case 005: /* Hit/miss */\r |
| 425 | return SCPE_OK;\r |
| 426 | \r |
| 427 | case 013: /* CPUERR */\r |
| 428 | CPUERR = 0;\r |
| 429 | return SCPE_OK;\r |
| 430 | \r |
| 431 | case 015: /* PIRQ */\r |
| 432 | ODD_WO (data);\r |
| 433 | put_PIRQ (data);\r |
| 434 | return SCPE_OK;\r |
| 435 | }\r |
| 436 | \r |
| 437 | return SCPE_NXM; /* unimplemented */\r |
| 438 | }\r |
| 439 | \r |
| 440 | /* CPU control registers - 11/45 */\r |
| 441 | \r |
| 442 | t_stat CPU45_rd (int32 *data, int32 pa, int32 access)\r |
| 443 | {\r |
| 444 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 445 | \r |
| 446 | case 014: /* MBRK */\r |
| 447 | *data = MBRK;\r |
| 448 | return SCPE_OK;\r |
| 449 | \r |
| 450 | case 015: /* PIRQ */\r |
| 451 | *data = PIRQ;\r |
| 452 | return SCPE_OK;\r |
| 453 | \r |
| 454 | case 016: /* STKLIM */\r |
| 455 | *data = STKLIM & STKLIM_RW;\r |
| 456 | return SCPE_OK;\r |
| 457 | } /* end switch PA */\r |
| 458 | \r |
| 459 | *data = 0;\r |
| 460 | return SCPE_NXM; /* unimplemented */\r |
| 461 | }\r |
| 462 | \r |
| 463 | t_stat CPU45_wr (int32 data, int32 pa, int32 access)\r |
| 464 | {\r |
| 465 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 466 | \r |
| 467 | case 015: /* PIRQ */\r |
| 468 | ODD_WO (data);\r |
| 469 | put_PIRQ (data);\r |
| 470 | return SCPE_OK;\r |
| 471 | \r |
| 472 | case 016: /* STKLIM */\r |
| 473 | ODD_WO (data);\r |
| 474 | STKLIM = data & STKLIM_RW;\r |
| 475 | return SCPE_OK;\r |
| 476 | } /* end switch pa */\r |
| 477 | \r |
| 478 | return SCPE_NXM; /* unimplemented */\r |
| 479 | }\r |
| 480 | \r |
| 481 | /* CPU control registers - 11/60 */\r |
| 482 | \r |
| 483 | t_stat CPU60_rd (int32 *data, int32 pa, int32 access)\r |
| 484 | {\r |
| 485 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 486 | \r |
| 487 | case 000: /* WCS */\r |
| 488 | *data = WCS & WCS60_RD;\r |
| 489 | return SCPE_OK;\r |
| 490 | \r |
| 491 | case 002: /* MEMERR */\r |
| 492 | *data = MEMERR & MEME60_RD;\r |
| 493 | return SCPE_OK;\r |
| 494 | \r |
| 495 | case 003: /* CCR */\r |
| 496 | *data = CCR & CCR60_RD;\r |
| 497 | return SCPE_OK;\r |
| 498 | \r |
| 499 | case 005: /* Hit/miss */\r |
| 500 | *data = HITMISS;\r |
| 501 | return SCPE_OK;\r |
| 502 | \r |
| 503 | case 013: /* CPUERR */\r |
| 504 | if (CPUERR & CPUE_NXM) /* TMO only */\r |
| 505 | CPUERR = (CPUERR & ~CPUE_NXM) | CPUE_TMO;\r |
| 506 | *data = CPUERR & CPUE60_RD;\r |
| 507 | return SCPE_OK;\r |
| 508 | \r |
| 509 | case 016: /* STKLIM */\r |
| 510 | *data = STKLIM & STKLIM_RW;\r |
| 511 | return SCPE_OK;\r |
| 512 | } /* end switch PA */\r |
| 513 | \r |
| 514 | *data = 0;\r |
| 515 | return SCPE_NXM; /* unimplemented */\r |
| 516 | }\r |
| 517 | \r |
| 518 | t_stat CPU60_wr (int32 data, int32 pa, int32 access)\r |
| 519 | {\r |
| 520 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 521 | \r |
| 522 | case 000: /* WCS */\r |
| 523 | WCS = data & WCS60_WR;\r |
| 524 | return SCPE_OK;\r |
| 525 | \r |
| 526 | case 002: /* MEMERR */\r |
| 527 | MEMERR = 0;\r |
| 528 | return SCPE_OK;\r |
| 529 | \r |
| 530 | case 003: /* CCR */\r |
| 531 | ODD_IGN (data);\r |
| 532 | CCR = data & CCR60_WR;\r |
| 533 | return SCPE_OK;\r |
| 534 | \r |
| 535 | case 005: /* Hit/miss */\r |
| 536 | return SCPE_OK;\r |
| 537 | \r |
| 538 | case 013: /* CPUERR */\r |
| 539 | CPUERR = 0;\r |
| 540 | return SCPE_OK;\r |
| 541 | \r |
| 542 | case 014: /* MBRK */\r |
| 543 | MBRK = data & MBRK60_WR;\r |
| 544 | return SCPE_OK;\r |
| 545 | \r |
| 546 | case 016: /* STKLIM */\r |
| 547 | ODD_WO (data);\r |
| 548 | STKLIM = data & STKLIM_RW;\r |
| 549 | return SCPE_OK;\r |
| 550 | } /* end switch pa */\r |
| 551 | \r |
| 552 | return SCPE_NXM; /* unimplemented */\r |
| 553 | }\r |
| 554 | \r |
| 555 | /* CPU control registers - 11/70 */\r |
| 556 | \r |
| 557 | t_stat CPU70_rd (int32 *data, int32 pa, int32 access)\r |
| 558 | {\r |
| 559 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 560 | \r |
| 561 | case 000: /* low error */\r |
| 562 | *data = 0;\r |
| 563 | return SCPE_OK;\r |
| 564 | \r |
| 565 | case 001: /* high error */\r |
| 566 | *data = 0;\r |
| 567 | return SCPE_OK;\r |
| 568 | \r |
| 569 | case 002: /* MEMERR */\r |
| 570 | *data = MEMERR;\r |
| 571 | return SCPE_OK;\r |
| 572 | \r |
| 573 | case 003: /* CCR */\r |
| 574 | *data = CCR;\r |
| 575 | return SCPE_OK;\r |
| 576 | \r |
| 577 | case 004: /* MAINT */\r |
| 578 | *data = 0;\r |
| 579 | return SCPE_OK;\r |
| 580 | \r |
| 581 | case 005: /* Hit/miss */\r |
| 582 | *data = HITMISS;\r |
| 583 | return SCPE_OK;\r |
| 584 | \r |
| 585 | case 010: /* low size */\r |
| 586 | *data = (MEMSIZE >> 6) - 1;\r |
| 587 | return SCPE_OK;\r |
| 588 | \r |
| 589 | case 011: /* high size */\r |
| 590 | *data = 0;\r |
| 591 | return SCPE_OK;\r |
| 592 | \r |
| 593 | case 012: /* system ID */\r |
| 594 | *data = SYSID;\r |
| 595 | return SCPE_OK;\r |
| 596 | \r |
| 597 | case 013: /* CPUERR */\r |
| 598 | *data = CPUERR & CPUE_IMP;\r |
| 599 | return SCPE_OK;\r |
| 600 | \r |
| 601 | case 014: /* MBRK */\r |
| 602 | *data = MBRK;\r |
| 603 | return SCPE_OK;\r |
| 604 | \r |
| 605 | case 015: /* PIRQ */\r |
| 606 | *data = PIRQ;\r |
| 607 | return SCPE_OK;\r |
| 608 | \r |
| 609 | case 016: /* STKLIM */\r |
| 610 | *data = STKLIM & STKLIM_RW;\r |
| 611 | return SCPE_OK;\r |
| 612 | } /* end switch PA */\r |
| 613 | \r |
| 614 | *data = 0;\r |
| 615 | return SCPE_NXM; /* unimplemented */\r |
| 616 | }\r |
| 617 | \r |
| 618 | t_stat CPU70_wr (int32 data, int32 pa, int32 access)\r |
| 619 | {\r |
| 620 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 621 | \r |
| 622 | case 002: /* MEMERR */\r |
| 623 | ODD_WO (data);\r |
| 624 | MEMERR = MEMERR & ~data;\r |
| 625 | return SCPE_OK;\r |
| 626 | \r |
| 627 | case 003: /* CCR */\r |
| 628 | ODD_MRG (CCR, data);\r |
| 629 | CCR = data;\r |
| 630 | return SCPE_OK;\r |
| 631 | \r |
| 632 | case 004: /* MAINT */\r |
| 633 | return SCPE_OK;\r |
| 634 | \r |
| 635 | case 005: /* Hit/miss */\r |
| 636 | return SCPE_OK;\r |
| 637 | \r |
| 638 | case 010: /* low size */\r |
| 639 | return SCPE_OK;\r |
| 640 | \r |
| 641 | case 011: /* high size */\r |
| 642 | return SCPE_OK;\r |
| 643 | \r |
| 644 | case 013: /* CPUERR */\r |
| 645 | CPUERR = 0;\r |
| 646 | return SCPE_OK;\r |
| 647 | \r |
| 648 | case 014: /* MBRK */\r |
| 649 | ODD_IGN (data);\r |
| 650 | MBRK = data & MBRK70_WR;\r |
| 651 | return SCPE_OK;\r |
| 652 | \r |
| 653 | case 015: /* PIRQ */\r |
| 654 | ODD_WO (data);\r |
| 655 | put_PIRQ (data);\r |
| 656 | return SCPE_OK;\r |
| 657 | \r |
| 658 | case 016: /* STKLIM */\r |
| 659 | ODD_WO (data);\r |
| 660 | STKLIM = data & STKLIM_RW;\r |
| 661 | return SCPE_OK;\r |
| 662 | } /* end switch pa */\r |
| 663 | \r |
| 664 | return SCPE_NXM; /* unimplemented */\r |
| 665 | }\r |
| 666 | \r |
| 667 | /* CPU control registers - J11 */\r |
| 668 | \r |
| 669 | t_stat CPUJ_rd (int32 *data, int32 pa, int32 access)\r |
| 670 | {\r |
| 671 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 672 | \r |
| 673 | case 002: /* MEMERR */\r |
| 674 | *data = MEMERR;\r |
| 675 | return SCPE_OK;\r |
| 676 | \r |
| 677 | case 003: /* CCR */\r |
| 678 | *data = CCR;\r |
| 679 | return SCPE_OK;\r |
| 680 | \r |
| 681 | case 004: /* MAINT */\r |
| 682 | *data = MAINT | MAINT_NOFPA | MAINT_BPOK | (UNIBUS? MAINT_U: MAINT_Q);\r |
| 683 | if (CPUT (CPUT_53)) *data |= MAINT_KDJD | MAINT_POROM;\r |
| 684 | if (CPUT (CPUT_73)) *data |= MAINT_KDJA | MAINT_POODT;\r |
| 685 | if (CPUT (CPUT_73B|CPUT_83|CPUT_84)) *data |= MAINT_KDJB | MAINT_POROM;\r |
| 686 | if (CPUT (CPUT_93|CPUT_94)) *data |= MAINT_KDJE | MAINT_POROM;\r |
| 687 | return SCPE_OK;\r |
| 688 | \r |
| 689 | case 005: /* Hit/miss */\r |
| 690 | if (CPUT (CPUT_73B)) *data = 0; /* must be 0 for 73B */\r |
| 691 | else *data = HITMISS | 010; /* must be nz for 11/8X */\r |
| 692 | return SCPE_OK;\r |
| 693 | \r |
| 694 | case 013: /* CPUERR */\r |
| 695 | *data = CPUERR & CPUE_IMP;\r |
| 696 | return SCPE_OK;\r |
| 697 | \r |
| 698 | case 015: /* PIRQ */\r |
| 699 | *data = PIRQ;\r |
| 700 | return SCPE_OK;\r |
| 701 | } /* end switch PA */\r |
| 702 | \r |
| 703 | *data = 0;\r |
| 704 | return SCPE_NXM; /* unimplemented */\r |
| 705 | }\r |
| 706 | \r |
| 707 | t_stat CPUJ_wr (int32 data, int32 pa, int32 access)\r |
| 708 | {\r |
| 709 | switch ((pa >> 1) & 017) { /* decode pa<4:1> */\r |
| 710 | \r |
| 711 | case 002: /* MEMERR */\r |
| 712 | MEMERR = 0;\r |
| 713 | return SCPE_OK;\r |
| 714 | \r |
| 715 | case 003: /* CCR */\r |
| 716 | ODD_MRG (CCR, data);\r |
| 717 | CCR = data;\r |
| 718 | return SCPE_OK;\r |
| 719 | \r |
| 720 | case 004: /* MAINT */\r |
| 721 | return SCPE_OK;\r |
| 722 | \r |
| 723 | case 005: /* Hit/miss */\r |
| 724 | return SCPE_OK;\r |
| 725 | \r |
| 726 | case 013: /* CPUERR */\r |
| 727 | CPUERR = 0;\r |
| 728 | return SCPE_OK;\r |
| 729 | \r |
| 730 | case 015: /* PIRQ */\r |
| 731 | ODD_WO (data);\r |
| 732 | put_PIRQ (data);\r |
| 733 | return SCPE_OK;\r |
| 734 | } /* end switch pa */\r |
| 735 | \r |
| 736 | return SCPE_NXM; /* unimplemented */\r |
| 737 | }\r |
| 738 | \r |
| 739 | /* Board control registers - KDF11B */\r |
| 740 | \r |
| 741 | t_stat CTLFB_rd (int32 *data, int32 pa, int32 access)\r |
| 742 | {\r |
| 743 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 744 | \r |
| 745 | case 0: /* PCR */\r |
| 746 | *data = JPCR & PCRFB_RW;\r |
| 747 | return SCPE_OK;\r |
| 748 | \r |
| 749 | case 1: /* MAINT */\r |
| 750 | *data = MAINT;\r |
| 751 | return SCPE_OK;\r |
| 752 | \r |
| 753 | case 2: /* CDR */\r |
| 754 | *data = SR & CDRFB_RD;\r |
| 755 | return SCPE_OK;\r |
| 756 | }\r |
| 757 | \r |
| 758 | *data = 0;\r |
| 759 | return SCPE_NXM;\r |
| 760 | }\r |
| 761 | \r |
| 762 | t_stat CTLFB_wr (int32 data, int32 pa, int32 access)\r |
| 763 | {\r |
| 764 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 765 | \r |
| 766 | case 0: /* PCR */\r |
| 767 | ODD_MRG (JPCR, data);\r |
| 768 | JPCR = data & PCRFB_RW;\r |
| 769 | return SCPE_OK;\r |
| 770 | case 1: /* MAINT */\r |
| 771 | ODD_MRG (MAINT, data);\r |
| 772 | MAINT = data;\r |
| 773 | return SCPE_OK;\r |
| 774 | case 2: /* CDR */\r |
| 775 | ODD_WO (data);\r |
| 776 | DR = data & CDRFB_WR;\r |
| 777 | return SCPE_OK;\r |
| 778 | }\r |
| 779 | \r |
| 780 | return SCPE_NXM;\r |
| 781 | }\r |
| 782 | \r |
| 783 | /* Board control registers - KDJ11B */\r |
| 784 | \r |
| 785 | t_stat CTLJB_rd (int32 *data, int32 pa, int32 access)\r |
| 786 | {\r |
| 787 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 788 | \r |
| 789 | case 0: /* CSR */\r |
| 790 | *data = JCSR & CSRJB_RD;\r |
| 791 | return SCPE_OK;\r |
| 792 | \r |
| 793 | case 1: /* PCR */\r |
| 794 | *data = JPCR & PCRJB_RW;\r |
| 795 | return SCPE_OK;\r |
| 796 | \r |
| 797 | case 2: /* CDR */\r |
| 798 | *data = SR & CDRJB_RD;\r |
| 799 | return SCPE_OK;\r |
| 800 | }\r |
| 801 | \r |
| 802 | *data = 0;\r |
| 803 | return SCPE_NXM;\r |
| 804 | }\r |
| 805 | \r |
| 806 | t_stat CTLJB_wr (int32 data, int32 pa, int32 access)\r |
| 807 | {\r |
| 808 | int32 t;\r |
| 809 | \r |
| 810 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 811 | \r |
| 812 | case 0: /* CSR */\r |
| 813 | ODD_MRG (JCSR, data);\r |
| 814 | JCSR = (JCSR & ~CSRJB_WR) | (data & CSRJB_WR);\r |
| 815 | if (JCSR & CSRJ_LTCI) clk_fie = 1; /* force LTC int enb? */\r |
| 816 | else clk_fie = 0;\r |
| 817 | if (JCSR & CSRJ_LTCD) clk_fnxm = 1; /* force LTC reg nxm? */\r |
| 818 | else clk_fnxm = 0;\r |
| 819 | t = CSRJ_LTCSEL (JCSR); /* get freq sel */\r |
| 820 | if (t) clk_tps = clk_tps_map[t];\r |
| 821 | else clk_tps = clk_default;\r |
| 822 | return SCPE_OK;\r |
| 823 | \r |
| 824 | case 1: /* PCR */\r |
| 825 | ODD_MRG (JPCR, data);\r |
| 826 | JPCR = data & PCRJB_RW;\r |
| 827 | return SCPE_OK;\r |
| 828 | \r |
| 829 | case 2: /* CDR */\r |
| 830 | ODD_WO (data);\r |
| 831 | DR = data & CDRJB_WR;\r |
| 832 | return SCPE_OK;\r |
| 833 | }\r |
| 834 | \r |
| 835 | return SCPE_NXM;\r |
| 836 | }\r |
| 837 | \r |
| 838 | /* Board control registers - KDJ11D */\r |
| 839 | \r |
| 840 | t_stat CTLJD_rd (int32 *data, int32 pa, int32 access)\r |
| 841 | {\r |
| 842 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 843 | \r |
| 844 | case 0: /* CSR */\r |
| 845 | *data = JCSR & CSRJD_RD;\r |
| 846 | return SCPE_OK;\r |
| 847 | }\r |
| 848 | \r |
| 849 | *data = 0;\r |
| 850 | return SCPE_NXM;\r |
| 851 | }\r |
| 852 | \r |
| 853 | t_stat CTLJD_wr (int32 data, int32 pa, int32 access)\r |
| 854 | {\r |
| 855 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 856 | \r |
| 857 | case 0: /* CSR */\r |
| 858 | ODD_MRG (JCSR, data);\r |
| 859 | JCSR = (JCSR & ~CSRJD_WR) | (data & CSRJD_WR);\r |
| 860 | return SCPE_OK;\r |
| 861 | }\r |
| 862 | \r |
| 863 | return SCPE_NXM;\r |
| 864 | }\r |
| 865 | \r |
| 866 | /* Board control registers - KDJ11E */\r |
| 867 | \r |
| 868 | t_stat CTLJE_rd (int32 *data, int32 pa, int32 access)\r |
| 869 | {\r |
| 870 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 871 | \r |
| 872 | case 0: /* CSR */\r |
| 873 | *data = JCSR & CSRJE_RD;\r |
| 874 | return SCPE_OK;\r |
| 875 | \r |
| 876 | case 1: /* PCR */\r |
| 877 | *data = JPCR & PCRJE_RW;\r |
| 878 | return SCPE_OK;\r |
| 879 | \r |
| 880 | case 2: /* CDR */\r |
| 881 | *data = SR & CDRJE_RD;\r |
| 882 | return SCPE_OK;\r |
| 883 | \r |
| 884 | case 3: /* ASR */\r |
| 885 | JASR = (JASR & ~ASRJE_TOY) | (toy_read () << ASRJE_V_TOY);\r |
| 886 | *data = JASR & ASRJE_RW; \r |
| 887 | return SCPE_OK;\r |
| 888 | }\r |
| 889 | \r |
| 890 | *data = 0;\r |
| 891 | return SCPE_NXM;\r |
| 892 | }\r |
| 893 | \r |
| 894 | t_stat CTLJE_wr (int32 data, int32 pa, int32 access)\r |
| 895 | {\r |
| 896 | int32 t;\r |
| 897 | \r |
| 898 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 899 | \r |
| 900 | case 0: /* CSR */\r |
| 901 | ODD_MRG (JCSR, data);\r |
| 902 | JCSR = (JCSR & ~CSRJE_WR) | (data & CSRJE_WR);\r |
| 903 | if (JCSR & CSRJ_LTCI) clk_fie = 1; /* force LTC int enb? */\r |
| 904 | else clk_fie = 0;\r |
| 905 | if (JCSR & CSRJ_LTCD) clk_fnxm = 1; /* force LTC reg nxm? */\r |
| 906 | else clk_fnxm = 0;\r |
| 907 | t = CSRJ_LTCSEL (JCSR); /* get freq sel */\r |
| 908 | if (t) clk_tps = clk_tps_map[t];\r |
| 909 | else clk_tps = clk_default;\r |
| 910 | return SCPE_OK;\r |
| 911 | \r |
| 912 | case 1: /* PCR */\r |
| 913 | ODD_MRG (JPCR, data);\r |
| 914 | JPCR = data & PCRJE_RW;\r |
| 915 | return SCPE_OK;\r |
| 916 | \r |
| 917 | case 2: /* CDR */\r |
| 918 | ODD_WO (data);\r |
| 919 | DR = data & CDRJE_WR;\r |
| 920 | return SCPE_OK;\r |
| 921 | \r |
| 922 | case 3: /* ASR */\r |
| 923 | ODD_MRG (JASR, data);\r |
| 924 | JASR = data & ASRJE_RW;\r |
| 925 | toy_write (ASRJE_TOYBIT (JASR));\r |
| 926 | return SCPE_OK;\r |
| 927 | }\r |
| 928 | \r |
| 929 | return SCPE_NXM;\r |
| 930 | }\r |
| 931 | \r |
| 932 | /* Unibus adapter registers - KT24 */\r |
| 933 | \r |
| 934 | t_stat UBA24_rd (int32 *data, int32 pa, int32 access)\r |
| 935 | {\r |
| 936 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 937 | \r |
| 938 | case 2: /* LMAL */\r |
| 939 | *data = uba_last & LMAL_RD;\r |
| 940 | return SCPE_OK;\r |
| 941 | case 3: /* LMAH */\r |
| 942 | *data = uba_last & LMAH_RD;\r |
| 943 | return SCPE_OK;\r |
| 944 | }\r |
| 945 | \r |
| 946 | *data = 0;\r |
| 947 | return SCPE_NXM;\r |
| 948 | }\r |
| 949 | \r |
| 950 | t_stat UBA24_wr (int32 data, int32 pa, int32 access)\r |
| 951 | {\r |
| 952 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 953 | \r |
| 954 | case 3: /* ASR */\r |
| 955 | ODD_IGN (data);\r |
| 956 | uba_last = (uba_last & ~LMAH_WR) | ((data & LMAH_WR) << 16);\r |
| 957 | return SCPE_OK;\r |
| 958 | }\r |
| 959 | \r |
| 960 | return SCPE_NXM;\r |
| 961 | }\r |
| 962 | \r |
| 963 | /* Unibus registers - KTJ11B */\r |
| 964 | \r |
| 965 | t_stat UBAJ_rd (int32 *data, int32 pa, int32 access)\r |
| 966 | {\r |
| 967 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 968 | \r |
| 969 | case 0: /* DCR */\r |
| 970 | *data = UDCR & DCRKTJ_RD;\r |
| 971 | return SCPE_OK;\r |
| 972 | \r |
| 973 | case 1: /* DDR */\r |
| 974 | *data = UDDR & DDRKTJ_RW;\r |
| 975 | return SCPE_OK;\r |
| 976 | \r |
| 977 | case 2: /* CSR */\r |
| 978 | *data = UCSR & MCRKTJ_RD;\r |
| 979 | return SCPE_OK;\r |
| 980 | }\r |
| 981 | \r |
| 982 | *data = 0;\r |
| 983 | return SCPE_NXM;\r |
| 984 | }\r |
| 985 | \r |
| 986 | t_stat UBAJ_wr (int32 data, int32 pa, int32 access)\r |
| 987 | {\r |
| 988 | switch ((pa >> 1) & 03) { /* decode pa<2:1> */\r |
| 989 | \r |
| 990 | case 0: /* DCR */\r |
| 991 | ODD_MRG (UDCR, data);\r |
| 992 | UDCR = (UDCR & ~DCRKTJ_WR) | (data & DCRKTJ_WR);\r |
| 993 | return SCPE_OK;\r |
| 994 | \r |
| 995 | case 1: /* DDR */\r |
| 996 | ODD_MRG (UDDR, data);\r |
| 997 | UDDR = data & DDRKTJ_RW;;\r |
| 998 | return SCPE_OK;\r |
| 999 | \r |
| 1000 | case 2: /* CSR */\r |
| 1001 | ODD_MRG (UCSR, data);\r |
| 1002 | UCSR = (UCSR & ~MCRKTJ_WR) | (data & MCRKTJ_WR);\r |
| 1003 | return SCPE_OK;\r |
| 1004 | }\r |
| 1005 | \r |
| 1006 | return SCPE_NXM;\r |
| 1007 | }\r |
| 1008 | \r |
| 1009 | /* KDJ11E TOY routines */\r |
| 1010 | \r |
| 1011 | int32 toy_read (void)\r |
| 1012 | {\r |
| 1013 | time_t curr;\r |
| 1014 | struct tm *ctm;\r |
| 1015 | int32 bit;\r |
| 1016 | \r |
| 1017 | if (toy_state == 0) {\r |
| 1018 | curr = time (NULL); /* get curr time */\r |
| 1019 | if (curr == (time_t) -1) return 0; /* error? */\r |
| 1020 | ctm = localtime (&curr); /* decompose */\r |
| 1021 | if (ctm == NULL) return 0; /* error? */\r |
| 1022 | toy_data[TOY_HSEC] = 0x50;\r |
| 1023 | toy_data[TOY_SEC] = toy_set (ctm->tm_sec);\r |
| 1024 | toy_data[TOY_MIN] = toy_set (ctm->tm_min);\r |
| 1025 | toy_data[TOY_HR] = toy_set (ctm->tm_hour);\r |
| 1026 | toy_data[TOY_DOW] = toy_set (ctm->tm_wday);\r |
| 1027 | toy_data[TOY_DOM] = toy_set (ctm->tm_mday);\r |
| 1028 | toy_data[TOY_MON] = toy_set (ctm->tm_mon + 1);\r |
| 1029 | toy_data[TOY_YR] = toy_set (ctm->tm_year % 100);\r |
| 1030 | }\r |
| 1031 | bit = toy_data[toy_state >> 3] >> (toy_state & 07);\r |
| 1032 | toy_state = (toy_state + 1) % (TOY_LNT * 8);\r |
| 1033 | return (bit & 1);\r |
| 1034 | }\r |
| 1035 | \r |
| 1036 | void toy_write (int32 bit)\r |
| 1037 | {\r |
| 1038 | toy_state = 0;\r |
| 1039 | return;\r |
| 1040 | }\r |
| 1041 | \r |
| 1042 | uint8 toy_set (int32 val)\r |
| 1043 | {\r |
| 1044 | uint32 d1, d2;\r |
| 1045 | \r |
| 1046 | d1 = val / 10;\r |
| 1047 | d2 = val % 10;\r |
| 1048 | return (uint8) ((d1 << 4) | d2);\r |
| 1049 | }\r |
| 1050 | \r |
| 1051 | /* Build I/O space entries for CPU */\r |
| 1052 | \r |
| 1053 | t_stat cpu_build_dib (void)\r |
| 1054 | {\r |
| 1055 | int32 i;\r |
| 1056 | t_stat r;\r |
| 1057 | \r |
| 1058 | for (i = 0; cnf_tab[i].dib != NULL; i++) { /* loop thru config tab */\r |
| 1059 | if (((cnf_tab[i].cpum == 0) || (cpu_type & cnf_tab[i].cpum)) &&\r |
| 1060 | ((cnf_tab[i].optm == 0) || (cpu_opt & cnf_tab[i].optm))) {\r |
| 1061 | if (r = build_ubus_tab (&cpu_dev, cnf_tab[i].dib)) /* add to dispatch tab */\r |
| 1062 | return r;\r |
| 1063 | }\r |
| 1064 | }\r |
| 1065 | return SCPE_OK;\r |
| 1066 | }\r |
| 1067 | \r |
| 1068 | /* Set/show CPU model */\r |
| 1069 | \r |
| 1070 | t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc)\r |
| 1071 | {\r |
| 1072 | if (cptr != NULL) return SCPE_ARG;\r |
| 1073 | if (val >= MOD_MAX) return SCPE_IERR;\r |
| 1074 | if (val == (int32) cpu_model) return SCPE_OK;\r |
| 1075 | if (MEMSIZE > cpu_tab[val].maxm)\r |
| 1076 | cpu_set_size (uptr, cpu_tab[val].maxm, NULL, NULL);\r |
| 1077 | if (MEMSIZE > cpu_tab[val].maxm) return SCPE_INCOMP;\r |
| 1078 | cpu_model = val;\r |
| 1079 | cpu_type = 1u << cpu_model;\r |
| 1080 | cpu_opt = cpu_tab[cpu_model].std;\r |
| 1081 | cpu_set_bus (cpu_opt);\r |
| 1082 | reset_all (0); /* reset world */\r |
| 1083 | return SCPE_OK;\r |
| 1084 | }\r |
| 1085 | \r |
| 1086 | t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc)\r |
| 1087 | {\r |
| 1088 | uint32 i, all_opt;\r |
| 1089 | \r |
| 1090 | fprintf (st, "%s", cpu_tab[cpu_model].name);\r |
| 1091 | all_opt = cpu_tab[cpu_model].opt;\r |
| 1092 | for (i = 0; opt_name[2 * i] != NULL; i++) {\r |
| 1093 | if ((all_opt >> i) & 1) fprintf (st, ", %s",\r |
| 1094 | ((cpu_opt >> i) & 1)? opt_name[2 * i]: opt_name[(2 * i) + 1]);\r |
| 1095 | } \r |
| 1096 | return SCPE_OK;\r |
| 1097 | }\r |
| 1098 | \r |
| 1099 | /* Set/clear CPU option */\r |
| 1100 | \r |
| 1101 | t_stat cpu_set_opt (UNIT *uptr, int32 val, char *cptr, void *desc)\r |
| 1102 | {\r |
| 1103 | if (cptr) return SCPE_ARG;\r |
| 1104 | if ((val & cpu_tab[cpu_model].opt) == 0) return SCPE_ARG;\r |
| 1105 | cpu_opt = cpu_opt | val;\r |
| 1106 | return SCPE_OK;\r |
| 1107 | }\r |
| 1108 | \r |
| 1109 | t_stat cpu_clr_opt (UNIT *uptr, int32 val, char *cptr, void *desc)\r |
| 1110 | {\r |
| 1111 | if (cptr) return SCPE_ARG;\r |
| 1112 | if ((val & cpu_tab[cpu_model].opt) == 0) return SCPE_ARG;\r |
| 1113 | cpu_opt = cpu_opt & ~val;\r |
| 1114 | return SCPE_OK;\r |
| 1115 | }\r |
| 1116 | \r |
| 1117 | /* Memory allocation */\r |
| 1118 | \r |
| 1119 | t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)\r |
| 1120 | {\r |
| 1121 | int32 mc = 0;\r |
| 1122 | uint32 i, clim;\r |
| 1123 | uint16 *nM;\r |
| 1124 | \r |
| 1125 | if ((val <= 0) || (val > (int32) cpu_tab[cpu_model].maxm) ||\r |
| 1126 | ((val & 07777) != 0)) return SCPE_ARG;\r |
| 1127 | for (i = val; i < MEMSIZE; i = i + 2) mc = mc | M[i >> 1];\r |
| 1128 | if ((mc != 0) && !get_yn ("Really truncate memory [N]?", FALSE))\r |
| 1129 | return SCPE_OK;\r |
| 1130 | nM = (uint16 *) calloc (val >> 1, sizeof (uint16));\r |
| 1131 | if (nM == NULL) return SCPE_MEM;\r |
| 1132 | clim = (((t_addr) val) < MEMSIZE)? val: MEMSIZE;\r |
| 1133 | for (i = 0; i < clim; i = i + 2) nM[i >> 1] = M[i >> 1];\r |
| 1134 | free (M);\r |
| 1135 | M = nM;\r |
| 1136 | MEMSIZE = val;\r |
| 1137 | if (!(sim_switches & SIM_SW_REST)) /* unless restore, */\r |
| 1138 | cpu_set_bus (cpu_opt); /* alter periph config */\r |
| 1139 | return SCPE_OK;\r |
| 1140 | }\r |
| 1141 | \r |
| 1142 | /* Bus configuration, disable Unibus or Qbus devices */\r |
| 1143 | \r |
| 1144 | t_stat cpu_set_bus (int32 opt)\r |
| 1145 | {\r |
| 1146 | DEVICE *dptr;\r |
| 1147 | uint32 i, mask;\r |
| 1148 | \r |
| 1149 | if (opt & BUS_U) mask = DEV_UBUS; /* Unibus variant? */\r |
| 1150 | else if (MEMSIZE <= UNIMEMSIZE) /* 18b Qbus devices? */\r |
| 1151 | mask = DEV_QBUS | DEV_Q18;\r |
| 1152 | else mask = DEV_QBUS; /* must be 22b */\r |
| 1153 | for (i = 0; (dptr = sim_devices[i]) != NULL; i++) {\r |
| 1154 | if ((dptr->flags & DEV_DISABLE) && /* disable-able? */\r |
| 1155 | !(dptr->flags & DEV_DIS) && /* enabled? */\r |
| 1156 | ((dptr->flags & mask) == 0)) { /* not allowed? */\r |
| 1157 | printf ("Disabling %s\n", sim_dname (dptr));\r |
| 1158 | if (sim_log) fprintf (sim_log, "Disabling %s\n", sim_dname (dptr));\r |
| 1159 | dptr->flags = dptr->flags | DEV_DIS;\r |
| 1160 | }\r |
| 1161 | }\r |
| 1162 | return SCPE_OK;\r |
| 1163 | }\r |
| 1164 | \r |
| 1165 | /* System reset */\r |
| 1166 | \r |
| 1167 | t_stat sys_reset (DEVICE *dptr)\r |
| 1168 | {\r |
| 1169 | int32 i;\r |
| 1170 | \r |
| 1171 | CCR = 0;\r |
| 1172 | HITMISS = 0;\r |
| 1173 | CPUERR = 0;\r |
| 1174 | MEMERR = 0;\r |
| 1175 | if (!CPUT (CPUT_J)) MAINT = 0;\r |
| 1176 | MBRK = 0;\r |
| 1177 | WCS = 0;\r |
| 1178 | if (CPUT (CPUT_JB|CPUT_JE))\r |
| 1179 | JCSR = JCSR_dflt;\r |
| 1180 | else JCSR = 0;\r |
| 1181 | JPCR = 0;\r |
| 1182 | JASR = 0;\r |
| 1183 | UDCR = 0;\r |
| 1184 | UDDR = 0;\r |
| 1185 | UCSR = 0;\r |
| 1186 | uba_last = 0;\r |
| 1187 | DR = 0;\r |
| 1188 | toy_state = 0;\r |
| 1189 | for (i = 0; i < UBM_LNT_LW; i++) ub_map[i] = 0;\r |
| 1190 | for (i = 0; i < TOY_LNT; i++) toy_data[i] = 0;\r |
| 1191 | return SCPE_OK;\r |
| 1192 | }\r |
| 1193 | \r |
| 1194 | /* Set/show JCLK default values */\r |
| 1195 | \r |
| 1196 | t_stat sys_set_jclk_dflt (UNIT *uptr, int32 val, char *cptr, void *desc)\r |
| 1197 | {\r |
| 1198 | uint32 i;\r |
| 1199 | \r |
| 1200 | if ((CPUT (CPUT_JB|CPUT_JE)) && cptr) {\r |
| 1201 | for (i = 0; i < 4; i++) {\r |
| 1202 | if (strncmp (cptr, jcsr_val[i], strlen (cptr)) == 0) {\r |
| 1203 | JCSR_dflt = i << CSRJ_V_LTCSEL;\r |
| 1204 | return SCPE_OK;\r |
| 1205 | }\r |
| 1206 | }\r |
| 1207 | }\r |
| 1208 | return SCPE_ARG;\r |
| 1209 | }\r |
| 1210 | \r |
| 1211 | t_stat sys_show_jclk_dflt (FILE *st, UNIT *uptr, int32 val, void *desc)\r |
| 1212 | {\r |
| 1213 | if (CPUT (CPUT_JB|CPUT_JE))\r |
| 1214 | fprintf (st, "JCLK default=%s\n", jcsr_val[CSRJ_LTCSEL (JCSR_dflt)]);\r |
| 1215 | else fprintf (st, "Not implemented\n");\r |
| 1216 | return SCPE_OK;\r |
| 1217 | }\r |