| 1 | /* pdp11_cpumod.h: PDP-11 CPU model definitions\r |
| 2 | \r |
| 3 | Copyright (c) 2004-2008, Robert M Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | 22-Apr-08 RMS Added 11/70 MBRK register\r |
| 27 | 30-Aug-05 RMS Added additional 11/60 registers\r |
| 28 | */\r |
| 29 | \r |
| 30 | #ifndef _PDP11_CPUMOD_H_\r |
| 31 | #define _PDP11_CPUMOD_H_ 0\r |
| 32 | \r |
| 33 | #define SOP_1103 (BUS_Q)\r |
| 34 | #define OPT_1103 (OPT_EIS|OPT_FIS)\r |
| 35 | #define PSW_1103 0000377\r |
| 36 | \r |
| 37 | #define SOP_1104 (BUS_U)\r |
| 38 | #define OPT_1104 0\r |
| 39 | #define PSW_1104 0000377\r |
| 40 | \r |
| 41 | #define SOP_1105 (BUS_U)\r |
| 42 | #define OPT_1105 0\r |
| 43 | #define PSW_1105 0000377\r |
| 44 | \r |
| 45 | #define SOP_1120 (BUS_U)\r |
| 46 | #define OPT_1120 0\r |
| 47 | #define PSW_1120 0000377\r |
| 48 | \r |
| 49 | #define SOP_1123 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)\r |
| 50 | #define OPT_1123 (OPT_FPP|OPT_CIS)\r |
| 51 | #define PSW_F 0170777\r |
| 52 | #define PAR_F 0177777\r |
| 53 | #define PDR_F 0077516\r |
| 54 | #define MM0_F 0160157\r |
| 55 | #define MM3_F 0000060\r |
| 56 | \r |
| 57 | #define SOP_1123P (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)\r |
| 58 | #define OPT_1123P (OPT_FPP|OPT_CIS)\r |
| 59 | \r |
| 60 | #define SOP_1124 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM)\r |
| 61 | #define OPT_1124 (OPT_FPP|OPT_CIS)\r |
| 62 | \r |
| 63 | #define SOP_1134 (BUS_U|OPT_EIS|OPT_MMU)\r |
| 64 | #define OPT_1134 (OPT_FPP)\r |
| 65 | #define PSW_1134 0170377\r |
| 66 | #define PAR_1134 0007777\r |
| 67 | #define PDR_1134 0077516\r |
| 68 | #define MM0_1134 0160557\r |
| 69 | \r |
| 70 | #define SOP_1140 (BUS_U|OPT_EIS|OPT_MMU)\r |
| 71 | #define OPT_1140 (OPT_FIS)\r |
| 72 | #define PSW_1140 0170377\r |
| 73 | #define PAR_1140 0007777\r |
| 74 | #define PDR_1140 0077516\r |
| 75 | #define MM0_1140 0160557\r |
| 76 | \r |
| 77 | #define SOP_1144 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM)\r |
| 78 | #define OPT_1144 (OPT_FPP|OPT_CIS)\r |
| 79 | #define PSW_1144 0170777\r |
| 80 | #define PAR_1144 0177777\r |
| 81 | #define PDR_1144 0177516\r |
| 82 | #define MM0_1144 0160557\r |
| 83 | #define MM3_1144 0000077\r |
| 84 | \r |
| 85 | #define SOP_1145 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_RH11)\r |
| 86 | #define OPT_1145 (OPT_FPP)\r |
| 87 | #define PSW_1145 0174377\r |
| 88 | #define PAR_1145 0007777\r |
| 89 | #define PDR_1145 0077717\r |
| 90 | #define MM0_1145 0171777\r |
| 91 | #define MM3_1145 0000007\r |
| 92 | \r |
| 93 | #define SOP_1160 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU)\r |
| 94 | #define OPT_1160 0\r |
| 95 | #define PSW_1160 0170377\r |
| 96 | #define PAR_1160 0007777\r |
| 97 | #define PDR_1160 0077516\r |
| 98 | #define MM0_1160 0160557\r |
| 99 | \r |
| 100 | #define SOP_1170 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM)\r |
| 101 | #define OPT_1170 (OPT_FPP|OPT_RH11)\r |
| 102 | #define PSW_1170 0174377\r |
| 103 | #define PAR_1170 0177777\r |
| 104 | #define PDR_1170 0077717\r |
| 105 | #define MM0_1170 0171777\r |
| 106 | #define MM3_1170 0000067\r |
| 107 | \r |
| 108 | #define SOP_1173 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)\r |
| 109 | #define OPT_1173 (OPT_CIS)\r |
| 110 | #define PSW_J 0174777\r |
| 111 | #define PAR_J 0177777\r |
| 112 | #define PDR_J 0177516\r |
| 113 | #define MM0_J 0160177\r |
| 114 | #define MM3_J 0000077\r |
| 115 | \r |
| 116 | #define SOP_1153 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)\r |
| 117 | #define OPT_1153 (OPT_CIS)\r |
| 118 | \r |
| 119 | #define SOP_1173B (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)\r |
| 120 | #define OPT_1173B (OPT_CIS)\r |
| 121 | \r |
| 122 | #define SOP_1183 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)\r |
| 123 | #define OPT_1183 (OPT_CIS)\r |
| 124 | \r |
| 125 | #define SOP_1184 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM|OPT_RH11)\r |
| 126 | #define OPT_1184 (OPT_CIS)\r |
| 127 | \r |
| 128 | #define SOP_1193 (BUS_Q|OPT_EIS|OPT_FPP|OPT_MMU)\r |
| 129 | #define OPT_1193 (OPT_CIS)\r |
| 130 | \r |
| 131 | #define SOP_1194 (BUS_U|OPT_EIS|OPT_FPP|OPT_MMU|OPT_UBM|OPT_RH11)\r |
| 132 | #define OPT_1194 (OPT_CIS)\r |
| 133 | \r |
| 134 | #define MOD_MAX 20\r |
| 135 | \r |
| 136 | /* MFPT codes */\r |
| 137 | \r |
| 138 | #define MFPT_44 1\r |
| 139 | #define MFPT_F 3\r |
| 140 | #define MFPT_T 4\r |
| 141 | #define MFPT_J 5\r |
| 142 | \r |
| 143 | /* KDF11B specific register */\r |
| 144 | \r |
| 145 | #define PCRFB_RW 0037477 /* page ctrl reg */\r |
| 146 | \r |
| 147 | #define CDRFB_RD 0000377 /* config reg */\r |
| 148 | #define CDRFB_WR 0000017\r |
| 149 | \r |
| 150 | /* KT24 Unibus map specific registers */\r |
| 151 | \r |
| 152 | #define LMAL_RD 0177777 /* last mapped low */\r |
| 153 | \r |
| 154 | #define LMAH_RD 0000177 /* last mapped high */\r |
| 155 | #define LMAH_WR 0000100\r |
| 156 | \r |
| 157 | /* 11/44 specific registers */\r |
| 158 | \r |
| 159 | #define CCR44_RD 0033315 /* cache control */\r |
| 160 | #define CCR44_WR 0003315\r |
| 161 | \r |
| 162 | #define CMR44_RD 0177437 /* cache maint */\r |
| 163 | #define CMR44_WR 0000037\r |
| 164 | \r |
| 165 | #define CPUE44_BUSE 0004000\r |
| 166 | \r |
| 167 | /* 11/60 specific registers */\r |
| 168 | \r |
| 169 | #define WCS60_RD 0161776 /* WCS control */\r |
| 170 | #define WCS60_WR 0061676\r |
| 171 | \r |
| 172 | #define MEME60_RD 0100340 /* memory error */\r |
| 173 | \r |
| 174 | #define CCR60_RD 0000315 /* cache control */\r |
| 175 | #define CCR60_WR 0000115\r |
| 176 | \r |
| 177 | #define MBRK60_WR 0007777 /* microbreak */\r |
| 178 | \r |
| 179 | #define CPUE60_RD (CPUE_ODD|CPUE_TMO|CPUE_RED)\r |
| 180 | \r |
| 181 | /* 11/70 specific registers */\r |
| 182 | \r |
| 183 | #define MBRK70_WR 0000377 /* microbreak */\r |
| 184 | \r |
| 185 | /* J11 specific registers */\r |
| 186 | \r |
| 187 | /* Maintenance register */\r |
| 188 | \r |
| 189 | #define MAINT_V_UQ 9 /* Q/U flag */\r |
| 190 | #define MAINT_Q (0 << MAINT_V_UQ) /* Qbus */\r |
| 191 | #define MAINT_U (1 << MAINT_V_UQ)\r |
| 192 | #define MAINT_V_FPA 8 /* FPA flag */\r |
| 193 | #define MAINT_NOFPA (0 << MAINT_V_FPA)\r |
| 194 | #define MAINT_FPA (1 << MAINT_V_FPA)\r |
| 195 | #define MAINT_V_TYP 4 /* system type */\r |
| 196 | #define MAINT_KDJA (1 << MAINT_V_TYP) /* KDJ11A */\r |
| 197 | #define MAINT_KDJB (2 << MAINT_V_TYP) /* KDJ11B */\r |
| 198 | #define MAINT_KDJD (4 << MAINT_V_TYP) /* KDJ11D */\r |
| 199 | #define MAINT_KDJE (5 << MAINT_V_TYP) /* KDJ11E */\r |
| 200 | #define MAINT_V_HTRAP 3 /* trap 4 on HALT */\r |
| 201 | #define MAINT_HTRAP (1 << MAINT_V_HTRAP)\r |
| 202 | #define MAINT_V_POM 1 /* power on option */\r |
| 203 | #define MAINT_POODT (0 << MAINT_V_POM) /* power up ODT */\r |
| 204 | #define MAINT_POROM (2 << MAINT_V_POM) /* power up ROM */\r |
| 205 | #define MAINT_V_BPOK 0 /* power OK */\r |
| 206 | #define MAINT_BPOK (1 << MAINT_V_BPOK)\r |
| 207 | \r |
| 208 | /* KDJ11B control */\r |
| 209 | \r |
| 210 | #define CSRJB_RD 0177767\r |
| 211 | #define CSRJB_WR 0037767\r |
| 212 | #define CSRJ_LTCI 0020000 /* force LTC int */\r |
| 213 | #define CSRJ_LTCD 0010000 /* disable LTC reg */\r |
| 214 | #define CSRJ_V_LTCSEL 10\r |
| 215 | #define CSRJ_M_LTCSEL 03\r |
| 216 | #define CSRJ_LTCSEL(x) (((x) >> CSRJ_V_LTCSEL) & CSRJ_M_LTCSEL)\r |
| 217 | #define CSRJ_HBREAK 0001000 /* halt on break */\r |
| 218 | \r |
| 219 | #define PCRJB_RW 0077176 /* page ctrl reg */\r |
| 220 | \r |
| 221 | #define CDRJB_RD 0000377 /* config register */\r |
| 222 | #define CDRJB_WR 0000377\r |
| 223 | \r |
| 224 | /* KDJ11D control */\r |
| 225 | \r |
| 226 | #define CSRJD_RD 0157777 /* native register */\r |
| 227 | #define CSRJD_WR 0000377\r |
| 228 | #define CSRJD_15M 0040000 /* 1.5M mem on board */\r |
| 229 | \r |
| 230 | /* KDJ11E control */\r |
| 231 | \r |
| 232 | #define CSRJE_RD 0137360 /* control reg */\r |
| 233 | #define CSRJE_WR 0037370\r |
| 234 | \r |
| 235 | #define PCRJE_RW 0177376 /* page ctrl reg */\r |
| 236 | \r |
| 237 | #define CDRJE_RD 0000377 /* config register */\r |
| 238 | #define CDRJE_WR 0000077\r |
| 239 | \r |
| 240 | #define ASRJE_RW 0030462 /* additional status */\r |
| 241 | #define ASRJE_V_TOY 8\r |
| 242 | #define ASRJE_TOY (1u << ASRJE_V_TOY) /* TOY serial bit */\r |
| 243 | #define ASRJE_TOYBIT(x) (((x) >> ASRJE_V_TOY) & 1)\r |
| 244 | \r |
| 245 | /* KDJ11E TOY clock */\r |
| 246 | \r |
| 247 | #define TOY_HSEC 0\r |
| 248 | #define TOY_SEC 1\r |
| 249 | #define TOY_MIN 2\r |
| 250 | #define TOY_HR 3\r |
| 251 | #define TOY_DOW 4\r |
| 252 | #define TOY_DOM 5\r |
| 253 | #define TOY_MON 6\r |
| 254 | #define TOY_YR 7\r |
| 255 | #define TOY_LNT 8\r |
| 256 | \r |
| 257 | /* KTJ11B Unibus map */\r |
| 258 | \r |
| 259 | #define DCRKTJ_RD 0100616 /* diag control */\r |
| 260 | #define DCRKTJ_WR 0000416\r |
| 261 | \r |
| 262 | #define DDRKTJ_RW 0177777 /* diag data */\r |
| 263 | \r |
| 264 | #define MCRKTJ_RD 0000377 /* control register */\r |
| 265 | #define MCRKTJ_WR 0000177\r |
| 266 | \r |
| 267 | /* Data tables */\r |
| 268 | \r |
| 269 | struct cpu_table {\r |
| 270 | char *name; /* model name */\r |
| 271 | uint32 std; /* standard flags */\r |
| 272 | uint32 opt; /* set/clear flags */\r |
| 273 | uint32 maxm; /* max memory */\r |
| 274 | uint32 psw; /* PSW mask */\r |
| 275 | uint32 mfpt; /* MFPT code */\r |
| 276 | uint32 par; /* PAR mask */\r |
| 277 | uint32 pdr; /* PDR mask */\r |
| 278 | uint32 mm0; /* MMR0 mask */\r |
| 279 | uint32 mm3; /* MMR3 mask */\r |
| 280 | };\r |
| 281 | \r |
| 282 | typedef struct cpu_table CPUTAB;\r |
| 283 | \r |
| 284 | struct conf_table {\r |
| 285 | uint32 cpum;\r |
| 286 | uint32 optm;\r |
| 287 | DIB *dib;\r |
| 288 | };\r |
| 289 | \r |
| 290 | typedef struct conf_table CNFTAB;\r |
| 291 | \r |
| 292 | /* Prototypes */\r |
| 293 | \r |
| 294 | t_stat cpu_set_model (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 295 | t_stat cpu_show_model (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 296 | t_stat cpu_set_opt (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 297 | t_stat cpu_clr_opt (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 298 | t_stat cpu_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 299 | t_stat cpu_set_bus (int32 opt);\r |
| 300 | \r |
| 301 | #endif\r |