| 1 | /* pdp11_rc.c: RC11/RS64 fixed head disk simulator\r |
| 2 | \r |
| 3 | Copyright (c) 2007-2008, John A. Dundas III\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of the author shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from the author.\r |
| 25 | \r |
| 26 | rc RC11/RS64 fixed head disk\r |
| 27 | \r |
| 28 | 28-Dec-07 JAD Correct extraction of unit number from da in rc_svc.\r |
| 29 | Clear _all_ error bits when a new operation starts.\r |
| 30 | Passes all diagnostics in all configurations.\r |
| 31 | 25-Dec-07 JAD Compute the CRC-16 of the last sector read via\r |
| 32 | a READ or WCHK.\r |
| 33 | 20-Dec-07 JAD Correctly simulate rotation over the selected\r |
| 34 | track for RCLA. Also update the register\r |
| 35 | correctly during I/O operations.\r |
| 36 | Insure function activation time is non-zero.\r |
| 37 | Handle unit number wrap correctly.\r |
| 38 | 19-Dec-07 JAD Iterate over a full sector regardless of the\r |
| 39 | actual word count so that RCDA ends correctly.\r |
| 40 | Honor the read-only vs. read-write status of the\r |
| 41 | attached file.\r |
| 42 | 16-Dec-07 JAD The RCDA must be checked for validity when it is\r |
| 43 | written to, not just when GO is received.\r |
| 44 | 15-Dec-07 JAD Better handling of disk address errors and the RCLA\r |
| 45 | register.\r |
| 46 | Add more registers to the visible device state.\r |
| 47 | 07-Jan-07 JAD Initial creation and testing. Adapted from pdp11_rf.c.\r |
| 48 | \r |
| 49 | The RS64 is a head-per-track disk. To minimize overhead, the entire RC11\r |
| 50 | is buffered in memory. Up to 4 RS64 "platters" may be controlled by one\r |
| 51 | RC11 for a total of 262,144 words (65536kW/platter). [Later in time the\r |
| 52 | RK611 was assigned the same CSR address.]\r |
| 53 | \r |
| 54 | Diagnostic routines:\r |
| 55 | ZRCAB0.BIC - passes w/1-4 platters\r |
| 56 | ZRCBB0.BIC - passes w/1-4 platters\r |
| 57 | ZRCCB0.BIC - passes w/1-4 platters\r |
| 58 | Note that the diagnostics require R/W disks (i.e., will destroy any\r |
| 59 | existing data).\r |
| 60 | \r |
| 61 | For regression, must pass all three diagnostics configured for 1-4\r |
| 62 | platters for a total of 12 tests.\r |
| 63 | \r |
| 64 | Information necessary to create this simulation was gathered from the\r |
| 65 | PDP11 Peripherals Handbook, 1973-74 edition.\r |
| 66 | \r |
| 67 | One timing parameter is provided:\r |
| 68 | \r |
| 69 | rc_time Minimum I/O operation time, must be non-zero\r |
| 70 | */\r |
| 71 | \r |
| 72 | #if !defined (VM_PDP11)\r |
| 73 | #error "RC11 is not supported!"\r |
| 74 | #endif\r |
| 75 | #include "pdp11_defs.h"\r |
| 76 | #include <math.h>\r |
| 77 | \r |
| 78 | #define UNIT_V_AUTO (UNIT_V_UF + 0) /* autosize */\r |
| 79 | #define UNIT_V_PLAT (UNIT_V_UF + 1) /* #platters - 1 */\r |
| 80 | #define UNIT_M_PLAT 03\r |
| 81 | #define UNIT_GETP(x) ((((x) >> UNIT_V_PLAT) & UNIT_M_PLAT) + 1)\r |
| 82 | #define UNIT_AUTO (1 << UNIT_V_AUTO)\r |
| 83 | #define UNIT_PLAT (UNIT_M_PLAT << UNIT_V_PLAT)\r |
| 84 | \r |
| 85 | /* Constants */\r |
| 86 | \r |
| 87 | #define RC_NUMWD (32*64) /* words/track */\r |
| 88 | #define RC_NUMTR 32 /* tracks/disk */\r |
| 89 | #define RC_DKSIZE (RC_NUMTR * RC_NUMWD) /* words/disk */\r |
| 90 | #define RC_NUMDK 4 /* disks/controller */\r |
| 91 | #define RC_WMASK (RC_NUMWD - 1) /* word mask */\r |
| 92 | \r |
| 93 | /* Parameters in the unit descriptor */\r |
| 94 | \r |
| 95 | #define FUNC u4 /* function */\r |
| 96 | \r |
| 97 | /* Control and status register (RCCS) */\r |
| 98 | \r |
| 99 | #define RCCS_ERR (CSR_ERR) /* error */\r |
| 100 | #define RCCS_DATA 0040000 /* data error */\r |
| 101 | #define RCCS_ADDR 0020000 /* address error */\r |
| 102 | #define RCCS_WLK 0010000 /* write lock */\r |
| 103 | #define RCCS_NED 0004000 /* nx disk */\r |
| 104 | #define RCCS_WCHK 0002000 /* write check */\r |
| 105 | #define RCCS_INH 0001000 /* inhibit CA incr */\r |
| 106 | #define RCCS_ABO 0000400 /* abort */\r |
| 107 | #define RCCS_DONE (CSR_DONE)\r |
| 108 | #define RCCS_IE (CSR_IE)\r |
| 109 | #define RCCS_M_MEX 0000003 /* memory extension */\r |
| 110 | #define RCCS_V_MEX 4\r |
| 111 | #define RCCS_MEX (RCCS_M_MEX << RCCS_V_MEX)\r |
| 112 | #define RCCS_MAINT 0000010 /* maint */\r |
| 113 | #define RCCS_M_FUNC 0000003 /* function */\r |
| 114 | #define RFNC_LAH 0\r |
| 115 | #define RFNC_WRITE 1\r |
| 116 | #define RFNC_READ 2\r |
| 117 | #define RFNC_WCHK 3\r |
| 118 | #define RCCS_V_FUNC 1\r |
| 119 | #define RCCS_FUNC (RCCS_M_FUNC << RCCS_V_FUNC)\r |
| 120 | #define RCCS_GO 0000001\r |
| 121 | \r |
| 122 | #define RCCS_ALLERR (RCCS_DATA|RCCS_ADDR|RCCS_WLK|RCCS_NED|RCCS_WCHK)\r |
| 123 | #define RCCS_W (RCCS_INH | RCCS_ABO |RCCS_IE | RCCS_MEX | RCCS_MAINT | \\r |
| 124 | RCCS_FUNC | RCCS_GO)\r |
| 125 | \r |
| 126 | /* Disk error status register (RCER) */\r |
| 127 | \r |
| 128 | #define RCER_DLT 0100000 /* data late */\r |
| 129 | #define RCER_CHK 0040000 /* block check */\r |
| 130 | #define RCER_SYNC 0020000 /* data sync */\r |
| 131 | #define RCER_NXM 0010000 /* nonexistant memory */\r |
| 132 | #define RCER_TRK 0001000 /* track error */\r |
| 133 | #define RCER_APAR 0000200 /* address parity */\r |
| 134 | #define RCER_SADDR 0000100 /* sync address */\r |
| 135 | #define RCER_OVFL 0000040 /* disk overflow */\r |
| 136 | #define RCER_MIS 0000020 /* missed transfer */\r |
| 137 | \r |
| 138 | /* Lood Ahead Register (RCLA) */\r |
| 139 | \r |
| 140 | #define RCLA_BADD 0100000 /* bad address */\r |
| 141 | \r |
| 142 | /* extract device operation code */\r |
| 143 | #define GET_FUNC(x) (((x) >> RCCS_V_FUNC) & RCCS_M_FUNC)\r |
| 144 | /* extract memory extension address (bits 17,18) */\r |
| 145 | #define GET_MEX(x) (((x) & RCCS_MEX) << (16 - RCCS_V_MEX))\r |
| 146 | #define GET_POS(x) ((int) fmod (sim_gtime() / ((double) (x)), \\r |
| 147 | ((double) RC_NUMWD)))\r |
| 148 | \r |
| 149 | extern int32 int_req[IPL_HLVL];\r |
| 150 | extern FILE *sim_deb;\r |
| 151 | extern int32 R[];\r |
| 152 | \r |
| 153 | static uint32 rc_la = 0; /* look-ahead */\r |
| 154 | static uint32 rc_da = 0; /* disk address */\r |
| 155 | static uint32 rc_er = 0; /* error status */\r |
| 156 | static uint32 rc_cs = 0; /* command and status */\r |
| 157 | static uint32 rc_wc = 0; /* word count */\r |
| 158 | static uint32 rc_ca = 0; /* current address */\r |
| 159 | static uint32 rc_maint = 0; /* maintenance */\r |
| 160 | static uint32 rc_db = 0; /* data buffer */\r |
| 161 | static uint32 rc_wlk = 0; /* write lock */\r |
| 162 | static uint32 rc_time = 16; /* inter-word time: 16us */\r |
| 163 | static uint32 rc_stopioe = 1; /* stop on error */\r |
| 164 | \r |
| 165 | /* forward references */\r |
| 166 | \r |
| 167 | DEVICE rc_dev;\r |
| 168 | static t_stat rc_rd (int32 *, int32, int32);\r |
| 169 | static t_stat rc_wr (int32, int32, int32);\r |
| 170 | static t_stat rc_svc (UNIT *);\r |
| 171 | static t_stat rc_reset (DEVICE *);\r |
| 172 | static t_stat rc_attach (UNIT *, char *);\r |
| 173 | static t_stat rc_set_size (UNIT *, int32, char *, void *);\r |
| 174 | static uint32 update_rccs (uint32, uint32);\r |
| 175 | \r |
| 176 | /* RC11 data structures\r |
| 177 | \r |
| 178 | rc_dev RC device descriptor\r |
| 179 | rc_unit RC unit descriptor\r |
| 180 | rc_reg RC register list\r |
| 181 | */\r |
| 182 | \r |
| 183 | static DIB rc_dib = {\r |
| 184 | IOBA_RC,\r |
| 185 | IOLN_RC,\r |
| 186 | &rc_rd,\r |
| 187 | &rc_wr,\r |
| 188 | 1, IVCL (RC), VEC_RC, { NULL }\r |
| 189 | };\r |
| 190 | \r |
| 191 | static UNIT rc_unit = {\r |
| 192 | UDATA (&rc_svc, UNIT_FIX + UNIT_ATTABLE + UNIT_BUFABLE +\r |
| 193 | UNIT_MUSTBUF + UNIT_ROABLE + UNIT_BINK, RC_DKSIZE)\r |
| 194 | };\r |
| 195 | \r |
| 196 | static const REG rc_reg[] = {\r |
| 197 | { ORDATA (RCLA, rc_la, 16) },\r |
| 198 | { ORDATA (RCDA, rc_da, 16) },\r |
| 199 | { ORDATA (RCER, rc_er, 16) },\r |
| 200 | { ORDATA (RCCS, rc_cs, 16) },\r |
| 201 | { ORDATA (RCWC, rc_wc, 16) },\r |
| 202 | { ORDATA (RCCA, rc_ca, 16) },\r |
| 203 | { ORDATA (RCMN, rc_maint, 16) },\r |
| 204 | { ORDATA (RCDB, rc_db, 16) },\r |
| 205 | { ORDATA (RCWLK, rc_wlk, 32) },\r |
| 206 | { FLDATA (INT, IREQ (RC), INT_V_RC) },\r |
| 207 | { FLDATA (ERR, rc_cs, CSR_V_ERR) },\r |
| 208 | { FLDATA (DONE, rc_cs, CSR_V_DONE) },\r |
| 209 | { FLDATA (IE, rc_cs, CSR_V_IE) },\r |
| 210 | { DRDATA (TIME, rc_time, 24), REG_NZ + PV_LEFT },\r |
| 211 | { FLDATA (STOP_IOE, rc_stopioe, 0) },\r |
| 212 | { ORDATA (DEVADDR, rc_dib.ba, 32), REG_HRO },\r |
| 213 | { ORDATA (DEVVEC, rc_dib.vec, 16), REG_HRO },\r |
| 214 | { NULL }\r |
| 215 | };\r |
| 216 | \r |
| 217 | static const MTAB rc_mod[] = {\r |
| 218 | { UNIT_PLAT, (0 << UNIT_V_PLAT), NULL, "1P", &rc_set_size },\r |
| 219 | { UNIT_PLAT, (1 << UNIT_V_PLAT), NULL, "2P", &rc_set_size },\r |
| 220 | { UNIT_PLAT, (2 << UNIT_V_PLAT), NULL, "3P", &rc_set_size },\r |
| 221 | { UNIT_PLAT, (3 << UNIT_V_PLAT), NULL, "4P", &rc_set_size },\r |
| 222 | { UNIT_AUTO, UNIT_AUTO, "autosize", "AUTOSIZE", NULL },\r |
| 223 | { MTAB_XTD|MTAB_VDV, 020, "ADDRESS", "ADDRESS",\r |
| 224 | &set_addr, &show_addr, NULL },\r |
| 225 | { MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",\r |
| 226 | &set_vec, &show_vec, NULL },\r |
| 227 | { 0 }\r |
| 228 | };\r |
| 229 | \r |
| 230 | DEVICE rc_dev = {\r |
| 231 | "RC", &rc_unit, (REG *) rc_reg, (MTAB *) rc_mod,\r |
| 232 | 1, 8, 21, 1, 8, 16,\r |
| 233 | NULL, /* examine */\r |
| 234 | NULL, /* deposit */\r |
| 235 | &rc_reset, /* reset */\r |
| 236 | NULL, /* boot */\r |
| 237 | &rc_attach, /* attach */\r |
| 238 | NULL, /* detach */\r |
| 239 | &rc_dib,\r |
| 240 | DEV_DISABLE | DEV_DIS | DEV_UBUS | DEV_DEBUG\r |
| 241 | };\r |
| 242 | \r |
| 243 | /* I/O dispatch routine, I/O addresses 17777440 - 17777456 */\r |
| 244 | \r |
| 245 | static t_stat rc_rd (int32 *data, int32 PA, int32 access)\r |
| 246 | {\r |
| 247 | uint32 t;\r |
| 248 | \r |
| 249 | switch ((PA >> 1) & 07) { /* decode PA<3:1> */\r |
| 250 | \r |
| 251 | case 0: /* RCLA */\r |
| 252 | t = rc_la & 017777;\r |
| 253 | if ((rc_cs & RCCS_NED) || (rc_er & RCER_OVFL))\r |
| 254 | t |= RCLA_BADD;\r |
| 255 | *data = t;\r |
| 256 | /* simulate sequential rotation about the current track */\r |
| 257 | rc_la = (rc_la & ~077) | ((rc_la + 1) & 077);\r |
| 258 | if (DEBUG_PRS (rc_dev))\r |
| 259 | fprintf (sim_deb, ">>RC rd: RCLA %06o\n", rc_la);\r |
| 260 | break;\r |
| 261 | \r |
| 262 | case 1: /* RCDA */\r |
| 263 | *data = rc_da;\r |
| 264 | if (DEBUG_PRS (rc_dev))\r |
| 265 | fprintf (sim_deb, ">>RC rd: RCDA %06o, PC %06o\n",\r |
| 266 | rc_da, PC);\r |
| 267 | break;\r |
| 268 | \r |
| 269 | case 2: /* RCER */\r |
| 270 | *data = rc_er;\r |
| 271 | if (DEBUG_PRS (rc_dev))\r |
| 272 | fprintf (sim_deb, ">>RC rd: RCER %06o\n", rc_er);\r |
| 273 | break;\r |
| 274 | \r |
| 275 | case 3: /* RCCS */\r |
| 276 | *data = update_rccs (0, 0) & ~(RCCS_ABO | RCCS_GO);\r |
| 277 | if (DEBUG_PRS (rc_dev))\r |
| 278 | fprintf (sim_deb, ">>RC rd: RCCS %06o\n", *data);\r |
| 279 | break;\r |
| 280 | \r |
| 281 | case 4: /* RCWC */\r |
| 282 | *data = rc_wc;\r |
| 283 | if (DEBUG_PRS (rc_dev))\r |
| 284 | fprintf (sim_deb, ">>RC rd: RCWC %06o\n", rc_wc);\r |
| 285 | break;\r |
| 286 | \r |
| 287 | case 5: /* RCCA */\r |
| 288 | *data = rc_ca;\r |
| 289 | if (DEBUG_PRS (rc_dev))\r |
| 290 | fprintf (sim_deb, ">>RC rd: RCCA %06o\n", rc_ca);\r |
| 291 | break;\r |
| 292 | \r |
| 293 | case 6: /* RCMN */\r |
| 294 | *data = rc_maint;\r |
| 295 | if (DEBUG_PRS (rc_dev))\r |
| 296 | fprintf (sim_deb, ">>RC rd: RCMN %06o\n", rc_maint);\r |
| 297 | break;\r |
| 298 | \r |
| 299 | case 7: /* RCDB */\r |
| 300 | *data = rc_db;\r |
| 301 | if (DEBUG_PRS (rc_dev))\r |
| 302 | fprintf (sim_deb, ">>RC rd: RCDB %06o\n", rc_db);\r |
| 303 | break;\r |
| 304 | \r |
| 305 | default:\r |
| 306 | return (SCPE_NXM); /* can't happen */\r |
| 307 | } /* end switch */\r |
| 308 | return (SCPE_OK);\r |
| 309 | }\r |
| 310 | \r |
| 311 | static t_stat rc_wr (int32 data, int32 PA, int32 access)\r |
| 312 | {\r |
| 313 | int32 t;\r |
| 314 | \r |
| 315 | switch ((PA >> 1) & 07) { /* decode PA<3:1> */ \r |
| 316 | \r |
| 317 | case 0: /* RCLA */\r |
| 318 | if (DEBUG_PRS (rc_dev))\r |
| 319 | fprintf (sim_deb, ">>RC wr: RCLA\n");\r |
| 320 | break; /* read only */\r |
| 321 | \r |
| 322 | case 1: /* RCDA */\r |
| 323 | if (access == WRITEB)\r |
| 324 | data = (PA & 1) ?\r |
| 325 | (rc_da & 0377) | (data << 8) :\r |
| 326 | (rc_da & ~0377) | data;\r |
| 327 | rc_da = data & 017777;\r |
| 328 | rc_cs &= ~RCCS_NED;\r |
| 329 | update_rccs (0, 0);\r |
| 330 | /* perform unit select */\r |
| 331 | if (((rc_da >> 11) & 03) >= UNIT_GETP(rc_unit.flags))\r |
| 332 | update_rccs (RCCS_NED, 0);\r |
| 333 | else\r |
| 334 | rc_la = rc_da;\r |
| 335 | if (DEBUG_PRS (rc_dev))\r |
| 336 | fprintf (sim_deb, ">>RC wr: RCDA %06o, PC %06o\n",\r |
| 337 | rc_da, PC);\r |
| 338 | break;\r |
| 339 | \r |
| 340 | case 2: /* RCER */\r |
| 341 | if (DEBUG_PRS (rc_dev))\r |
| 342 | fprintf (sim_deb, ">>RC wr: RCER\n");\r |
| 343 | break; /* read only */\r |
| 344 | \r |
| 345 | case 3: /* RCCS */\r |
| 346 | if (access == WRITEB)\r |
| 347 | data = (PA & 1) ?\r |
| 348 | (rc_cs & 0377) | (data << 8) :\r |
| 349 | (rc_cs & ~0377) | data;\r |
| 350 | if (data & RCCS_ABO) {\r |
| 351 | update_rccs (RCCS_DONE, 0);\r |
| 352 | sim_cancel (&rc_unit);\r |
| 353 | }\r |
| 354 | if ((data & RCCS_IE) == 0) /* int disable? */\r |
| 355 | CLR_INT (RC); /* clr int request */\r |
| 356 | else if ((rc_cs & (RCCS_DONE | RCCS_IE)) == RCCS_DONE)\r |
| 357 | SET_INT (RC); /* set int request */\r |
| 358 | rc_cs = (rc_cs & ~RCCS_W) | (data & RCCS_W); /* merge */\r |
| 359 | if ((rc_cs & RCCS_DONE) && (data & RCCS_GO)) { /* new function? */\r |
| 360 | rc_unit.FUNC = GET_FUNC (data); /* save function */\r |
| 361 | t = (rc_da & RC_WMASK) - GET_POS (rc_time); /* delta to new loc */\r |
| 362 | if (t <= 0) /* wrap around? */\r |
| 363 | t = t + RC_NUMWD;\r |
| 364 | sim_activate (&rc_unit, t * rc_time); /* schedule op */\r |
| 365 | /* clear error indicators for new operation */\r |
| 366 | rc_cs &= ~(RCCS_ALLERR | RCCS_ERR | RCCS_DONE);\r |
| 367 | rc_er = 0;\r |
| 368 | CLR_INT (RC);\r |
| 369 | if (DEBUG_PRS (rc_dev))\r |
| 370 | fprintf (sim_deb, ">>RC start: cs = %o, da = %o, ma = %o, wc = %o\n",\r |
| 371 | update_rccs (0, 0), rc_da,\r |
| 372 | GET_MEX (rc_cs) | rc_ca, rc_wc);\r |
| 373 | }\r |
| 374 | break;\r |
| 375 | \r |
| 376 | case 4: /* RCWC */\r |
| 377 | if (access == WRITEB)\r |
| 378 | data = (PA & 1) ?\r |
| 379 | (rc_wc & 0377) | (data << 8) :\r |
| 380 | (rc_wc & ~0377) | data;\r |
| 381 | rc_wc = data & DMASK;\r |
| 382 | if (DEBUG_PRS (rc_dev))\r |
| 383 | fprintf (sim_deb, ">>RC wr: RCWC %06o, PC %06o\n",\r |
| 384 | rc_wc, PC);\r |
| 385 | break;\r |
| 386 | \r |
| 387 | case 5: /* RCCA */\r |
| 388 | /* TBD: write byte fixup? */\r |
| 389 | rc_ca = data & 0177776;\r |
| 390 | if (DEBUG_PRS (rc_dev))\r |
| 391 | fprintf (sim_deb, ">>RC wr: RCCA %06o\n", rc_ca);\r |
| 392 | break;\r |
| 393 | \r |
| 394 | case 6: /* RCMN */\r |
| 395 | /* TBD: write byte fixup? */\r |
| 396 | rc_maint = data & 0177700;\r |
| 397 | if (DEBUG_PRS (rc_dev))\r |
| 398 | fprintf (sim_deb, ">>RC wr: RCMN %06o\n", rc_maint);\r |
| 399 | break;\r |
| 400 | \r |
| 401 | case 7: /* RCDB */\r |
| 402 | if (DEBUG_PRS (rc_dev))\r |
| 403 | fprintf (sim_deb, ">>RC wr: RCDB\n");\r |
| 404 | break; /* read only */\r |
| 405 | \r |
| 406 | default: /* can't happen */\r |
| 407 | return (SCPE_NXM);\r |
| 408 | } /* end switch */\r |
| 409 | update_rccs (0, 0);\r |
| 410 | return (SCPE_OK);\r |
| 411 | }\r |
| 412 | \r |
| 413 | /* sector (32W) CRC-16 */\r |
| 414 | \r |
| 415 | static uint32 sectorCRC (const uint16 *data)\r |
| 416 | {\r |
| 417 | uint32 crc, i, j, d;\r |
| 418 | \r |
| 419 | crc = 0;\r |
| 420 | for (i = 0; i < 32; i++) {\r |
| 421 | d = *data++;\r |
| 422 | /* cribbed from KG11-A */\r |
| 423 | for (j = 0; j < 16; j++) {\r |
| 424 | crc = (crc & ~01) | ((crc & 01) ^ (d & 01));\r |
| 425 | crc = (crc & 01) ? (crc >> 1) ^ 0120001 : crc >> 1;\r |
| 426 | d >>= 1;\r |
| 427 | }\r |
| 428 | }\r |
| 429 | return (crc);\r |
| 430 | }\r |
| 431 | \r |
| 432 | /* Unit service\r |
| 433 | \r |
| 434 | Note that for reads and writes, memory addresses wrap around in the\r |
| 435 | current field. This code assumes the entire disk is buffered.\r |
| 436 | */\r |
| 437 | \r |
| 438 | static t_stat rc_svc (UNIT *uptr)\r |
| 439 | {\r |
| 440 | uint32 ma, da, t, u_old, u_new, last_da;\r |
| 441 | uint16 dat;\r |
| 442 | uint16 *fbuf = uptr->filebuf;\r |
| 443 | \r |
| 444 | if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? abort */\r |
| 445 | update_rccs (RCCS_NED | RCCS_DONE, 0); /* nx disk */\r |
| 446 | return (IORETURN (rc_stopioe, SCPE_UNATT));\r |
| 447 | }\r |
| 448 | \r |
| 449 | ma = GET_MEX (rc_cs) | rc_ca; /* 18b mem addr */\r |
| 450 | da = rc_da * RC_NUMTR; /* sector->word offset */\r |
| 451 | u_old = (da >> 16) & 03; /* save starting unit# */\r |
| 452 | do {\r |
| 453 | u_new = (da >> 16) & 03;\r |
| 454 | if (u_new < u_old) { /* unit # overflow? */\r |
| 455 | update_rccs (RCCS_NED, RCER_OVFL);\r |
| 456 | break;\r |
| 457 | }\r |
| 458 | if (u_new >= UNIT_GETP(uptr->flags)) { /* disk overflow? */\r |
| 459 | update_rccs (RCCS_NED, 0);\r |
| 460 | break;\r |
| 461 | }\r |
| 462 | if (uptr->FUNC == RFNC_READ) { /* read? */\r |
| 463 | last_da = da & ~037;\r |
| 464 | dat = fbuf[da]; /* get disk data */\r |
| 465 | rc_db = dat;\r |
| 466 | if (Map_WriteW (ma, 2, &dat)) { /* store mem, nxm? */\r |
| 467 | update_rccs (0, RCER_NXM);\r |
| 468 | break;\r |
| 469 | }\r |
| 470 | } else if (uptr->FUNC == RFNC_WCHK) { /* write check? */\r |
| 471 | last_da = da & ~037;\r |
| 472 | rc_db = fbuf[da]; /* get disk data */\r |
| 473 | if (Map_ReadW (ma, 2, &dat)) { /* read mem, nxm? */\r |
| 474 | update_rccs (0, RCER_NXM);\r |
| 475 | break;\r |
| 476 | }\r |
| 477 | if (rc_db != dat) { /* miscompare? */\r |
| 478 | update_rccs (RCCS_WCHK, 0);\r |
| 479 | break;\r |
| 480 | }\r |
| 481 | } else if (uptr->FUNC == RFNC_WRITE) { /* write */\r |
| 482 | t = (da >> 15) & 037;\r |
| 483 | if (((rc_wlk >> t) & 1) ||\r |
| 484 | (uptr->flags & UNIT_RO)) { /* write locked? */\r |
| 485 | update_rccs (RCCS_WLK, 0);\r |
| 486 | break;\r |
| 487 | }\r |
| 488 | /* not locked */\r |
| 489 | if (Map_ReadW (ma, 2, &dat)) { /* read mem, nxm? */\r |
| 490 | update_rccs (0, RCER_NXM);\r |
| 491 | break;\r |
| 492 | }\r |
| 493 | fbuf[da] = dat; /* write word */\r |
| 494 | rc_db = dat;\r |
| 495 | if (da >= uptr->hwmark)\r |
| 496 | uptr->hwmark = da + 1;\r |
| 497 | } else { /* look ahead */\r |
| 498 | break; /* no op for now */\r |
| 499 | }\r |
| 500 | rc_wc = (rc_wc + 1) & DMASK; /* incr word count */\r |
| 501 | da = (da + 1) & 0777777; /* incr disk addr */\r |
| 502 | if ((rc_cs & RCCS_INH) == 0) /* inhibit clear? */\r |
| 503 | ma = (ma + 2) & UNIMASK; /* incr mem addr */\r |
| 504 | } while (rc_wc != 0); /* brk if wc */\r |
| 505 | rc_ca = ma & DMASK; /* split ma */\r |
| 506 | rc_cs = (rc_cs & ~RCCS_MEX) | ((ma >> (16 - RCCS_V_MEX)) & RCCS_MEX); \r |
| 507 | da += 31;\r |
| 508 | rc_da = (da >> 5) & 017777;\r |
| 509 | /* CRC of last 32W, if necessary */\r |
| 510 | if ((uptr->FUNC == RFNC_READ) || (uptr->FUNC == RFNC_WCHK))\r |
| 511 | rc_db = sectorCRC (&fbuf[last_da]);\r |
| 512 | if (uptr->FUNC != RFNC_LAH)\r |
| 513 | rc_la = rc_da;\r |
| 514 | update_rccs (RCCS_DONE, 0);\r |
| 515 | if (DEBUG_PRS (rc_dev))\r |
| 516 | fprintf (sim_deb, ">>RC done: cs = %o, da = %o, ma = %o, wc = %o\n",\r |
| 517 | rc_cs, rc_da, rc_ca, rc_wc);\r |
| 518 | return (SCPE_OK);\r |
| 519 | }\r |
| 520 | \r |
| 521 | /* Update CS register */\r |
| 522 | \r |
| 523 | static uint32 update_rccs (uint32 newcs, uint32 newer)\r |
| 524 | {\r |
| 525 | uint32 oldcs = rc_cs;\r |
| 526 | \r |
| 527 | rc_er |= newer; /* update RCER */\r |
| 528 | rc_cs |= newcs; /* update CS */\r |
| 529 | if ((rc_cs & RCCS_ALLERR) || (rc_er != 0)) /* update CS<err> */\r |
| 530 | rc_cs |= RCCS_ERR;\r |
| 531 | else\r |
| 532 | rc_cs &= ~RCCS_ERR;\r |
| 533 | if ((rc_cs & RCCS_IE) && /* IE and */\r |
| 534 | (rc_cs & RCCS_DONE) && !(oldcs & RCCS_DONE)) /* done 0->1? */\r |
| 535 | SET_INT (RC);\r |
| 536 | return (rc_cs);\r |
| 537 | }\r |
| 538 | \r |
| 539 | /* Reset routine */\r |
| 540 | \r |
| 541 | static t_stat rc_reset (DEVICE *dptr)\r |
| 542 | {\r |
| 543 | rc_cs = RCCS_DONE;\r |
| 544 | rc_la = rc_da = 0;\r |
| 545 | rc_er = 0;\r |
| 546 | rc_wc = 0;\r |
| 547 | rc_ca = 0;\r |
| 548 | rc_maint = 0;\r |
| 549 | rc_db = 0;\r |
| 550 | CLR_INT (RC);\r |
| 551 | sim_cancel (&rc_unit);\r |
| 552 | return (SCPE_OK);\r |
| 553 | }\r |
| 554 | \r |
| 555 | /* Attach routine */\r |
| 556 | \r |
| 557 | static t_stat rc_attach (UNIT *uptr, char *cptr)\r |
| 558 | {\r |
| 559 | uint32 sz, p;\r |
| 560 | static const uint32 ds_bytes = RC_DKSIZE * sizeof (int16);\r |
| 561 | \r |
| 562 | if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize_name (cptr))) {\r |
| 563 | p = (sz + ds_bytes - 1) / ds_bytes;\r |
| 564 | if (p >= RC_NUMDK)\r |
| 565 | p = RC_NUMDK - 1;\r |
| 566 | uptr->flags = (uptr->flags & ~UNIT_PLAT) | (p << UNIT_V_PLAT);\r |
| 567 | }\r |
| 568 | uptr->capac = UNIT_GETP (uptr->flags) * RC_DKSIZE;\r |
| 569 | return (attach_unit (uptr, cptr));\r |
| 570 | }\r |
| 571 | \r |
| 572 | /* Change disk size */\r |
| 573 | \r |
| 574 | static t_stat rc_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)\r |
| 575 | {\r |
| 576 | if (val < 0)\r |
| 577 | return (SCPE_IERR);\r |
| 578 | if (uptr->flags & UNIT_ATT)\r |
| 579 | return (SCPE_ALATT);\r |
| 580 | uptr->capac = UNIT_GETP (val) * RC_DKSIZE;\r |
| 581 | uptr->flags = uptr->flags & ~UNIT_AUTO;\r |
| 582 | return (SCPE_OK);\r |
| 583 | }\r |