| 1 | /* pdp11_rl.c: RL11 (RLV12) cartridge disk simulator\r |
| 2 | \r |
| 3 | Copyright (c) 1993-2005, Robert M Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | rl RL11(RLV12)/RL01/RL02 cartridge disk\r |
| 27 | \r |
| 28 | 22-Sep-05 RMS Fixed declarations (from Sterling Garwood)\r |
| 29 | 16-Aug-05 RMS Fixed C++ declaration and cast problems\r |
| 30 | 07-Jul-05 RMS Removed extraneous externs\r |
| 31 | 30-Sep-04 RMS Revised Unibus interface\r |
| 32 | 04-Jan-04 RMS Changed sim_fsize calling sequence\r |
| 33 | 19-May-03 RMS Revised for new conditional compilation scheme\r |
| 34 | 25-Apr-03 RMS Revised for extended file support\r |
| 35 | 29-Sep-02 RMS Added variable address support to bootstrap\r |
| 36 | Added vector change/display support\r |
| 37 | Revised mapping nomenclature\r |
| 38 | New data structures\r |
| 39 | 26-Jan-02 RMS Revised bootstrap to conform to M9312\r |
| 40 | 06-Jan-02 RMS Revised enable/disable support\r |
| 41 | 30-Nov-01 RMS Added read only, extended SET/SHOW support\r |
| 42 | 26-Nov-01 RMS Fixed per-drive error handling\r |
| 43 | 24-Nov-01 RMS Converted FLG, CAPAC to arrays\r |
| 44 | 19-Nov-01 RMS Fixed signed/unsigned mismatch in write check\r |
| 45 | 09-Nov-01 RMS Added bus map, VAX support\r |
| 46 | 07-Sep-01 RMS Revised device disable and interrupt mechanisms\r |
| 47 | 20-Aug-01 RMS Added bad block option in attach\r |
| 48 | 17-Jul-01 RMS Fixed warning from VC++ 6.0\r |
| 49 | 26-Apr-01 RMS Added device enable/disable support\r |
| 50 | 25-Mar-01 RMS Fixed block fill calculation\r |
| 51 | 15-Feb-01 RMS Corrected bootstrap string\r |
| 52 | 12-Nov-97 RMS Added bad block table command\r |
| 53 | 25-Nov-96 RMS Default units to autosize\r |
| 54 | 29-Jun-96 RMS Added unit disable support\r |
| 55 | \r |
| 56 | The RL11 is a four drive cartridge disk subsystem. An RL01 drive\r |
| 57 | consists of 256 cylinders, each with 2 surfaces containing 40 sectors\r |
| 58 | of 256 bytes. An RL02 drive has 512 cylinders. The RLV12 is a\r |
| 59 | controller variant which supports 22b direct addressing.\r |
| 60 | \r |
| 61 | The most complicated part of the RL11 controller is the way it does\r |
| 62 | seeks. Seeking is relative to the current disk address; this requires\r |
| 63 | keeping accurate track of the current cylinder. The RL11 will not\r |
| 64 | switch heads or cross cylinders during transfers.\r |
| 65 | \r |
| 66 | The RL11 functions in three environments:\r |
| 67 | \r |
| 68 | - PDP-11 Q22 systems - the I/O map is one for one, so it's safe to\r |
| 69 | go through the I/O map\r |
| 70 | - PDP-11 Unibus 22b systems - the RL11 behaves as an 18b Unibus\r |
| 71 | peripheral and must go through the I/O map\r |
| 72 | - VAX Q22 systems - the RL11 must go through the I/O map\r |
| 73 | */\r |
| 74 | \r |
| 75 | #if defined (VM_PDP10) /* PDP10 version */\r |
| 76 | #error "RL11 is not supported on the PDP-10!"\r |
| 77 | \r |
| 78 | #elif defined (VM_VAX) /* VAX version */\r |
| 79 | #include "vax_defs.h"\r |
| 80 | \r |
| 81 | #else /* PDP-11 version */\r |
| 82 | #include "pdp11_defs.h"\r |
| 83 | extern uint32 cpu_opt;\r |
| 84 | #endif\r |
| 85 | \r |
| 86 | /* Constants */\r |
| 87 | \r |
| 88 | #define RL_NUMWD 128 /* words/sector */\r |
| 89 | #define RL_NUMSC 40 /* sectors/surface */\r |
| 90 | #define RL_NUMSF 2 /* surfaces/cylinder */\r |
| 91 | #define RL_NUMCY 256 /* cylinders/drive */\r |
| 92 | #define RL_NUMDR 4 /* drives/controller */\r |
| 93 | #define RL_MAXFR (1 << 16) /* max transfer */\r |
| 94 | #define RL01_SIZE (RL_NUMCY * RL_NUMSF * RL_NUMSC * RL_NUMWD) /* words/drive */\r |
| 95 | #define RL02_SIZE (RL01_SIZE * 2) /* words/drive */\r |
| 96 | \r |
| 97 | /* Flags in the unit flags word */\r |
| 98 | \r |
| 99 | #define UNIT_V_WLK (UNIT_V_UF + 0) /* hwre write lock */\r |
| 100 | #define UNIT_V_RL02 (UNIT_V_UF + 1) /* RL01 vs RL02 */\r |
| 101 | #define UNIT_V_AUTO (UNIT_V_UF + 2) /* autosize enable */\r |
| 102 | #define UNIT_V_DUMMY (UNIT_V_UF + 3) /* dummy flag */\r |
| 103 | #define UNIT_DUMMY (1 << UNIT_V_DUMMY)\r |
| 104 | #define UNIT_WLK (1u << UNIT_V_WLK)\r |
| 105 | #define UNIT_RL02 (1u << UNIT_V_RL02)\r |
| 106 | #define UNIT_AUTO (1u << UNIT_V_AUTO)\r |
| 107 | #define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protected */\r |
| 108 | \r |
| 109 | /* Parameters in the unit descriptor */\r |
| 110 | \r |
| 111 | #define TRK u3 /* current track */\r |
| 112 | #define STAT u4 /* status */\r |
| 113 | \r |
| 114 | /* RLDS, NI = not implemented, * = kept in STAT, ^ = kept in TRK */\r |
| 115 | \r |
| 116 | #define RLDS_LOAD 0 /* no cartridge */\r |
| 117 | #define RLDS_LOCK 5 /* lock on */\r |
| 118 | #define RLDS_BHO 0000010 /* brushes home NI */\r |
| 119 | #define RLDS_HDO 0000020 /* heads out NI */\r |
| 120 | #define RLDS_CVO 0000040 /* cover open NI */\r |
| 121 | #define RLDS_HD 0000100 /* head select ^ */\r |
| 122 | #define RLDS_RL02 0000200 /* RL02 */\r |
| 123 | #define RLDS_DSE 0000400 /* drv sel err NI */\r |
| 124 | #define RLDS_VCK 0001000 /* vol check * */\r |
| 125 | #define RLDS_WGE 0002000 /* wr gate err * */\r |
| 126 | #define RLDS_SPE 0004000 /* spin err * */\r |
| 127 | #define RLDS_STO 0010000 /* seek time out NI */\r |
| 128 | #define RLDS_WLK 0020000 /* wr locked */\r |
| 129 | #define RLDS_HCE 0040000 /* hd curr err NI */\r |
| 130 | #define RLDS_WDE 0100000 /* wr data err NI */\r |
| 131 | #define RLDS_ATT (RLDS_HDO+RLDS_BHO+RLDS_LOCK) /* att status */\r |
| 132 | #define RLDS_UNATT (RLDS_CVO+RLDS_LOAD) /* unatt status */\r |
| 133 | #define RLDS_ERR (RLDS_WDE+RLDS_HCE+RLDS_STO+RLDS_SPE+RLDS_WGE+ \\r |
| 134 | RLDS_VCK+RLDS_DSE) /* errors bits */\r |
| 135 | \r |
| 136 | /* RLCS */\r |
| 137 | \r |
| 138 | #define RLCS_DRDY 0000001 /* drive ready */\r |
| 139 | #define RLCS_M_FUNC 0000007 /* function */\r |
| 140 | #define RLCS_NOP 0\r |
| 141 | #define RLCS_WCHK 1\r |
| 142 | #define RLCS_GSTA 2\r |
| 143 | #define RLCS_SEEK 3\r |
| 144 | #define RLCS_RHDR 4\r |
| 145 | #define RLCS_WRITE 5\r |
| 146 | #define RLCS_READ 6\r |
| 147 | #define RLCS_RNOHDR 7\r |
| 148 | #define RLCS_V_FUNC 1\r |
| 149 | #define RLCS_M_MEX 03 /* memory extension */\r |
| 150 | #define RLCS_V_MEX 4\r |
| 151 | #define RLCS_MEX (RLCS_M_MEX << RLCS_V_MEX)\r |
| 152 | #define RLCS_M_DRIVE 03\r |
| 153 | #define RLCS_V_DRIVE 8\r |
| 154 | #define RLCS_INCMP 0002000 /* incomplete */\r |
| 155 | #define RLCS_CRC 0004000 /* CRC error */\r |
| 156 | #define RLCS_HDE 0010000 /* header error */\r |
| 157 | #define RLCS_NXM 0020000 /* non-exist memory */\r |
| 158 | #define RLCS_DRE 0040000 /* drive error */\r |
| 159 | #define RLCS_ERR 0100000 /* error summary */\r |
| 160 | #define RLCS_ALLERR (RLCS_ERR+RLCS_DRE+RLCS_NXM+RLCS_HDE+RLCS_CRC+RLCS_INCMP)\r |
| 161 | #define RLCS_RW 0001776 /* read/write */\r |
| 162 | #define GET_FUNC(x) (((x) >> RLCS_V_FUNC) & RLCS_M_FUNC)\r |
| 163 | #define GET_DRIVE(x) (((x) >> RLCS_V_DRIVE) & RLCS_M_DRIVE)\r |
| 164 | \r |
| 165 | /* RLDA */\r |
| 166 | \r |
| 167 | #define RLDA_SK_DIR 0000004 /* direction */\r |
| 168 | #define RLDA_GS_CLR 0000010 /* clear errors */\r |
| 169 | #define RLDA_SK_HD 0000020 /* head select */\r |
| 170 | \r |
| 171 | #define RLDA_V_SECT 0 /* sector */\r |
| 172 | #define RLDA_M_SECT 077\r |
| 173 | #define RLDA_V_TRACK 6 /* track */\r |
| 174 | #define RLDA_M_TRACK 01777\r |
| 175 | #define RLDA_HD0 (0 << RLDA_V_TRACK)\r |
| 176 | #define RLDA_HD1 (1u << RLDA_V_TRACK)\r |
| 177 | #define RLDA_V_CYL 7 /* cylinder */\r |
| 178 | #define RLDA_M_CYL 0777\r |
| 179 | #define RLDA_TRACK (RLDA_M_TRACK << RLDA_V_TRACK)\r |
| 180 | #define RLDA_CYL (RLDA_M_CYL << RLDA_V_CYL)\r |
| 181 | #define GET_SECT(x) (((x) >> RLDA_V_SECT) & RLDA_M_SECT)\r |
| 182 | #define GET_CYL(x) (((x) >> RLDA_V_CYL) & RLDA_M_CYL)\r |
| 183 | #define GET_TRACK(x) (((x) >> RLDA_V_TRACK) & RLDA_M_TRACK)\r |
| 184 | #define GET_DA(x) ((GET_TRACK (x) * RL_NUMSC) + GET_SECT (x))\r |
| 185 | \r |
| 186 | /* RLBA */\r |
| 187 | \r |
| 188 | #define RLBA_IMP 0177776 /* implemented */\r |
| 189 | \r |
| 190 | /* RLBAE */\r |
| 191 | \r |
| 192 | #define RLBAE_IMP 0000077 /* implemented */\r |
| 193 | \r |
| 194 | extern int32 int_req[IPL_HLVL];\r |
| 195 | \r |
| 196 | uint16 *rlxb = NULL; /* xfer buffer */\r |
| 197 | int32 rlcs = 0; /* control/status */\r |
| 198 | int32 rlba = 0; /* memory address */\r |
| 199 | int32 rlbae = 0; /* mem addr extension */\r |
| 200 | int32 rlda = 0; /* disk addr */\r |
| 201 | int32 rlmp = 0, rlmp1 = 0, rlmp2 = 0; /* mp register queue */\r |
| 202 | int32 rl_swait = 10; /* seek wait */\r |
| 203 | int32 rl_rwait = 10; /* rotate wait */\r |
| 204 | int32 rl_stopioe = 1; /* stop on error */\r |
| 205 | \r |
| 206 | DEVICE rl_dev;\r |
| 207 | t_stat rl_rd (int32 *data, int32 PA, int32 access);\r |
| 208 | t_stat rl_wr (int32 data, int32 PA, int32 access);\r |
| 209 | t_stat rl_svc (UNIT *uptr);\r |
| 210 | t_stat rl_reset (DEVICE *dptr);\r |
| 211 | void rl_set_done (int32 error);\r |
| 212 | t_stat rl_boot (int32 unitno, DEVICE *dptr);\r |
| 213 | t_stat rl_attach (UNIT *uptr, char *cptr);\r |
| 214 | t_stat rl_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 215 | t_stat rl_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 216 | extern t_stat pdp11_bad_block (UNIT *uptr, int32 sec, int32 wds);\r |
| 217 | \r |
| 218 | /* RL11 data structures\r |
| 219 | \r |
| 220 | rl_dev RL device descriptor\r |
| 221 | rl_unit RL unit list\r |
| 222 | rl_reg RL register list\r |
| 223 | rl_mod RL modifier list\r |
| 224 | */\r |
| 225 | \r |
| 226 | DIB rl_dib = {\r |
| 227 | IOBA_RL, IOLN_RL, &rl_rd, &rl_wr,\r |
| 228 | 1, IVCL (RL), VEC_RL, { NULL } };\r |
| 229 | \r |
| 230 | UNIT rl_unit[] = {\r |
| 231 | { UDATA (&rl_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+\r |
| 232 | UNIT_ROABLE+UNIT_AUTO, RL01_SIZE) },\r |
| 233 | { UDATA (&rl_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+\r |
| 234 | UNIT_ROABLE+UNIT_AUTO, RL01_SIZE) },\r |
| 235 | { UDATA (&rl_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+\r |
| 236 | UNIT_ROABLE+UNIT_AUTO, RL01_SIZE) },\r |
| 237 | { UDATA (&rl_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_DISABLE+\r |
| 238 | UNIT_ROABLE+UNIT_AUTO, RL01_SIZE) }\r |
| 239 | };\r |
| 240 | \r |
| 241 | REG rl_reg[] = {\r |
| 242 | { GRDATA (RLCS, rlcs, DEV_RDX, 16, 0) },\r |
| 243 | { GRDATA (RLDA, rlda, DEV_RDX, 16, 0) },\r |
| 244 | { GRDATA (RLBA, rlba, DEV_RDX, 16, 0) },\r |
| 245 | { GRDATA (RLBAE, rlbae, DEV_RDX, 6, 0) },\r |
| 246 | { GRDATA (RLMP, rlmp, DEV_RDX, 16, 0) },\r |
| 247 | { GRDATA (RLMP1, rlmp1, DEV_RDX, 16, 0) },\r |
| 248 | { GRDATA (RLMP2, rlmp2, DEV_RDX, 16, 0) },\r |
| 249 | { FLDATA (INT, IREQ (RL), INT_V_RL) },\r |
| 250 | { FLDATA (ERR, rlcs, CSR_V_ERR) },\r |
| 251 | { FLDATA (DONE, rlcs, CSR_V_DONE) },\r |
| 252 | { FLDATA (IE, rlcs, CSR_V_IE) },\r |
| 253 | { DRDATA (STIME, rl_swait, 24), PV_LEFT },\r |
| 254 | { DRDATA (RTIME, rl_rwait, 24), PV_LEFT },\r |
| 255 | { URDATA (CAPAC, rl_unit[0].capac, 10, T_ADDR_W, 0,\r |
| 256 | RL_NUMDR, PV_LEFT + REG_HRO) },\r |
| 257 | { FLDATA (STOP_IOE, rl_stopioe, 0) },\r |
| 258 | { GRDATA (DEVADDR, rl_dib.ba, DEV_RDX, 32, 0), REG_HRO },\r |
| 259 | { GRDATA (DEVVEC, rl_dib.vec, DEV_RDX, 16, 0), REG_HRO },\r |
| 260 | { NULL }\r |
| 261 | };\r |
| 262 | \r |
| 263 | MTAB rl_mod[] = {\r |
| 264 | { UNIT_WLK, 0, "write enabled", "WRITEENABLED", NULL },\r |
| 265 | { UNIT_WLK, UNIT_WLK, "write locked", "LOCKED", NULL },\r |
| 266 | { UNIT_DUMMY, 0, NULL, "BADBLOCK", &rl_set_bad },\r |
| 267 | { (UNIT_RL02+UNIT_ATT), UNIT_ATT, "RL01", NULL, NULL },\r |
| 268 | { (UNIT_RL02+UNIT_ATT), (UNIT_RL02+UNIT_ATT), "RL02", NULL, NULL },\r |
| 269 | { (UNIT_AUTO+UNIT_RL02+UNIT_ATT), 0, "RL01", NULL, NULL },\r |
| 270 | { (UNIT_AUTO+UNIT_RL02+UNIT_ATT), UNIT_RL02, "RL02", NULL, NULL },\r |
| 271 | { (UNIT_AUTO+UNIT_ATT), UNIT_AUTO, "autosize", NULL, NULL },\r |
| 272 | { UNIT_AUTO, UNIT_AUTO, NULL, "AUTOSIZE", NULL },\r |
| 273 | { (UNIT_AUTO+UNIT_RL02), 0, NULL, "RL01", &rl_set_size },\r |
| 274 | { (UNIT_AUTO+UNIT_RL02), UNIT_RL02, NULL, "RL02", &rl_set_size },\r |
| 275 | { MTAB_XTD|MTAB_VDV, 010, "ADDRESS", "ADDRESS",\r |
| 276 | &set_addr, &show_addr, NULL },\r |
| 277 | { MTAB_XTD|MTAB_VDV, 0, "VECTOR", "VECTOR",\r |
| 278 | &set_vec, &show_vec, NULL },\r |
| 279 | { 0 }\r |
| 280 | };\r |
| 281 | \r |
| 282 | DEVICE rl_dev = {\r |
| 283 | "RL", rl_unit, rl_reg, rl_mod,\r |
| 284 | RL_NUMDR, DEV_RDX, 24, 1, DEV_RDX, 16,\r |
| 285 | NULL, NULL, &rl_reset,\r |
| 286 | &rl_boot, &rl_attach, NULL,\r |
| 287 | &rl_dib, DEV_DISABLE | DEV_UBUS | DEV_QBUS\r |
| 288 | };\r |
| 289 | \r |
| 290 | /* I/O dispatch routines, I/O addresses 17774400 - 17774407\r |
| 291 | \r |
| 292 | 17774400 RLCS read/write\r |
| 293 | 17774402 RLBA read/write\r |
| 294 | 17774404 RLDA read/write\r |
| 295 | 17774406 RLMP read/write\r |
| 296 | 17774410 RLBAE read/write\r |
| 297 | */\r |
| 298 | \r |
| 299 | t_stat rl_rd (int32 *data, int32 PA, int32 access)\r |
| 300 | {\r |
| 301 | UNIT *uptr;\r |
| 302 | \r |
| 303 | switch ((PA >> 1) & 07) { /* decode PA<2:1> */\r |
| 304 | \r |
| 305 | case 0: /* RLCS */\r |
| 306 | rlcs = (rlcs & ~RLCS_MEX) | ((rlbae & RLCS_M_MEX) << RLCS_V_MEX);\r |
| 307 | if (rlcs & RLCS_ALLERR) rlcs = rlcs | RLCS_ERR;\r |
| 308 | uptr = rl_dev.units + GET_DRIVE (rlcs);\r |
| 309 | if (sim_is_active (uptr)) rlcs = rlcs & ~RLCS_DRDY;\r |
| 310 | else rlcs = rlcs | RLCS_DRDY; /* see if ready */\r |
| 311 | *data = rlcs;\r |
| 312 | break;\r |
| 313 | \r |
| 314 | case 1: /* RLBA */\r |
| 315 | *data = rlba & RLBA_IMP;\r |
| 316 | break;\r |
| 317 | \r |
| 318 | case 2: /* RLDA */\r |
| 319 | *data = rlda;\r |
| 320 | break;\r |
| 321 | \r |
| 322 | case 3: /* RLMP */\r |
| 323 | *data = rlmp;\r |
| 324 | rlmp = rlmp1; /* ripple data */\r |
| 325 | rlmp1 = rlmp2;\r |
| 326 | break;\r |
| 327 | \r |
| 328 | case 4: /* RLBAE */\r |
| 329 | if (UNIBUS) return SCPE_NXM; /* not in RL11 */\r |
| 330 | *data = rlbae & RLBAE_IMP;\r |
| 331 | break;\r |
| 332 | } /* end switch */\r |
| 333 | \r |
| 334 | return SCPE_OK;\r |
| 335 | }\r |
| 336 | \r |
| 337 | t_stat rl_wr (int32 data, int32 PA, int32 access)\r |
| 338 | {\r |
| 339 | int32 curr, offs, newc, maxc;\r |
| 340 | UNIT *uptr;\r |
| 341 | \r |
| 342 | switch ((PA >> 1) & 07) { /* decode PA<2:1> */\r |
| 343 | \r |
| 344 | case 0: /* RLCS */\r |
| 345 | rlcs = (rlcs & ~RLCS_MEX) | ((rlbae & RLCS_M_MEX) << RLCS_V_MEX);\r |
| 346 | if (rlcs & RLCS_ALLERR) rlcs = rlcs | RLCS_ERR;\r |
| 347 | uptr = rl_dev.units + GET_DRIVE (data); /* get new drive */\r |
| 348 | if (sim_is_active (uptr)) rlcs = rlcs & ~RLCS_DRDY;\r |
| 349 | else rlcs = rlcs | RLCS_DRDY; /* see if ready */\r |
| 350 | \r |
| 351 | if (access == WRITEB) data = (PA & 1)?\r |
| 352 | (rlcs & 0377) | (data << 8): (rlcs & ~0377) | data;\r |
| 353 | rlcs = (rlcs & ~RLCS_RW) | (data & RLCS_RW);\r |
| 354 | rlbae = (rlbae & ~RLCS_M_MEX) | ((rlcs >> RLCS_V_MEX) & RLCS_M_MEX);\r |
| 355 | if (data & CSR_DONE) { /* ready set? */\r |
| 356 | if ((data & CSR_IE) == 0) CLR_INT (RL);\r |
| 357 | else if ((rlcs & (CSR_DONE + CSR_IE)) == CSR_DONE)\r |
| 358 | SET_INT (RL); \r |
| 359 | return SCPE_OK;\r |
| 360 | }\r |
| 361 | \r |
| 362 | CLR_INT (RL); /* clear interrupt */\r |
| 363 | rlcs = rlcs & ~RLCS_ALLERR; /* clear errors */\r |
| 364 | switch (GET_FUNC (rlcs)) { /* case on RLCS<3:1> */\r |
| 365 | case RLCS_NOP: /* nop */\r |
| 366 | rl_set_done (0);\r |
| 367 | break;\r |
| 368 | case RLCS_SEEK: /* seek */\r |
| 369 | curr = GET_CYL (uptr->TRK); /* current cylinder */\r |
| 370 | offs = GET_CYL (rlda); /* offset */\r |
| 371 | if (rlda & RLDA_SK_DIR) { /* in or out? */\r |
| 372 | newc = curr + offs; /* out */\r |
| 373 | maxc = (uptr->flags & UNIT_RL02)?\r |
| 374 | RL_NUMCY * 2: RL_NUMCY;\r |
| 375 | if (newc >= maxc) newc = maxc - 1;\r |
| 376 | }\r |
| 377 | else {\r |
| 378 | newc = curr - offs; /* in */\r |
| 379 | if (newc < 0) newc = 0;\r |
| 380 | }\r |
| 381 | uptr->TRK = (newc << RLDA_V_CYL) | /* put on track */\r |
| 382 | ((rlda & RLDA_SK_HD)? RLDA_HD1: RLDA_HD0);\r |
| 383 | sim_activate (uptr, rl_swait * abs (newc - curr));\r |
| 384 | break;\r |
| 385 | default: /* data transfer */\r |
| 386 | sim_activate (uptr, rl_swait); /* activate unit */\r |
| 387 | break;\r |
| 388 | } /* end switch func */\r |
| 389 | break; /* end case RLCS */\r |
| 390 | \r |
| 391 | case 1: /* RLBA */\r |
| 392 | if (access == WRITEB) data = (PA & 1)?\r |
| 393 | (rlba & 0377) | (data << 8): (rlba & ~0377) | data;\r |
| 394 | rlba = data & RLBA_IMP;\r |
| 395 | break;\r |
| 396 | \r |
| 397 | case 2: /* RLDA */\r |
| 398 | if (access == WRITEB) data = (PA & 1)?\r |
| 399 | (rlda & 0377) | (data << 8): (rlda & ~0377) | data;\r |
| 400 | rlda = data;\r |
| 401 | break;\r |
| 402 | \r |
| 403 | case 3: /* RLMP */\r |
| 404 | if (access == WRITEB) data = (PA & 1)?\r |
| 405 | (rlmp & 0377) | (data << 8): (rlmp & ~0377) | data;\r |
| 406 | rlmp = rlmp1 = rlmp2 = data;\r |
| 407 | break;\r |
| 408 | \r |
| 409 | case 4: /* RLBAE */\r |
| 410 | if (UNIBUS) return SCPE_NXM; /* not in RL11 */\r |
| 411 | if (PA & 1) return SCPE_OK;\r |
| 412 | rlbae = data & RLBAE_IMP;\r |
| 413 | rlcs = (rlcs & ~RLCS_MEX) | ((rlbae & RLCS_M_MEX) << RLCS_V_MEX);\r |
| 414 | break;\r |
| 415 | } /* end switch */\r |
| 416 | \r |
| 417 | return SCPE_OK;\r |
| 418 | }\r |
| 419 | \r |
| 420 | /* Service unit timeout\r |
| 421 | \r |
| 422 | If seek in progress, complete seek command\r |
| 423 | Else complete data transfer command\r |
| 424 | \r |
| 425 | The unit control block contains the function and cylinder for\r |
| 426 | the current command.\r |
| 427 | */\r |
| 428 | \r |
| 429 | t_stat rl_svc (UNIT *uptr)\r |
| 430 | {\r |
| 431 | int32 err, wc, maxwc, t;\r |
| 432 | int32 i, func, da, awc;\r |
| 433 | uint32 ma;\r |
| 434 | uint16 comp;\r |
| 435 | \r |
| 436 | func = GET_FUNC (rlcs); /* get function */\r |
| 437 | if (func == RLCS_GSTA) { /* get status */\r |
| 438 | if (rlda & RLDA_GS_CLR) uptr->STAT = uptr->STAT & ~RLDS_ERR;\r |
| 439 | rlmp = uptr->STAT | (uptr->TRK & RLDS_HD) |\r |
| 440 | ((uptr->flags & UNIT_ATT)? RLDS_ATT: RLDS_UNATT);\r |
| 441 | if (uptr->flags & UNIT_RL02) rlmp = rlmp | RLDS_RL02;\r |
| 442 | if (uptr->flags & UNIT_WPRT) rlmp = rlmp | RLDS_WLK;\r |
| 443 | rlmp2 = rlmp1 = rlmp;\r |
| 444 | rl_set_done (0); /* done */\r |
| 445 | return SCPE_OK;\r |
| 446 | }\r |
| 447 | \r |
| 448 | if ((uptr->flags & UNIT_ATT) == 0) { /* attached? */\r |
| 449 | rlcs = rlcs & ~RLCS_DRDY; /* clear drive ready */\r |
| 450 | uptr->STAT = uptr->STAT | RLDS_SPE; /* spin error */\r |
| 451 | rl_set_done (RLCS_ERR | RLCS_INCMP); /* flag error */\r |
| 452 | return IORETURN (rl_stopioe, SCPE_UNATT);\r |
| 453 | }\r |
| 454 | \r |
| 455 | if ((func == RLCS_WRITE) && (uptr->flags & UNIT_WPRT)) {\r |
| 456 | uptr->STAT = uptr->STAT | RLDS_WGE; /* write and locked */\r |
| 457 | rl_set_done (RLCS_ERR | RLCS_DRE);\r |
| 458 | return SCPE_OK;\r |
| 459 | }\r |
| 460 | \r |
| 461 | if (func == RLCS_SEEK) { /* seek? */\r |
| 462 | rl_set_done (0); /* done */\r |
| 463 | return SCPE_OK;\r |
| 464 | }\r |
| 465 | \r |
| 466 | if (func == RLCS_RHDR) { /* read header? */\r |
| 467 | rlmp = (uptr->TRK & RLDA_TRACK) | GET_SECT (rlda);\r |
| 468 | rlmp1 = rlmp2 = 0;\r |
| 469 | rl_set_done (0); /* done */\r |
| 470 | return SCPE_OK;\r |
| 471 | }\r |
| 472 | \r |
| 473 | if (((func != RLCS_RNOHDR) && ((uptr->TRK & RLDA_CYL) != (rlda & RLDA_CYL)))\r |
| 474 | || (GET_SECT (rlda) >= RL_NUMSC)) { /* bad cyl or sector? */\r |
| 475 | rl_set_done (RLCS_ERR | RLCS_HDE | RLCS_INCMP); /* wrong cylinder? */\r |
| 476 | return SCPE_OK;\r |
| 477 | }\r |
| 478 | \r |
| 479 | ma = (rlbae << 16) | rlba; /* get mem addr */\r |
| 480 | da = GET_DA (rlda) * RL_NUMWD; /* get disk addr */\r |
| 481 | wc = 0200000 - rlmp; /* get true wc */\r |
| 482 | \r |
| 483 | maxwc = (RL_NUMSC - GET_SECT (rlda)) * RL_NUMWD; /* max transfer */\r |
| 484 | if (wc > maxwc) wc = maxwc; /* track overrun? */\r |
| 485 | err = fseek (uptr->fileref, da * sizeof (int16), SEEK_SET);\r |
| 486 | \r |
| 487 | if ((func >= RLCS_READ) && (err == 0)) { /* read (no hdr)? */\r |
| 488 | i = fxread (rlxb, sizeof (int16), wc, uptr->fileref);\r |
| 489 | err = ferror (uptr->fileref);\r |
| 490 | for ( ; i < wc; i++) rlxb[i] = 0; /* fill buffer */\r |
| 491 | if (t = Map_WriteW (ma, wc << 1, rlxb)) { /* store buffer */\r |
| 492 | rlcs = rlcs | RLCS_ERR | RLCS_NXM; /* nxm */\r |
| 493 | wc = wc - t; /* adjust wc */\r |
| 494 | }\r |
| 495 | } /* end read */\r |
| 496 | \r |
| 497 | if ((func == RLCS_WRITE) && (err == 0)) { /* write? */\r |
| 498 | if (t = Map_ReadW (ma, wc << 1, rlxb)) { /* fetch buffer */\r |
| 499 | rlcs = rlcs | RLCS_ERR | RLCS_NXM; /* nxm */\r |
| 500 | wc = wc - t; /* adj xfer lnt */\r |
| 501 | }\r |
| 502 | if (wc) { /* any xfer? */\r |
| 503 | awc = (wc + (RL_NUMWD - 1)) & ~(RL_NUMWD - 1); /* clr to */\r |
| 504 | for (i = wc; i < awc; i++) rlxb[i] = 0; /* end of blk */\r |
| 505 | fxwrite (rlxb, sizeof (int16), awc, uptr->fileref);\r |
| 506 | err = ferror (uptr->fileref);\r |
| 507 | }\r |
| 508 | } /* end write */\r |
| 509 | \r |
| 510 | if ((func == RLCS_WCHK) && (err == 0)) { /* write check? */\r |
| 511 | i = fxread (rlxb, sizeof (int16), wc, uptr->fileref);\r |
| 512 | err = ferror (uptr->fileref);\r |
| 513 | for ( ; i < wc; i++) rlxb[i] = 0; /* fill buffer */\r |
| 514 | awc = wc; /* save wc */\r |
| 515 | for (wc = 0; (err == 0) && (wc < awc); wc++) { /* loop thru buf */\r |
| 516 | if (Map_ReadW (ma + (wc << 1), 2, &comp)) { /* mem wd */\r |
| 517 | rlcs = rlcs | RLCS_ERR | RLCS_NXM; /* nxm */\r |
| 518 | break;\r |
| 519 | }\r |
| 520 | if (comp != rlxb[wc]) /* check to buf */\r |
| 521 | rlcs = rlcs | RLCS_ERR | RLCS_CRC;\r |
| 522 | } /* end for */\r |
| 523 | } /* end wcheck */\r |
| 524 | \r |
| 525 | rlmp = (rlmp + wc) & 0177777; /* final word count */\r |
| 526 | if (rlmp != 0) rlcs = rlcs | RLCS_ERR | RLCS_INCMP; /* completed? */\r |
| 527 | ma = ma + (wc << 1); /* final byte addr */\r |
| 528 | rlbae = (ma >> 16) & RLBAE_IMP; /* upper 6b */\r |
| 529 | rlba = ma & RLBA_IMP; /* lower 16b */\r |
| 530 | rlcs = (rlcs & ~RLCS_MEX) | ((rlbae & RLCS_M_MEX) << RLCS_V_MEX);\r |
| 531 | rlda = rlda + ((wc + (RL_NUMWD - 1)) / RL_NUMWD);\r |
| 532 | rl_set_done (0);\r |
| 533 | \r |
| 534 | if (err != 0) { /* error? */\r |
| 535 | perror ("RL I/O error");\r |
| 536 | clearerr (uptr->fileref);\r |
| 537 | return SCPE_IOERR;\r |
| 538 | }\r |
| 539 | return SCPE_OK;\r |
| 540 | }\r |
| 541 | \r |
| 542 | /* Set done and possibly errors */\r |
| 543 | \r |
| 544 | void rl_set_done (int32 status)\r |
| 545 | {\r |
| 546 | rlcs = rlcs | status | CSR_DONE; /* set done */\r |
| 547 | if (rlcs & CSR_IE) SET_INT (RL);\r |
| 548 | else CLR_INT (RL);\r |
| 549 | return;\r |
| 550 | }\r |
| 551 | \r |
| 552 | /* Device reset\r |
| 553 | \r |
| 554 | Note that the RL11 does NOT recalibrate its drives on RESET\r |
| 555 | */\r |
| 556 | \r |
| 557 | t_stat rl_reset (DEVICE *dptr)\r |
| 558 | {\r |
| 559 | int32 i;\r |
| 560 | UNIT *uptr;\r |
| 561 | \r |
| 562 | rlcs = CSR_DONE;\r |
| 563 | rlda = rlba = rlbae = rlmp = rlmp1 = rlmp2 = 0;\r |
| 564 | CLR_INT (RL);\r |
| 565 | for (i = 0; i < RL_NUMDR; i++) {\r |
| 566 | uptr = rl_dev.units + i;\r |
| 567 | sim_cancel (uptr);\r |
| 568 | uptr->STAT = 0;\r |
| 569 | }\r |
| 570 | if (rlxb == NULL) rlxb = (uint16 *) calloc (RL_MAXFR, sizeof (uint16));\r |
| 571 | if (rlxb == NULL) return SCPE_MEM;\r |
| 572 | return SCPE_OK;\r |
| 573 | }\r |
| 574 | \r |
| 575 | /* Attach routine */\r |
| 576 | \r |
| 577 | t_stat rl_attach (UNIT *uptr, char *cptr)\r |
| 578 | {\r |
| 579 | uint32 p;\r |
| 580 | t_stat r;\r |
| 581 | \r |
| 582 | uptr->capac = (uptr->flags & UNIT_RL02)? RL02_SIZE: RL01_SIZE;\r |
| 583 | r = attach_unit (uptr, cptr); /* attach unit */\r |
| 584 | if (r != SCPE_OK) return r; /* error? */\r |
| 585 | uptr->TRK = 0; /* cylinder 0 */\r |
| 586 | uptr->STAT = RLDS_VCK; /* new volume */\r |
| 587 | if ((p = sim_fsize (uptr->fileref)) == 0) { /* new disk image? */\r |
| 588 | if (uptr->flags & UNIT_RO) return SCPE_OK; /* if ro, done */\r |
| 589 | return pdp11_bad_block (uptr, RL_NUMSC, RL_NUMWD);\r |
| 590 | }\r |
| 591 | if ((uptr->flags & UNIT_AUTO) == 0) return SCPE_OK; /* autosize? */\r |
| 592 | if (p > (RL01_SIZE * sizeof (int16))) {\r |
| 593 | uptr->flags = uptr->flags | UNIT_RL02;\r |
| 594 | uptr->capac = RL02_SIZE;\r |
| 595 | }\r |
| 596 | else {\r |
| 597 | uptr->flags = uptr->flags & ~UNIT_RL02;\r |
| 598 | uptr->capac = RL01_SIZE;\r |
| 599 | }\r |
| 600 | return SCPE_OK;\r |
| 601 | }\r |
| 602 | \r |
| 603 | /* Set size routine */\r |
| 604 | \r |
| 605 | t_stat rl_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)\r |
| 606 | {\r |
| 607 | if (uptr->flags & UNIT_ATT) return SCPE_ALATT;\r |
| 608 | uptr->capac = (val & UNIT_RL02)? RL02_SIZE: RL01_SIZE;\r |
| 609 | return SCPE_OK;\r |
| 610 | }\r |
| 611 | \r |
| 612 | /* Set bad block routine */\r |
| 613 | \r |
| 614 | t_stat rl_set_bad (UNIT *uptr, int32 val, char *cptr, void *desc)\r |
| 615 | {\r |
| 616 | return pdp11_bad_block (uptr, RL_NUMSC, RL_NUMWD);\r |
| 617 | }\r |
| 618 | \r |
| 619 | /* Device bootstrap */\r |
| 620 | \r |
| 621 | #if defined (VM_PDP11)\r |
| 622 | \r |
| 623 | #define BOOT_START 02000 /* start */\r |
| 624 | #define BOOT_ENTRY (BOOT_START + 002) /* entry */\r |
| 625 | #define BOOT_UNIT (BOOT_START + 010) /* unit number */\r |
| 626 | #define BOOT_CSR (BOOT_START + 020) /* CSR */\r |
| 627 | #define BOOT_LEN (sizeof (boot_rom) / sizeof (int16))\r |
| 628 | \r |
| 629 | static const uint16 boot_rom[] = {\r |
| 630 | 0042114, /* "LD" */\r |
| 631 | 0012706, BOOT_START, /* MOV #boot_start, SP */\r |
| 632 | 0012700, 0000000, /* MOV #unit, R0 */\r |
| 633 | 0010003, /* MOV R0, R3 */\r |
| 634 | 0000303, /* SWAB R3 */\r |
| 635 | 0012701, 0174400, /* MOV #RLCS, R1 ; csr */\r |
| 636 | 0012761, 0000013, 0000004, /* MOV #13, 4(R1) ; clr err */\r |
| 637 | 0052703, 0000004, /* BIS #4, R3 ; unit+gstat */\r |
| 638 | 0010311, /* MOV R3, (R1) ; issue cmd */\r |
| 639 | 0105711, /* TSTB (R1) ; wait */\r |
| 640 | 0100376, /* BPL .-2 */\r |
| 641 | 0105003, /* CLRB R3 */\r |
| 642 | 0052703, 0000010, /* BIS #10, R3 ; unit+rdhdr */\r |
| 643 | 0010311, /* MOV R3, (R1) ; issue cmd */\r |
| 644 | 0105711, /* TSTB (R1) ; wait */\r |
| 645 | 0100376, /* BPL .-2 */\r |
| 646 | 0016102, 0000006, /* MOV 6(R1), R2 ; get hdr */\r |
| 647 | 0042702, 0000077, /* BIC #77, R2 ; clr sector */\r |
| 648 | 0005202, /* INC R2 ; magic bit */\r |
| 649 | 0010261, 0000004, /* MOV R2, 4(R1) ; seek to 0 */\r |
| 650 | 0105003, /* CLRB R3 */\r |
| 651 | 0052703, 0000006, /* BIS #6, R3 ; unit+seek */\r |
| 652 | 0010311, /* MOV R3, (R1) ; issue cmd */\r |
| 653 | 0105711, /* TSTB (R1) ; wait */\r |
| 654 | 0100376, /* BPL .-2 */\r |
| 655 | 0005061, 0000002, /* CLR 2(R1) ; clr ba */\r |
| 656 | 0005061, 0000004, /* CLR 4(R1) ; clr da */\r |
| 657 | 0012761, 0177000, 0000006, /* MOV #-512., 6(R1) ; set wc */\r |
| 658 | 0105003, /* CLRB R3 */\r |
| 659 | 0052703, 0000014, /* BIS #14, R3 ; unit+read */\r |
| 660 | 0010311, /* MOV R3, (R1) ; issue cmd */\r |
| 661 | 0105711, /* TSTB (R1) ; wait */\r |
| 662 | 0100376, /* BPL .-2 */\r |
| 663 | 0042711, 0000377, /* BIC #377, (R1) */\r |
| 664 | 0005002, /* CLR R2 */\r |
| 665 | 0005003, /* CLR R3 */\r |
| 666 | 0012704, BOOT_START+020, /* MOV #START+20, R4 */\r |
| 667 | 0005005, /* CLR R5 */\r |
| 668 | 0005007 /* CLR PC */\r |
| 669 | };\r |
| 670 | \r |
| 671 | t_stat rl_boot (int32 unitno, DEVICE *dptr)\r |
| 672 | {\r |
| 673 | int32 i;\r |
| 674 | extern uint16 *M;\r |
| 675 | extern int32 saved_PC;\r |
| 676 | \r |
| 677 | for (i = 0; i < BOOT_LEN; i++) M[(BOOT_START >> 1) + i] = boot_rom[i];\r |
| 678 | M[BOOT_UNIT >> 1] = unitno & RLCS_M_DRIVE;\r |
| 679 | M[BOOT_CSR >> 1] = rl_dib.ba & DMASK;\r |
| 680 | saved_PC = BOOT_ENTRY;\r |
| 681 | return SCPE_OK;\r |
| 682 | }\r |
| 683 | \r |
| 684 | #else\r |
| 685 | \r |
| 686 | t_stat rl_boot (int32 unitno, DEVICE *dptr)\r |
| 687 | {\r |
| 688 | return SCPE_NOFNC;\r |
| 689 | }\r |
| 690 | \r |
| 691 | #endif\r |
| 692 | \r |