[simh.git] / PDP8 / pdp8_defs.h

/* pdp8_defs.h: PDP-8 simulator definitions\r
\r
   Copyright (c) 1993-2007, Robert M Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   21-Aug-07    RMS     Added FPP8 support\r
   13-Dec-06    RMS     Added TA8E support\r
   30-Oct-06    RMS     Added infinite loop stop\r
   13-Oct-03    RMS     Added TSC8-75 support\r
   04-Oct-02    RMS     Added variable device number support\r
   20-Jan-02    RMS     Fixed bug in TTx interrupt enable initialization\r
   25-Nov-01    RMS     Added RL8A support\r
   16-Sep-01    RMS     Added multiple KL support\r
   18-Mar-01    RMS     Added DF32 support\r
   15-Feb-01    RMS     Added DECtape support\r
   14-Apr-99    RMS     Changed t_addr to unsigned\r
   19-Mar-95    RMS     Added dynamic memory size\r
   02-May-94    RMS     Added non-existent memory handling\r
\r
   The author gratefully acknowledges the help of Max Burnet, Richie Lary,\r
   and Bill Haygood in resolving questions about the PDP-8\r
*/\r
\r
#ifndef _PDP8_DEFS_H_\r
#define _PDP8_DEFS_H_   0\r
\r
#include "sim_defs.h"                                   /* simulator defns */\r
\r
/* Simulator stop codes */\r
\r
#define STOP_RSRV       1                               /* must be 1 */\r
#define STOP_HALT       2                               /* HALT */\r
#define STOP_IBKPT      3                               /* breakpoint */\r
#define STOP_NOTSTD     4                               /* non-std devno */\r
#define STOP_DTOFF      5                               /* DECtape off reel */\r
#define STOP_LOOP       6                               /* infinite loop */\r
\r
/* Memory */\r
\r
#define MAXMEMSIZE      32768                           /* max memory size */\r
#define MEMSIZE         (cpu_unit.capac)                /* actual memory size */\r
#define ADDRMASK        (MAXMEMSIZE - 1)                /* address mask */\r
#define MEM_ADDR_OK(x)  (((uint32) (x)) < MEMSIZE)\r
\r
/* IOT subroutine return codes */\r
\r
#define IOT_V_SKP       12                              /* skip */\r
#define IOT_V_REASON    13                              /* reason */\r
#define IOT_SKP         (1 << IOT_V_SKP)\r
#define IOT_REASON      (1 << IOT_V_REASON)\r
#define IORETURN(f,v)   ((f)? (v): SCPE_OK)             /* stop on error */\r
\r
/* Timers */\r
\r
#define TMR_CLK         0                               /* timer 0 = clock */\r
#define TMR_TTX         1                               /* timer 1 = TTx */\r
\r
/* Device information block */\r
\r
#define DEV_MAXBLK      8                               /* max dev block */\r
#define DEV_MAX         64                              /* total devices */\r
\r
typedef struct {\r
    uint32              dev;                            /* base dev number */\r
    uint32              num;                            /* number of slots */\r
    int32               (*dsp[DEV_MAXBLK])(int32 IR, int32 dat);\r
    } DIB;\r
\r
/* Standard device numbers */\r
\r
#define DEV_PTR         001                             /* paper tape reader */\r
#define DEV_PTP         002                             /* paper tape punch */\r
#define DEV_TTI         003                             /* console input */\r
#define DEV_TTO         004                             /* console output */\r
#define DEV_CLK         013                             /* clock */\r
#define DEV_TSC         036\r
#define DEV_KJ8         040                             /* extra terminals */\r
#define DEV_FPP         055                             /* floating point */\r
#define DEV_DF          060                             /* DF32 */\r
#define DEV_RF          060                             /* RF08 */\r
#define DEV_RL          060                             /* RL8A */\r
#define DEV_LPT         066                             /* line printer */\r
#define DEV_MT          070                             /* TM8E */\r
#define DEV_CT          070                             /* TA8E */\r
#define DEV_RK          074                             /* RK8E */\r
#define DEV_RX          075                             /* RX8E/RX28 */\r
#define DEV_DTA         076                             /* TC08 */\r
#define DEV_TD8E        077                             /* TD8E */\r
\r
/* Interrupt flags\r
\r
   The interrupt flags consist of three groups:\r
\r
   1.   Devices with individual interrupt enables.  These record\r
        their interrupt requests in device_done and their enables\r
        in device_enable, and must occupy the low bit positions.\r
\r
   2.   Devices without interrupt enables.  These record their\r
        interrupt requests directly in int_req, and must occupy\r
        the middle bit positions.\r
\r
   3.   Overhead.  These exist only in int_req and must occupy the\r
        high bit positions.\r
\r
   Because the PDP-8 does not have priority interrupts, the order\r
   of devices within groups does not matter.\r
\r
   Note: all extra KL input and output interrupts must be assigned\r
   to contiguous bits.\r
*/\r
\r
#define INT_V_START     0                               /* enable start */\r
#define INT_V_LPT       (INT_V_START+0)                 /* line printer */\r
#define INT_V_PTP       (INT_V_START+1)                 /* tape punch */\r
#define INT_V_PTR       (INT_V_START+2)                 /* tape reader */\r
#define INT_V_TTO       (INT_V_START+3)                 /* terminal */\r
#define INT_V_TTI       (INT_V_START+4)                 /* keyboard */\r
#define INT_V_CLK       (INT_V_START+5)                 /* clock */\r
#define INT_V_TTO1      (INT_V_START+6)                 /* tto1 */\r
#define INT_V_TTO2      (INT_V_START+7)                 /* tto2 */\r
#define INT_V_TTO3      (INT_V_START+8)                 /* tto3 */\r
#define INT_V_TTO4      (INT_V_START+9)                 /* tto4 */\r
#define INT_V_TTI1      (INT_V_START+10)                /* tti1 */\r
#define INT_V_TTI2      (INT_V_START+11)                /* tti2 */\r
#define INT_V_TTI3      (INT_V_START+12)                /* tti3 */\r
#define INT_V_TTI4      (INT_V_START+13)                /* tti4 */\r
#define INT_V_DIRECT    (INT_V_START+14)                /* direct start */\r
#define INT_V_RX        (INT_V_DIRECT+0)                /* RX8E */\r
#define INT_V_RK        (INT_V_DIRECT+1)                /* RK8E */\r
#define INT_V_RF        (INT_V_DIRECT+2)                /* RF08 */\r
#define INT_V_DF        (INT_V_DIRECT+3)                /* DF32 */\r
#define INT_V_MT        (INT_V_DIRECT+4)                /* TM8E */\r
#define INT_V_DTA       (INT_V_DIRECT+5)                /* TC08 */\r
#define INT_V_RL        (INT_V_DIRECT+6)                /* RL8A */\r
#define INT_V_CT        (INT_V_DIRECT+7)                /* TA8E int */\r
#define INT_V_PWR       (INT_V_DIRECT+8)                /* power int */\r
#define INT_V_UF        (INT_V_DIRECT+9)                /* user int */\r
#define INT_V_TSC       (INT_V_DIRECT+10)               /* TSC8-75 int */\r
#define INT_V_FPP       (INT_V_DIRECT+11)               /* FPP8 */\r
#define INT_V_OVHD      (INT_V_DIRECT+12)               /* overhead start */\r
#define INT_V_NO_ION_PENDING (INT_V_OVHD+0)             /* ion pending */\r
#define INT_V_NO_CIF_PENDING (INT_V_OVHD+1)             /* cif pending */\r
#define INT_V_ION       (INT_V_OVHD+2)                  /* interrupts on */\r
\r
#define INT_LPT         (1 << INT_V_LPT)\r
#define INT_PTP         (1 << INT_V_PTP)\r
#define INT_PTR         (1 << INT_V_PTR)\r
#define INT_TTO         (1 << INT_V_TTO)\r
#define INT_TTI         (1 << INT_V_TTI)\r
#define INT_CLK         (1 << INT_V_CLK)\r
#define INT_TTO1        (1 << INT_V_TTO1)\r
#define INT_TTO2        (1 << INT_V_TTO2)\r
#define INT_TTO3        (1 << INT_V_TTO3)\r
#define INT_TTO4        (1 << INT_V_TTO4)\r
#define INT_TTI1        (1 << INT_V_TTI1)\r
#define INT_TTI2        (1 << INT_V_TTI2)\r
#define INT_TTI3        (1 << INT_V_TTI3)\r
#define INT_TTI4        (1 << INT_V_TTI4)\r
#define INT_RX          (1 << INT_V_RX)\r
#define INT_RK          (1 << INT_V_RK)\r
#define INT_RF          (1 << INT_V_RF)\r
#define INT_DF          (1 << INT_V_DF)\r
#define INT_MT          (1 << INT_V_MT)\r
#define INT_DTA         (1 << INT_V_DTA)\r
#define INT_RL          (1 << INT_V_RL)\r
#define INT_CT          (1 << INT_V_CT)\r
#define INT_PWR         (1 << INT_V_PWR)\r
#define INT_UF          (1 << INT_V_UF)\r
#define INT_TSC         (1 << INT_V_TSC)\r
#define INT_FPP         (1 << INT_V_FPP)\r
#define INT_NO_ION_PENDING (1 << INT_V_NO_ION_PENDING)\r
#define INT_NO_CIF_PENDING (1 << INT_V_NO_CIF_PENDING)\r
#define INT_ION         (1 << INT_V_ION)\r
#define INT_DEV_ENABLE  ((1 << INT_V_DIRECT) - 1)       /* devices w/enables */\r
#define INT_ALL         ((1 << INT_V_OVHD) - 1)         /* all interrupts */\r
#define INT_INIT_ENABLE (INT_TTI+INT_TTO+INT_PTR+INT_PTP+INT_LPT) | \\r
                        (INT_TTI1+INT_TTI2+INT_TTI3+INT_TTI4) | \\r
                        (INT_TTO1+INT_TTO2+INT_TTO3+INT_TTO4)\r
#define INT_PENDING     (INT_ION+INT_NO_CIF_PENDING+INT_NO_ION_PENDING)\r
#define INT_UPDATE      ((int_req & ~INT_DEV_ENABLE) | (dev_done & int_enable))\r
\r
/* Function prototypes */\r
\r
t_stat set_dev (UNIT *uptr, int32 val, char *cptr, void *desc);\r
t_stat show_dev (FILE *st, UNIT *uptr, int32 val, void *desc);\r
\r
#endif\r
Commit	Line	Data
	1	/* pdp8_defs.h: PDP-8 simulator definitions\r
	2	\r
	3	Copyright (c) 1993-2007, Robert M Supnik\r
	4	\r
	5	Permission is hereby granted, free of charge, to any person obtaining a\r
	6	copy of this software and associated documentation files (the "Software"),\r
	7	to deal in the Software without restriction, including without limitation\r
	8	the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
	9	and/or sell copies of the Software, and to permit persons to whom the\r
	10	Software is furnished to do so, subject to the following conditions:\r
	11	\r
	12	The above copyright notice and this permission notice shall be included in\r
	13	all copies or substantial portions of the Software.\r
	14	\r
	15	THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
	16	IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
	17	FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r
	18	ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
	19	IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
	20	CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
	21	\r
	22	Except as contained in this notice, the name of Robert M Supnik shall not be\r
	23	used in advertising or otherwise to promote the sale, use or other dealings\r
	24	in this Software without prior written authorization from Robert M Supnik.\r
	25	\r
	26	21-Aug-07 RMS Added FPP8 support\r
	27	13-Dec-06 RMS Added TA8E support\r
	28	30-Oct-06 RMS Added infinite loop stop\r
	29	13-Oct-03 RMS Added TSC8-75 support\r
	30	04-Oct-02 RMS Added variable device number support\r
	31	20-Jan-02 RMS Fixed bug in TTx interrupt enable initialization\r
	32	25-Nov-01 RMS Added RL8A support\r
	33	16-Sep-01 RMS Added multiple KL support\r
	34	18-Mar-01 RMS Added DF32 support\r
	35	15-Feb-01 RMS Added DECtape support\r
	36	14-Apr-99 RMS Changed t_addr to unsigned\r
	37	19-Mar-95 RMS Added dynamic memory size\r
	38	02-May-94 RMS Added non-existent memory handling\r
	39	\r
	40	The author gratefully acknowledges the help of Max Burnet, Richie Lary,\r
	41	and Bill Haygood in resolving questions about the PDP-8\r
	42	*/\r
	43	\r
	44	#ifndef _PDP8_DEFS_H_\r
	45	#define _PDP8_DEFS_H_ 0\r
	46	\r
	47	#include "sim_defs.h" /* simulator defns */\r
	48	\r
	49	/* Simulator stop codes */\r
	50	\r
	51	#define STOP_RSRV 1 /* must be 1 */\r
	52	#define STOP_HALT 2 /* HALT */\r
	53	#define STOP_IBKPT 3 /* breakpoint */\r
	54	#define STOP_NOTSTD 4 /* non-std devno */\r
	55	#define STOP_DTOFF 5 /* DECtape off reel */\r
	56	#define STOP_LOOP 6 /* infinite loop */\r
	57	\r
	58	/* Memory */\r
	59	\r
	60	#define MAXMEMSIZE 32768 /* max memory size */\r
	61	#define MEMSIZE (cpu_unit.capac) /* actual memory size */\r
	62	#define ADDRMASK (MAXMEMSIZE - 1) /* address mask */\r
	63	#define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)\r
	64	\r
	65	/* IOT subroutine return codes */\r
	66	\r
	67	#define IOT_V_SKP 12 /* skip */\r
	68	#define IOT_V_REASON 13 /* reason */\r
	69	#define IOT_SKP (1 << IOT_V_SKP)\r
	70	#define IOT_REASON (1 << IOT_V_REASON)\r
	71	#define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */\r
	72	\r
	73	/* Timers */\r
	74	\r
	75	#define TMR_CLK 0 /* timer 0 = clock */\r
	76	#define TMR_TTX 1 /* timer 1 = TTx */\r
	77	\r
	78	/* Device information block */\r
	79	\r
	80	#define DEV_MAXBLK 8 /* max dev block */\r
	81	#define DEV_MAX 64 /* total devices */\r
	82	\r
	83	typedef struct {\r
	84	uint32 dev; /* base dev number */\r
	85	uint32 num; /* number of slots */\r
	86	int32 (*dsp[DEV_MAXBLK])(int32 IR, int32 dat);\r
	87	} DIB;\r
	88	\r
	89	/* Standard device numbers */\r
	90	\r
	91	#define DEV_PTR 001 /* paper tape reader */\r
	92	#define DEV_PTP 002 /* paper tape punch */\r
	93	#define DEV_TTI 003 /* console input */\r
	94	#define DEV_TTO 004 /* console output */\r
	95	#define DEV_CLK 013 /* clock */\r
	96	#define DEV_TSC 036\r
	97	#define DEV_KJ8 040 /* extra terminals */\r
	98	#define DEV_FPP 055 /* floating point */\r
	99	#define DEV_DF 060 /* DF32 */\r
	100	#define DEV_RF 060 /* RF08 */\r
	101	#define DEV_RL 060 /* RL8A */\r
	102	#define DEV_LPT 066 /* line printer */\r
	103	#define DEV_MT 070 /* TM8E */\r
	104	#define DEV_CT 070 /* TA8E */\r
	105	#define DEV_RK 074 /* RK8E */\r
	106	#define DEV_RX 075 /* RX8E/RX28 */\r
	107	#define DEV_DTA 076 /* TC08 */\r
	108	#define DEV_TD8E 077 /* TD8E */\r
	109	\r
	110	/* Interrupt flags\r
	111	\r
	112	The interrupt flags consist of three groups:\r
	113	\r
	114	1. Devices with individual interrupt enables. These record\r
	115	their interrupt requests in device_done and their enables\r
	116	in device_enable, and must occupy the low bit positions.\r
	117	\r
	118	2. Devices without interrupt enables. These record their\r
	119	interrupt requests directly in int_req, and must occupy\r
	120	the middle bit positions.\r
	121	\r
	122	3. Overhead. These exist only in int_req and must occupy the\r
	123	high bit positions.\r
	124	\r
	125	Because the PDP-8 does not have priority interrupts, the order\r
	126	of devices within groups does not matter.\r
	127	\r
	128	Note: all extra KL input and output interrupts must be assigned\r
	129	to contiguous bits.\r
	130	*/\r
	131	\r
	132	#define INT_V_START 0 /* enable start */\r
	133	#define INT_V_LPT (INT_V_START+0) /* line printer */\r
	134	#define INT_V_PTP (INT_V_START+1) /* tape punch */\r
	135	#define INT_V_PTR (INT_V_START+2) /* tape reader */\r
	136	#define INT_V_TTO (INT_V_START+3) /* terminal */\r
	137	#define INT_V_TTI (INT_V_START+4) /* keyboard */\r
	138	#define INT_V_CLK (INT_V_START+5) /* clock */\r
	139	#define INT_V_TTO1 (INT_V_START+6) /* tto1 */\r
	140	#define INT_V_TTO2 (INT_V_START+7) /* tto2 */\r
	141	#define INT_V_TTO3 (INT_V_START+8) /* tto3 */\r
	142	#define INT_V_TTO4 (INT_V_START+9) /* tto4 */\r
	143	#define INT_V_TTI1 (INT_V_START+10) /* tti1 */\r
	144	#define INT_V_TTI2 (INT_V_START+11) /* tti2 */\r
	145	#define INT_V_TTI3 (INT_V_START+12) /* tti3 */\r
	146	#define INT_V_TTI4 (INT_V_START+13) /* tti4 */\r
	147	#define INT_V_DIRECT (INT_V_START+14) /* direct start */\r
	148	#define INT_V_RX (INT_V_DIRECT+0) /* RX8E */\r
	149	#define INT_V_RK (INT_V_DIRECT+1) /* RK8E */\r
	150	#define INT_V_RF (INT_V_DIRECT+2) /* RF08 */\r
	151	#define INT_V_DF (INT_V_DIRECT+3) /* DF32 */\r
	152	#define INT_V_MT (INT_V_DIRECT+4) /* TM8E */\r
	153	#define INT_V_DTA (INT_V_DIRECT+5) /* TC08 */\r
	154	#define INT_V_RL (INT_V_DIRECT+6) /* RL8A */\r
	155	#define INT_V_CT (INT_V_DIRECT+7) /* TA8E int */\r
	156	#define INT_V_PWR (INT_V_DIRECT+8) /* power int */\r
	157	#define INT_V_UF (INT_V_DIRECT+9) /* user int */\r
	158	#define INT_V_TSC (INT_V_DIRECT+10) /* TSC8-75 int */\r
	159	#define INT_V_FPP (INT_V_DIRECT+11) /* FPP8 */\r
	160	#define INT_V_OVHD (INT_V_DIRECT+12) /* overhead start */\r
	161	#define INT_V_NO_ION_PENDING (INT_V_OVHD+0) /* ion pending */\r
	162	#define INT_V_NO_CIF_PENDING (INT_V_OVHD+1) /* cif pending */\r
	163	#define INT_V_ION (INT_V_OVHD+2) /* interrupts on */\r
	164	\r
	165	#define INT_LPT (1 << INT_V_LPT)\r
	166	#define INT_PTP (1 << INT_V_PTP)\r
	167	#define INT_PTR (1 << INT_V_PTR)\r
	168	#define INT_TTO (1 << INT_V_TTO)\r
	169	#define INT_TTI (1 << INT_V_TTI)\r
	170	#define INT_CLK (1 << INT_V_CLK)\r
	171	#define INT_TTO1 (1 << INT_V_TTO1)\r
	172	#define INT_TTO2 (1 << INT_V_TTO2)\r
	173	#define INT_TTO3 (1 << INT_V_TTO3)\r
	174	#define INT_TTO4 (1 << INT_V_TTO4)\r
	175	#define INT_TTI1 (1 << INT_V_TTI1)\r
	176	#define INT_TTI2 (1 << INT_V_TTI2)\r
	177	#define INT_TTI3 (1 << INT_V_TTI3)\r
	178	#define INT_TTI4 (1 << INT_V_TTI4)\r
	179	#define INT_RX (1 << INT_V_RX)\r
	180	#define INT_RK (1 << INT_V_RK)\r
	181	#define INT_RF (1 << INT_V_RF)\r
	182	#define INT_DF (1 << INT_V_DF)\r
	183	#define INT_MT (1 << INT_V_MT)\r
	184	#define INT_DTA (1 << INT_V_DTA)\r
	185	#define INT_RL (1 << INT_V_RL)\r
	186	#define INT_CT (1 << INT_V_CT)\r
	187	#define INT_PWR (1 << INT_V_PWR)\r
	188	#define INT_UF (1 << INT_V_UF)\r
	189	#define INT_TSC (1 << INT_V_TSC)\r
	190	#define INT_FPP (1 << INT_V_FPP)\r
	191	#define INT_NO_ION_PENDING (1 << INT_V_NO_ION_PENDING)\r
	192	#define INT_NO_CIF_PENDING (1 << INT_V_NO_CIF_PENDING)\r
	193	#define INT_ION (1 << INT_V_ION)\r
	194	#define INT_DEV_ENABLE ((1 << INT_V_DIRECT) - 1) /* devices w/enables */\r
	195	#define INT_ALL ((1 << INT_V_OVHD) - 1) /* all interrupts */\r
	196	#define INT_INIT_ENABLE (INT_TTI+INT_TTO+INT_PTR+INT_PTP+INT_LPT) \| \\r
	197	(INT_TTI1+INT_TTI2+INT_TTI3+INT_TTI4) \| \\r
	198	(INT_TTO1+INT_TTO2+INT_TTO3+INT_TTO4)\r
	199	#define INT_PENDING (INT_ION+INT_NO_CIF_PENDING+INT_NO_ION_PENDING)\r
	200	#define INT_UPDATE ((int_req & ~INT_DEV_ENABLE) \| (dev_done & int_enable))\r
	201	\r
	202	/* Function prototypes */\r
	203	\r
	204	t_stat set_dev (UNIT uptr, int32 val, char cptr, void *desc);\r
	205	t_stat show_dev (FILE st, UNIT uptr, int32 val, void *desc);\r
	206	\r
	207	#endif\r