| 1 | The IBM System/3 simulator is configured as follows:\r |
| 2 | \r |
| 3 | CPU 5410 (Model 10) CPU with 64KB of memory.\r |
| 4 | PKB 5471 Printer/Keyboard console.\r |
| 5 | CDR 1442 Card Reader\r |
| 6 | CDP 1442 Card Punch \r |
| 7 | CDP2 1442 2nd stacker \r |
| 8 | LPT 1403 Line Printer\r |
| 9 | R1 5444 Top Drive (removeable)\r |
| 10 | F1 5444 Top Drive (fixed)\r |
| 11 | R2 5444 Bottom Drive (removeable)\r |
| 12 | F2 5444 Bottom Drive (fixed\r |
| 13 | \r |
| 14 | The only CPU options are to set Model 15 mode (not implemented), DPF\r |
| 15 | (Dual Programming Facility, not implemented), and the memory size 8K, 16K,\r |
| 16 | 32K, 48K, or 64K.\r |
| 17 | \r |
| 18 | CPU registers are the standard System/3 set:\r |
| 19 | \r |
| 20 | name size Description\r |
| 21 | \r |
| 22 | IAR-P1 16 Instruction Address Register for Program Level 1\r |
| 23 | ARR-P2 16 Address Recall Register for Program Level 1\r |
| 24 | IAR-P2 16 IAR for Program Level 2 (not implemented)\r |
| 25 | ARR-P2 16 ARR for Program Level 2 (not implemented)\r |
| 26 | AAR 16 A-Address Register\r |
| 27 | BAR 16 B-Address Register\r |
| 28 | PSR 16 Program Status Register\r |
| 29 | XR1 16 Index Register 1\r |
| 30 | XR2 16 Index Register 2\r |
| 31 | IAR<0:7> 16 IAR for interrupt level 0 thru 7\r |
| 32 | ARR<0:7> 16 ARR for interrupt level 0 thru 7\r |
| 33 | \r |
| 34 | Plus these simulator registers:\r |
| 35 | \r |
| 36 | IAR 16 Value of last IAR used.\r |
| 37 | LEVEL 8 Current operating level (8=P1, 9=P2,\r |
| 38 | 0 thru 7 = Interrupt level)\r |
| 39 | SR 16 Front Panel switches\r |
| 40 | INT 16 Interrupt Request Flags\r |
| 41 | WRU 8 Simulator Interrupt Character\r |
| 42 | BREAK 17 Breakpoint Address\r |
| 43 | DEBUG 16 Debugging bits:\r |
| 44 | 0x01: Write all instructions executed to\r |
| 45 | file trace.log.\r |
| 46 | 0x02: Write details of all Disk I/O \r |
| 47 | requests to trace.log.\r |
| 48 | 0x80: Breakpoint on first character\r |
| 49 | written to 5471 printer.\r |
| 50 | \r |
| 51 | 1 5471 Printer/Keyboard\r |
| 52 | \r |
| 53 | This is the operator console. It has the following registers:\r |
| 54 | \r |
| 55 | FLAG 5471 Flag Bytes\r |
| 56 | IBUF: Input character from keyboard\r |
| 57 | OBUF: Output character to printer\r |
| 58 | POS: Number of characters printed\r |
| 59 | TIME: Delay for device operation\r |
| 60 | REQKEY: ASCII value of key mapped to 5471 REQUEST key\r |
| 61 | RTNKEY: ASCII value of key mapped to 5471 RETURN key\r |
| 62 | ENDKEY: ASCII value of key mapped to 5471 END key\r |
| 63 | CANKEY: ASCII value of key mapped to 5471 CANCEL key\r |
| 64 | \r |
| 65 | \r |
| 66 | 2 1442 Card Reader. This reader reads 80-column cards; the input\r |
| 67 | is usually an ASCII file which is translated to EBCDIC when read,\r |
| 68 | but optionally can be a binary file in EBCDIC format (such as an\r |
| 69 | object program).\r |
| 70 | \r |
| 71 | LAST Last card switch\r |
| 72 | ERR Card Reader Error\r |
| 73 | NOTRDY 1442 reader not ready (not attached or past EOF)\r |
| 74 | DAR Data Address Register (shared with punch)\r |
| 75 | LCR Length Count Register (shared with punch)\r |
| 76 | EBCDIC EBCDIC mode flag: if 1, input is 80-col EBCDIC binary.\r |
| 77 | (IPL from 1442 automatically sets this to 1).\r |
| 78 | S2 Stacker 2 is selected when this is 1\r |
| 79 | POS Number of cards read\r |
| 80 | TIME Device Delay\r |
| 81 | \r |
| 82 | The real hardware 1442 had only 1 hopper for cards, whether\r |
| 83 | these were used for blank cards for punching, or cards to be\r |
| 84 | read. Cards could be read without a feed cycle, then\r |
| 85 | punched. When punching cards, the SCP does a read of a card,\r |
| 86 | makes sure it is blank, and then punches it. To simulate\r |
| 87 | this without requiring that a stack of blank lines be attached\r |
| 88 | to the card reader device, a special feature of the simulator\r |
| 89 | is this: if no file is attached to the cdr device, but a file\r |
| 90 | is attached to the cdp or the cdp2 devices, any read from the\r |
| 91 | reader will return a blank card -- i.e. when punching, an\r |
| 92 | unattached cdr device is assumed to be loaded with an unlimited\r |
| 93 | supply of blank cards.\r |
| 94 | \r |
| 95 | \r |
| 96 | 3 1442 Card Punch. Normally cards are written to the attached\r |
| 97 | disk file as ASCII with newline/cr delimiters. But an optional\r |
| 98 | flag allows writing as 80-column binary EBCDIC.\r |
| 99 | \r |
| 100 | ERR Card Punch Error\r |
| 101 | EBCDIC When this is 1, output will be 80-col EBCDIC.\r |
| 102 | S2 When this is 1, output is placed in stacker 2\r |
| 103 | NOTRDY 1442 punch not ready (not attached)\r |
| 104 | DAR Data Address Register (shared with reader)\r |
| 105 | LCR Length Count Register (shared with reader)\r |
| 106 | POS Number of cards punched\r |
| 107 | TIME Device Delay\r |
| 108 | \r |
| 109 | 4 1442 Stacker 2. When cards are to be punched in stacker 2,\r |
| 110 | attach a disk file to this device (cdp2) to hold that output.\r |
| 111 | Note: When SCP punches cards, the default is to punch in\r |
| 112 | stacker 2.\r |
| 113 | \r |
| 114 | POS0 Number of cards punched.\r |
| 115 | \r |
| 116 | 5 1403 Printer. This is a 132-column output device, emulating\r |
| 117 | the famous IBM 1403, models 2, 6, and N1. Output is always\r |
| 118 | translated to ASCII with newline/CR delimiters. Page advance\r |
| 119 | is output as a form feed.\r |
| 120 | \r |
| 121 | ERR 1403 error flags\r |
| 122 | LPDAR Data Address Register\r |
| 123 | LPFLR Forms Length Register\r |
| 124 | LPIAR Image Address Register\r |
| 125 | LINECT Current Line on form\r |
| 126 | POS Number of lines printed\r |
| 127 | \r |
| 128 | 6 5444 Disk Drives (R1, R2, F1, F2)\r |
| 129 | \r |
| 130 | The 5444 came as a set of two drives, each with two disks. The\r |
| 131 | top disk in a drive was removable, the bottom fixed. The first\r |
| 132 | drive consists of disks R1 and F1, the second drive R2 and F2.\r |
| 133 | Each disk holds 2,467,600 bytes of user data, plus 3 alternate\r |
| 134 | tracks and a CE track. Flagging of alternate tracks is not\r |
| 135 | supported in this version of the simulator.\r |
| 136 | \r |
| 137 | NOTRDY Drive not ready (not attached)\r |
| 138 | SEEK Drive is busy with a seek operation\r |
| 139 | DAR Data Address Register\r |
| 140 | CAR Control Address Register\r |
| 141 | ERR Error Flags (16 bits)\r |
| 142 | CYL Current Cylinder (0 thru 203)\r |
| 143 | HEAD Current head (0 or 1)\r |
| 144 | POS Current position in attached disk file\r |
| 145 | TIME Device Delay\r |
| 146 | \r |
| 147 | 7 Symbolic Display and Input\r |
| 148 | \r |
| 149 | The System/3 Simulator supports symbolic display and input.\r |
| 150 | Display is controlled by command line switches:\r |
| 151 | \r |
| 152 | (none) display as hex EBCDIC\r |
| 153 | -c display bytes as characters\r |
| 154 | -m display instruction mnemonics.\r |
| 155 | -a display a 256-byte block of memory in both hex and ASCII.\r |
| 156 | \r |
| 157 | The symbolic format contains the same elements as the machine\r |
| 158 | language operation, but not always in the same order. The\r |
| 159 | operation code frequently specifies both the opcode and the Q byte,\r |
| 160 | and the top nybble of the opcode is determined by the format of the\r |
| 161 | addresses.\r |
| 162 | \r |
| 163 | Addresses take two forms: the direct address in hex, or a relative\r |
| 164 | address specified thusly: (byte,XRx) where 'byte' is a 1-byte\r |
| 165 | offset, and XRx is either XR1 or XR2 for the two index registers. \r |
| 166 | Use these formats when 'address' is indicated below:\r |
| 167 | \r |
| 168 | When 'reg' is mentioned, a mnemonic may be used for the register,\r |
| 169 | thusly:\r |
| 170 | \r |
| 171 | IAR Instruction Address Register for the current program level\r |
| 172 | ARR Address Recall Register for the current program level\r |
| 173 | P1IAR IAR for Program Level 1\r |
| 174 | P2IAR IAR for Program Level 2\r |
| 175 | PSR Program Status Register\r |
| 176 | XR1 Index Register 1\r |
| 177 | XR2 Index Register 2\r |
| 178 | IARx IAR for the interrupt level x (x = 0 thru 7)\r |
| 179 | \r |
| 180 | All other operands mentioned below are single-byte hex, except for\r |
| 181 | the length (len) operand of the two-address instructions, which is a\r |
| 182 | decimal length in the range 1-256.\r |
| 183 | \r |
| 184 | In operations where there is a source and a destination, the \r |
| 185 | destination is always operand 1, the source is operand 2.\r |
| 186 | \r |
| 187 | No-address formats:\r |
| 188 | ------------------\r |
| 189 | \r |
| 190 | HPL hex,hex Halt Program Level, the operands are the\r |
| 191 | Q and R bytes.\r |
| 192 | \r |
| 193 | \r |
| 194 | One-address formats:\r |
| 195 | -------------------\r |
| 196 | \r |
| 197 | A reg,address Add to register\r |
| 198 | CLI address,byte Compare Logical Immediate\r |
| 199 | MVI address,byte Move Immediate\r |
| 200 | TBF address,mask Test Bits Off\r |
| 201 | TBN address,mask Test Bits On\r |
| 202 | SBF address,mask Set Bits Off\r |
| 203 | SBN address,mask Set Bits On\r |
| 204 | ST reg,address Store Register\r |
| 205 | L reg,address Load Register\r |
| 206 | LA reg,address Load Address (reg can only be XR1 or XR2)\r |
| 207 | JC address,cond Jump on Condition\r |
| 208 | BC address,cond Branch on Condition\r |
| 209 | \r |
| 210 | These operations do not specify a qbyte, it is implicit in the\r |
| 211 | opcode:\r |
| 212 | \r |
| 213 | B address Unconditional branch to address\r |
| 214 | BE address Branch Equal\r |
| 215 | BNE address Branch Not Equal\r |
| 216 | BH address Branch High\r |
| 217 | BNH address Branch Not High\r |
| 218 | BL address Branch Low\r |
| 219 | BNL address Branch Not Low\r |
| 220 | BT address Branch True\r |
| 221 | BF address Branch False\r |
| 222 | BP address Branch Plus\r |
| 223 | BM address Branch Minus\r |
| 224 | BNP address Branch Not Plus\r |
| 225 | BNM address Branch Not Minus\r |
| 226 | BZ address Branch Zero\r |
| 227 | BNZ address Branch Not Zero\r |
| 228 | BOZ address Branch Overflow Zoned\r |
| 229 | BOL address Branch Overflow Logical\r |
| 230 | BNOZ address Branch No Overflow Zoned\r |
| 231 | BNOL address Branch No Overflow Logical\r |
| 232 | NOPB address No - never branch\r |
| 233 | \r |
| 234 | (substitute J for B above for a set of Jumps -- 1-byte operand (not\r |
| 235 | 2), always jumps forward up to 255 bytes from the address following\r |
| 236 | the Jump instruction. In this case, 'address' cannot be less than\r |
| 237 | the current address, nor greater than the current address + 255)\r |
| 238 | \r |
| 239 | Two-address formats (first address is destination, len is decimal 1-256):\r |
| 240 | -------------------\r |
| 241 | \r |
| 242 | MVC address,address,len Move Characters\r |
| 243 | CLC address,address,len Compare Logical Characters\r |
| 244 | ALC address,address,len Add Logical Characters\r |
| 245 | SLC address,address,len Subtract Logical Characters\r |
| 246 | ED address,address,len Edit\r |
| 247 | ITC address,address,len Insert and Test Characters\r |
| 248 | AZ address,address,len Add Zoned Decimal\r |
| 249 | SZ address,address,len Subtract Zoned Decimal\r |
| 250 | \r |
| 251 | MNN address,address Move Numeric to Numeric\r |
| 252 | MNZ address,address Move Numeric to Zone\r |
| 253 | MZZ address,address Move Zone to Zone\r |
| 254 | MZN address,address Move Zone to Numeric\r |
| 255 | \r |
| 256 | I/O Format\r |
| 257 | ----------\r |
| 258 | \r |
| 259 | In the I/O format, there are always 3 fields:\r |
| 260 | \r |
| 261 | da - Device Address 0-15 (decimal)\r |
| 262 | m - Modifier 0-1\r |
| 263 | n - Function 0-7\r |
| 264 | \r |
| 265 | The meaning of these is entirely defined by the device addressed. \r |
| 266 | \r |
| 267 | There may be an optional control byte, or an optional address (based\r |
| 268 | on the type of instruction).\r |
| 269 | \r |
| 270 | SNS da,m,n,address Sense I/O\r |
| 271 | LIO da,m,n,address Load I/O\r |
| 272 | TIO da,m,n,address Test I/O\r |
| 273 | \r |
| 274 | SIO da,m,n,cc Start I/O -- cc is a control byte\r |
| 275 | \r |
| 276 | APL da,m,n Advance Program Level \r |
| 277 | \r |
| 278 | \r |
| 279 | 8 Device Programming.\r |
| 280 | \r |
| 281 | Note: On a model 15, interrupts are used for all devices. On\r |
| 282 | other models, interrupts are only used for the printer/keyboard.\r |
| 283 | \r |
| 284 | This is a summary of the DA, M, N, and CC codes for all supported\r |
| 285 | devices:\r |
| 286 | \r |
| 287 | 5471 Printer Keyboard\r |
| 288 | ---------------------\r |
| 289 | \r |
| 290 | The PKB has 2 visible indicators: Proceed and Request\r |
| 291 | Pending. It has a normal keyboard and 4 special keys:\r |
| 292 | Request, Return, End, and Cancel.\r |
| 293 | \r |
| 294 | SIO 1,0,0,XX Start Keyboard Operation, bit masks for XX are:\r |
| 295 | X'20': Request Pending Indicator On\r |
| 296 | X'10': Proceed Indicator On\r |
| 297 | X'04': Request Key Interrupts Enable (1) Disable (0)\r |
| 298 | X'02': Other Key Interrupts Enable (1) Disable (0)\r |
| 299 | X'01': Reset request key and other key interrupts\r |
| 300 | \r |
| 301 | SIO 1,1,0,XX Start Printer Operation, bit masks for XX are:\r |
| 302 | X'80': Start Printing\r |
| 303 | X'40': Start Carrier Return\r |
| 304 | X'04': Printer Interrupt Enable(1) or Disable (0)\r |
| 305 | X'01': Reset Printer Interrupt\r |
| 306 | \r |
| 307 | LIO 1,1,0,addr Load Printer Output Character\r |
| 308 | addr is address of low-order (highest numbered)\r |
| 309 | byte of two-byte field, and high-order byte\r |
| 310 | (that is, addr - 1) is loaded into output\r |
| 311 | register to print. Printing is done one character\r |
| 312 | at a time.\r |
| 313 | \r |
| 314 | SNS 1,0,1,addr Sense Status Bytes 0 and 1:\r |
| 315 | Byte 0 (leftmost) is the character typed in\r |
| 316 | in EBCDIC.\r |
| 317 | Byte 1 is status:\r |
| 318 | X'80': Request key interrupt pending\r |
| 319 | X'40': End or Cancel key interrupt pending\r |
| 320 | X'20': Cancel key pressed\r |
| 321 | X'10': End Key Pressed\r |
| 322 | X'08': Return or data key interrupt pending\r |
| 323 | X'04': Return key pressed\r |
| 324 | \r |
| 325 | SNS 1,0,3,addr Sense Status Bytes 2 and 3: returns 0000 in\r |
| 326 | this sim.\r |
| 327 | \r |
| 328 | 1442 Reader/Punch\r |
| 329 | -----------------\r |
| 330 | \r |
| 331 | SIO 5,0,0,XX Feed Card without reading/punching\r |
| 332 | XX is stacker select for all functions: 0 = stacker\r |
| 333 | 1 (normal), 1 = stacker 2.\r |
| 334 | \r |
| 335 | SIO 5,0,1,XX Read Card\r |
| 336 | SIO 5,0,2,XX Punch and Feed\r |
| 337 | SIO 5,0,3,XX Read Column Binary\r |
| 338 | SIO 5,0,4,XX Punch with no feed\r |
| 339 | \r |
| 340 | TIO 5,0,0,addr Branch to addr if not ready or busy\r |
| 341 | TIO 5,0,2,addr Branch to addr if busy\r |
| 342 | TIO 5,0,5,addr (mod 15 only) branch if interrupt pending\r |
| 343 | \r |
| 344 | APL 5,0,0 Loop (or switch prog levels) if not ready/busy\r |
| 345 | APL 5,0,2 Loop (or switch) if busy\r |
| 346 | APL 5,0,5 Loop (or switch) if interrupt pending (mod 15 only)\r |
| 347 | \r |
| 348 | LIO 5,0,0,addr Load 2-byte field to Length Count Register\r |
| 349 | LIO 5,0,4,addr Load 2-byte field to Data Address Register\r |
| 350 | (DAR is incremented by a read/punch operation and must\r |
| 351 | be reset every card)\r |
| 352 | \r |
| 353 | SNS 5,0,1,addr Sense CE indicators (0000 returned in this sim)\r |
| 354 | SNS 5,0,2,addr Sense CE indicators (0000 returned in this sim)\r |
| 355 | SNS 5,0,3,addr Sense Status Indicators: (only simulated bits shown)\r |
| 356 | X'8000': Read Check\r |
| 357 | X'4000': Last Card\r |
| 358 | X'2000': Punch Check\r |
| 359 | X'1000': Data Overrun\r |
| 360 | X'0800': Not Ready\r |
| 361 | \r |
| 362 | \r |
| 363 | 1403 Printer\r |
| 364 | ------------\r |
| 365 | \r |
| 366 | SIO 14,0,0,XX Line space XX lines (0-3 valid in XX)\r |
| 367 | SIO 14,0,2,XX Print a line space (0-3 valid in XX)\r |
| 368 | SIO 14,0,4,XX Skip Only (line number 1-112 in XX)\r |
| 369 | \r |
| 370 | SIO 14,0,6,XX Print and Skip (line number 0-112 in XX)\r |
| 371 | \r |
| 372 | TIO 14,0,0,addr Branch to addr if not ready\r |
| 373 | TIO 14,0,2,addr Branch to addr if buffer busy\r |
| 374 | TIO 14,0,3,addr Branch to addr if interrupt pending (mod 15 only)\r |
| 375 | TIO 14,0,4,addr Branch if carriage busy\r |
| 376 | TIO 14,0,6,addr Branch if printer busy\r |
| 377 | \r |
| 378 | APL 14,0,0 Loop (or switch prog levels) if not ready/check\r |
| 379 | APL 14,0,2 Loop (or switch) if buffer busy\r |
| 380 | APL 14,0,3 Loop (or switch) if interrupt pending (mod 15 only)\r |
| 381 | APL 14,0,4 Loop (or switch) if carriage busy\r |
| 382 | APL 14,0,6 Loop (or switch) if printer busy\r |
| 383 | \r |
| 384 | LIO 14,0,0,addr Load 1 byte to Forms Length Reg at addr-1\r |
| 385 | LIO 14,0,4,addr Load 2 bytes to Chain Image Address Register\r |
| 386 | LIO 14,0,6,addr Load 2 bytes to Data Address Register\r |
| 387 | \r |
| 388 | SNS 14,0,0,addr Sense Character Count\r |
| 389 | SNS 14,0,4,addr Sense LPIAR (Image Address Register)\r |
| 390 | SNS 14,0,6,addr Sense LPDAR (data addres register)\r |
| 391 | \r |
| 392 | \r |
| 393 | 5444 Disk Drives\r |
| 394 | ----------------\r |
| 395 | \r |
| 396 | Each drive has two disks (upper and lower), each disk\r |
| 397 | has two surfaces (upper and lower), each surface has\r |
| 398 | 24 256-byte sectors, sectors are number 0 thru 23 on\r |
| 399 | upper surface, 32 thru 55 on lower.\r |
| 400 | \r |
| 401 | d = drive, 0 is R1/F1, 1 is R2/F2\r |
| 402 | s = surface, 0 = upper (removable), 1 = lower (fixed)\r |
| 403 | \r |
| 404 | The Control register points to the leftmost byte of a 4-byte\r |
| 405 | control field in memory with these bytes:\r |
| 406 | \r |
| 407 | F - Flag byte (not supported in this sim)\r |
| 408 | C - Cylinder Address (0-203)\r |
| 409 | S - Sector Number (0-23, or 32-55) in top 6 bits\r |
| 410 | N - Number of sectors minus 1\r |
| 411 | \r |
| 412 | These have meaning for all operations except seek, seek uses\r |
| 413 | the fields differently.\r |
| 414 | \r |
| 415 | SIO 1d,s,0,XX Seek, XX not used, control field is used:\r |
| 416 | \r |
| 417 | F - not used\r |
| 418 | C - not used\r |
| 419 | S - high bit is head to be used 0-upper 1-lower\r |
| 420 | low bit is direction to move 0-back 1-forward\r |
| 421 | N - number of cylinders to move\r |
| 422 | \r |
| 423 | SIO 1d,s,1,XX Read, values of XX are as follows:\r |
| 424 | X'00': Read Data\r |
| 425 | X'01': Read Identifier (updates control field, no\r |
| 426 | data is read)\r |
| 427 | X'02': Read Data Diagnostic\r |
| 428 | X'03': Verify (does not read, but checks)\r |
| 429 | \r |
| 430 | SIO 1d,s,2,XX Write, values of XX are as follows:\r |
| 431 | X'00': Write Data\r |
| 432 | X'01': Write Identifier (24 sectors with byte at\r |
| 433 | data address register)\r |
| 434 | \r |
| 435 | SIO 1d,s,3,XX Scan. All 256 bytes in memory at data\r |
| 436 | address register are compared to disk\r |
| 437 | sectors on current track, except those\r |
| 438 | bytes of X'FF' are not compared. Values of\r |
| 439 | XX are:\r |
| 440 | \r |
| 441 | X'00': Scan Equal\r |
| 442 | X'01': Scan Low or Equal\r |
| 443 | X'02': Scan High or Equal\r |
| 444 | \r |
| 445 | LIO 1d,0,4,addr Load Data Address Register\r |
| 446 | LIO 1d,0,6,addr Load Disk Control Address Register\r |
| 447 | \r |
| 448 | TIO 1d,0,0,addr Branch if not ready/unit check\r |
| 449 | TIO 1d,0,2,addr Branch if busy\r |
| 450 | TIO 1d,0,4,addr Branch if Scan Found\r |
| 451 | \r |
| 452 | APL 1d,0,0 Loop if not ready/unit check\r |
| 453 | APL 1d,0,2 Loop if busy\r |
| 454 | APL 1d,0,4 Loop if scan found\r |
| 455 | \r |
| 456 | SNS 1d,0,2,addr Sense Status Bytes 0 and 1: (simulated \r |
| 457 | bits only are shown, otehrs are 0):\r |
| 458 | X'1000': equipment check\r |
| 459 | X'0800': data check\r |
| 460 | X'0400': No record found\r |
| 461 | X'0100': Seek Check (past cyl 203)\r |
| 462 | X'0080': Scan equal Hit\r |
| 463 | X'0040': Cylinder 0\r |
| 464 | X'0020': End of Cylinder \r |
| 465 | X'0010': Seek Busy\r |
| 466 | SNS 1d,0,3,addr Sense bytes 2 and 3 (0000 in this sim)\r |
| 467 | SNS 1d,0,4,addr Sense Data Address Register\r |
| 468 | SNS 1d,0,6,addr Sense Control Address Register\r |
| 469 | \r |
| 470 | \r |
| 471 | \r |
| 472 | \r |