| 1 | /* vaxmod_defs.h: VAX model-specific definitions file\r |
| 2 | \r |
| 3 | Copyright (c) 1998-2007, Robert M Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | 29-Apr-07 RMS Separated checks for PxBR and SBR\r |
| 27 | 17-May-06 RMS Added CR11/CD11 support\r |
| 28 | 10-May-06 RMS Added NOP'd reserved operand checking macros\r |
| 29 | 05-Oct-05 RMS Added XU definitions for autoconfigure\r |
| 30 | 15-Jun-05 RMS Added QDSS support\r |
| 31 | 12-Sep-04 RMS Removed map_address prototype\r |
| 32 | 16-Jun-04 RMS Added DHQ11 support\r |
| 33 | 21-Mar-04 RMS Added RXV21 support\r |
| 34 | 25-Jan-04 RMS Removed local debug logging support\r |
| 35 | RMS,MP Added "KA655X" support\r |
| 36 | 29-Dec-03 RMS Added Q18 definition for PDP11 compatibility\r |
| 37 | 22-Dec-02 RMS Added BDR halt enable definition\r |
| 38 | 11-Nov-02 RMS Added log bits for XQ\r |
| 39 | 10-Oct-02 RMS Added DEQNA/DELQA, multiple RQ, autoconfigure support\r |
| 40 | 29-Sep-02 RMS Revamped bus support macros\r |
| 41 | 06-Sep-02 RMS Added TMSCP support\r |
| 42 | 14-Jul-02 RMS Added additional console halt codes\r |
| 43 | 28-Apr-02 RMS Fixed DZV vector base and number of lines\r |
| 44 | \r |
| 45 | This file covers the KA65x ("Mayfair") series of CVAX-based Qbus systems.\r |
| 46 | The simulator defines an extended physical memory variant of the KA655,\r |
| 47 | called the KA655X. It has a maximum memory size of 512MB instead of 64MB.\r |
| 48 | \r |
| 49 | System memory map\r |
| 50 | \r |
| 51 | 0000 0000 - 03FF FFFF main memory (KA655)\r |
| 52 | 0400 0000 - 0FFF FFFF reserved (KA655), main memory (KA655X)\r |
| 53 | 1000 0000 - 13FF FFFF cache diagnostic space (KA655), main memory (KA655X)\r |
| 54 | 1400 0000 - 1FFF FFFF reserved (KA655), main memory (KA655X)\r |
| 55 | \r |
| 56 | 2000 0000 - 2000 1FFF Qbus I/O page\r |
| 57 | 2000 2000 - 2003 FFFF reserved\r |
| 58 | 2004 0000 - 2005 FFFF ROM space, halt protected\r |
| 59 | 2006 0000 - 2007 FFFF ROM space, halt unprotected\r |
| 60 | 2008 0000 - 201F FFFF Local register space\r |
| 61 | 2020 0000 - 2FFF FFFF reserved\r |
| 62 | 3000 0000 - 303F FFFF Qbus memory space\r |
| 63 | 3400 0000 - 3FFF FFFF reserved\r |
| 64 | */\r |
| 65 | \r |
| 66 | #ifdef FULL_VAX /* subset VAX */\r |
| 67 | #undef FULL_VAX\r |
| 68 | #endif\r |
| 69 | \r |
| 70 | #ifndef _VAXMOD_DEFS_H_\r |
| 71 | #define _VAXMOD_DEFS_H_ 1\r |
| 72 | \r |
| 73 | /* Microcode constructs */\r |
| 74 | \r |
| 75 | #define CVAX_SID (10 << 24) /* system ID */\r |
| 76 | #define CVAX_UREV 6 /* ucode revision */\r |
| 77 | #define CON_HLTPIN 0x0200 /* external CPU halt */\r |
| 78 | #define CON_PWRUP 0x0300 /* powerup code */\r |
| 79 | #define CON_HLTINS 0x0600 /* HALT instruction */\r |
| 80 | #define CON_BADPSL 0x4000 /* invalid PSL flag */\r |
| 81 | #define CON_MAPON 0x8000 /* mapping on flag */\r |
| 82 | #define MCHK_TBM_P0 0x05 /* PPTE in P0 */\r |
| 83 | #define MCHK_TBM_P1 0x06 /* PPTE in P1 */\r |
| 84 | #define MCHK_M0_P0 0x07 /* PPTE in P0 */\r |
| 85 | #define MCHK_M0_P1 0x08 /* PPTE in P1 */\r |
| 86 | #define MCHK_INTIPL 0x09 /* invalid ireq */\r |
| 87 | #define MCHK_READ 0x80 /* read check */\r |
| 88 | #define MCHK_WRITE 0x82 /* write check */\r |
| 89 | \r |
| 90 | /* Machine specific IPRs */\r |
| 91 | \r |
| 92 | #define MT_CADR 37\r |
| 93 | #define MT_MSER 39\r |
| 94 | #define MT_CONPC 42\r |
| 95 | #define MT_CONPSL 43\r |
| 96 | #define MT_IORESET 55\r |
| 97 | \r |
| 98 | /* Memory system error register */\r |
| 99 | \r |
| 100 | #define MSER_HM 0x80 /* hit/miss */\r |
| 101 | #define MSER_CPE 0x40 /* CDAL par err */\r |
| 102 | #define MSER_CPM 0x20 /* CDAL mchk */\r |
| 103 | \r |
| 104 | /* Cache disable register */\r |
| 105 | \r |
| 106 | #define CADR_RW 0xF3\r |
| 107 | #define CADR_MBO 0x0C\r |
| 108 | \r |
| 109 | /* Memory */\r |
| 110 | \r |
| 111 | #define MAXMEMWIDTH 26 /* max mem, std KA655 */\r |
| 112 | #define MAXMEMSIZE (1 << MAXMEMWIDTH) /* max mem size */\r |
| 113 | #define MAXMEMWIDTH_X 29 /* max mem, KA655X */\r |
| 114 | #define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X)\r |
| 115 | #define INITMEMSIZE (1 << 24) /* initial memory size */\r |
| 116 | #define MEMSIZE (cpu_unit.capac)\r |
| 117 | #define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE)\r |
| 118 | \r |
| 119 | /* Cache diagnostic space */\r |
| 120 | \r |
| 121 | #define CDAAWIDTH 16 /* cache dat addr width */\r |
| 122 | #define CDASIZE (1u << CDAAWIDTH) /* cache dat length */\r |
| 123 | #define CDAMASK (CDASIZE - 1) /* cache dat mask */\r |
| 124 | #define CTGAWIDTH 10 /* cache tag addr width */\r |
| 125 | #define CTGSIZE (1u << CTGAWIDTH) /* cache tag length */\r |
| 126 | #define CTGMASK (CTGSIZE - 1) /* cache tag mask */\r |
| 127 | #define CDGSIZE (CDASIZE * CTGSIZE) /* diag addr length */\r |
| 128 | #define CDGBASE 0x10000000 /* diag addr base */\r |
| 129 | #define CDG_GETROW(x) (((x) & CDAMASK) >> 2)\r |
| 130 | #define CDG_GETTAG(x) (((x) >> CDAAWIDTH) & CTGMASK)\r |
| 131 | #define CTG_V (1u << (CTGAWIDTH + 0)) /* tag valid */\r |
| 132 | #define CTG_WP (1u << (CTGAWIDTH + 1)) /* wrong parity */\r |
| 133 | #define ADDR_IS_CDG(x) ((((uint32) (x)) >= CDGBASE) && \\r |
| 134 | (((uint32) (x)) < (CDGBASE + CDGSIZE)))\r |
| 135 | \r |
| 136 | /* Qbus I/O registers */\r |
| 137 | \r |
| 138 | #define IOPAGEAWIDTH 13 /* IO addr width */\r |
| 139 | #define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */\r |
| 140 | #define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */\r |
| 141 | #define IOPAGEBASE 0x20000000 /* IO page base */\r |
| 142 | #define ADDR_IS_IO(x) ((((uint32) (x)) >= IOPAGEBASE) && \\r |
| 143 | (((uint32) (x)) < (IOPAGEBASE + IOPAGESIZE)))\r |
| 144 | \r |
| 145 | /* Read only memory - appears twice */\r |
| 146 | \r |
| 147 | #define ROMAWIDTH 17 /* ROM addr width */\r |
| 148 | #define ROMSIZE (1u << ROMAWIDTH) /* ROM length */\r |
| 149 | #define ROMAMASK (ROMSIZE - 1) /* ROM addr mask */\r |
| 150 | #define ROMBASE 0x20040000 /* ROM base */\r |
| 151 | #define ADDR_IS_ROM(x) ((((uint32) (x)) >= ROMBASE) && \\r |
| 152 | (((uint32) (x)) < (ROMBASE + ROMSIZE + ROMSIZE)))\r |
| 153 | \r |
| 154 | /* Local register space */\r |
| 155 | \r |
| 156 | #define REGAWIDTH 19 /* REG addr width */\r |
| 157 | #define REGSIZE (1u << REGAWIDTH) /* REG length */\r |
| 158 | #define REGBASE 0x20080000 /* REG addr base */\r |
| 159 | \r |
| 160 | /* KA655 board registers */\r |
| 161 | \r |
| 162 | #define KAAWIDTH 3 /* KA reg width */\r |
| 163 | #define KASIZE (1u << KAAWIDTH) /* KA reg length */\r |
| 164 | #define KABASE (REGBASE + 0x4000) /* KA650 addr base */\r |
| 165 | \r |
| 166 | /* CQBIC registers */\r |
| 167 | \r |
| 168 | #define CQBICSIZE (5 << 2) /* 5 registers */\r |
| 169 | #define CQBICBASE (REGBASE) /* CQBIC addr base */\r |
| 170 | #define CQMAPASIZE 15 /* map addr width */\r |
| 171 | #define CQMAPSIZE (1u << CQMAPASIZE) /* map length */\r |
| 172 | #define CQMAPAMASK (CQMAPSIZE - 1) /* map addr mask */\r |
| 173 | #define CQMAPBASE (REGBASE + 0x8000) /* map addr base */\r |
| 174 | #define CQIPCSIZE 2 /* 2 bytes only */\r |
| 175 | #define CQIPCBASE (REGBASE + 0x1F40) /* ipc reg addr */\r |
| 176 | \r |
| 177 | /* CMCTL registers */\r |
| 178 | \r |
| 179 | /* #define CMCTLSIZE (18 << 2) /* 18 registers */\r |
| 180 | #define CMCTLSIZE (19 << 2) /* KA655X extra reg */\r |
| 181 | #define CMCTLBASE (REGBASE + 0x100) /* CMCTL addr base */\r |
| 182 | \r |
| 183 | /* SSC registers */\r |
| 184 | \r |
| 185 | #define SSCSIZE 0x150 /* SSC size */\r |
| 186 | #define SSCBASE 0x20140000 /* SSC base */\r |
| 187 | \r |
| 188 | /* Non-volatile RAM - 1KB long */\r |
| 189 | \r |
| 190 | #define NVRAWIDTH 10 /* NVR addr width */\r |
| 191 | #define NVRSIZE (1u << NVRAWIDTH) /* NVR length */\r |
| 192 | #define NVRAMASK (NVRSIZE - 1) /* NVR addr mask */\r |
| 193 | #define NVRBASE 0x20140400 /* NVR base */\r |
| 194 | #define ADDR_IS_NVR(x) ((((uint32) (x)) >= NVRBASE) && \\r |
| 195 | (((uint32) (x)) < (NVRBASE + NVRSIZE)))\r |
| 196 | \r |
| 197 | /* CQBIC Qbus memory space (seen from CVAX) */\r |
| 198 | \r |
| 199 | #define CQMAWIDTH 22 /* Qmem addr width */\r |
| 200 | #define CQMSIZE (1u << CQMAWIDTH) /* Qmem length */\r |
| 201 | #define CQMAMASK (CQMSIZE - 1) /* Qmem addr mask */\r |
| 202 | #define CQMBASE 0x30000000 /* Qmem base */\r |
| 203 | \r |
| 204 | /* Machine specific reserved operand tests (all NOPs) */\r |
| 205 | \r |
| 206 | #define ML_PA_TEST(r)\r |
| 207 | #define ML_LR_TEST(r)\r |
| 208 | #define ML_SBR_TEST(r)\r |
| 209 | #define ML_PXBR_TEST(r)\r |
| 210 | #define LP_AST_TEST(r)\r |
| 211 | #define LP_MBZ84_TEST(r)\r |
| 212 | #define LP_MBZ92_TEST(r)\r |
| 213 | \r |
| 214 | /* Qbus I/O modes */\r |
| 215 | \r |
| 216 | #define READ 0 /* PDP-11 compatibility */\r |
| 217 | #define WRITE (L_WORD)\r |
| 218 | #define WRITEB (L_BYTE)\r |
| 219 | \r |
| 220 | /* Common CSI flags */\r |
| 221 | \r |
| 222 | #define CSR_V_GO 0 /* go */\r |
| 223 | #define CSR_V_IE 6 /* interrupt enable */\r |
| 224 | #define CSR_V_DONE 7 /* done */\r |
| 225 | #define CSR_V_BUSY 11 /* busy */\r |
| 226 | #define CSR_V_ERR 15 /* error */\r |
| 227 | #define CSR_GO (1u << CSR_V_GO)\r |
| 228 | #define CSR_IE (1u << CSR_V_IE)\r |
| 229 | #define CSR_DONE (1u << CSR_V_DONE)\r |
| 230 | #define CSR_BUSY (1u << CSR_V_BUSY)\r |
| 231 | #define CSR_ERR (1u << CSR_V_ERR)\r |
| 232 | \r |
| 233 | /* Timers */\r |
| 234 | \r |
| 235 | #define TMR_CLK 0 /* 100Hz clock */\r |
| 236 | \r |
| 237 | /* I/O system definitions */\r |
| 238 | \r |
| 239 | #define DZ_MUXES 4 /* max # of DZV muxes */\r |
| 240 | #define DZ_LINES 4 /* lines per DZV mux */\r |
| 241 | #define VH_MUXES 4 /* max # of DHQ muxes */\r |
| 242 | #define MT_MAXFR (1 << 16) /* magtape max rec */\r |
| 243 | #define AUTO_LNT 34 /* autoconfig ranks */\r |
| 244 | \r |
| 245 | #define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */\r |
| 246 | #define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */\r |
| 247 | #define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus, mem <= 256KB */\r |
| 248 | #define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */\r |
| 249 | #define DEV_UBUS (1u << DEV_V_UBUS)\r |
| 250 | #define DEV_QBUS (1u << DEV_V_QBUS)\r |
| 251 | #define DEV_Q18 (1u << DEV_V_Q18)\r |
| 252 | #define DEV_FLTA (1u << DEV_V_FLTA)\r |
| 253 | \r |
| 254 | #define UNIBUS FALSE /* 22b only */\r |
| 255 | \r |
| 256 | #define DEV_RDX 16 /* default device radix */\r |
| 257 | \r |
| 258 | /* Device information block */\r |
| 259 | \r |
| 260 | #define VEC_DEVMAX 4 /* max device vec */\r |
| 261 | \r |
| 262 | typedef struct {\r |
| 263 | uint32 ba; /* base addr */\r |
| 264 | uint32 lnt; /* length */\r |
| 265 | t_stat (*rd)(int32 *dat, int32 ad, int32 md);\r |
| 266 | t_stat (*wr)(int32 dat, int32 ad, int32 md);\r |
| 267 | int32 vnum; /* vectors: number */\r |
| 268 | int32 vloc; /* locator */\r |
| 269 | int32 vec; /* value */\r |
| 270 | int32 (*ack[VEC_DEVMAX])(void); /* ack routine */\r |
| 271 | } DIB;\r |
| 272 | \r |
| 273 | /* I/O page layout - RQB,RQC,RQD float based on number of DZ's */\r |
| 274 | \r |
| 275 | #define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */\r |
| 276 | #define IOLN_DZ 010\r |
| 277 | #define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2)))\r |
| 278 | #define IOLN_RQB 004\r |
| 279 | #define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB)\r |
| 280 | #define IOLN_RQC 004\r |
| 281 | #define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC)\r |
| 282 | #define IOLN_RQD 004\r |
| 283 | #define IOBA_VH (IOPAGEBASE + 000440) /* DHQ11 */\r |
| 284 | #define IOLN_VH 020\r |
| 285 | #define IOBA_RQ (IOPAGEBASE + 012150) /* RQDX3 */\r |
| 286 | #define IOLN_RQ 004\r |
| 287 | #define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */\r |
| 288 | #define IOLN_TS 004\r |
| 289 | #define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */\r |
| 290 | #define IOLN_RL 012\r |
| 291 | #define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */\r |
| 292 | #define IOLN_XQ 020\r |
| 293 | #define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */\r |
| 294 | #define IOLN_XQB 020\r |
| 295 | #define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */\r |
| 296 | #define IOLN_TQ 004\r |
| 297 | #define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */\r |
| 298 | #define IOLN_XU 010\r |
| 299 | #define IOBA_RP (IOPAGEBASE + 016700) /* RP/RM */\r |
| 300 | #define IOLN_RP 054\r |
| 301 | #define IOBA_CR (IOPAGEBASE + 017160) /* CD/CR/CM */\r |
| 302 | #define IOLN_CR 010\r |
| 303 | #define IOBA_RX (IOPAGEBASE + 017170) /* RXV11 */\r |
| 304 | #define IOLN_RX 004\r |
| 305 | #define IOBA_RY (IOPAGEBASE + 017170) /* RXV21 */\r |
| 306 | #define IOLN_RY 004\r |
| 307 | #define IOBA_QDSS (IOPAGEBASE + 017400) /* QDSS */\r |
| 308 | #define IOLN_QDSS 002\r |
| 309 | #define IOBA_DBL (IOPAGEBASE + 017500) /* doorbell */\r |
| 310 | #define IOLN_DBL 002\r |
| 311 | #define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */\r |
| 312 | #define IOLN_LPT 004\r |
| 313 | #define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */\r |
| 314 | #define IOLN_PTR 004\r |
| 315 | #define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */\r |
| 316 | #define IOLN_PTP 004\r |
| 317 | \r |
| 318 | /* The KA65x maintains 4 separate hardware IPL levels, IPL 17 to IPL 14\r |
| 319 | Within each IPL, priority is right to left\r |
| 320 | */\r |
| 321 | \r |
| 322 | /* IPL 17 */\r |
| 323 | \r |
| 324 | /* IPL 16 */\r |
| 325 | \r |
| 326 | #define INT_V_CLK 0 /* clock */\r |
| 327 | \r |
| 328 | /* IPL 15 */\r |
| 329 | \r |
| 330 | #define INT_V_RQ 0 /* RQDX3 */\r |
| 331 | #define INT_V_RL 1 /* RLV12/RL02 */\r |
| 332 | #define INT_V_DZRX 2 /* DZ11 */\r |
| 333 | #define INT_V_DZTX 3\r |
| 334 | #define INT_V_RP 4 /* RP,RM drives */\r |
| 335 | #define INT_V_TS 5 /* TS11/TSV05 */\r |
| 336 | #define INT_V_TQ 6 /* TMSCP */\r |
| 337 | #define INT_V_XQ 7 /* DEQNA/DELQA */\r |
| 338 | #define INT_V_RY 8 /* RXV21 */\r |
| 339 | \r |
| 340 | /* IPL 14 */\r |
| 341 | \r |
| 342 | #define INT_V_TTI 0 /* console */\r |
| 343 | #define INT_V_TTO 1\r |
| 344 | #define INT_V_PTR 2 /* PC11 */\r |
| 345 | #define INT_V_PTP 3\r |
| 346 | #define INT_V_LPT 4 /* LP11 */\r |
| 347 | #define INT_V_CSI 5 /* SSC cons UART */\r |
| 348 | #define INT_V_CSO 6\r |
| 349 | #define INT_V_TMR0 7 /* SSC timers */\r |
| 350 | #define INT_V_TMR1 8\r |
| 351 | #define INT_V_VHRX 9 /* DHQ11 */\r |
| 352 | #define INT_V_VHTX 10 \r |
| 353 | #define INT_V_QDSS 11 /* QDSS */\r |
| 354 | #define INT_V_CR 12\r |
| 355 | \r |
| 356 | #define INT_CLK (1u << INT_V_CLK)\r |
| 357 | #define INT_RQ (1u << INT_V_RQ)\r |
| 358 | #define INT_RL (1u << INT_V_RL)\r |
| 359 | #define INT_DZRX (1u << INT_V_DZRX)\r |
| 360 | #define INT_DZTX (1u << INT_V_DZTX)\r |
| 361 | #define INT_RP (1u << INT_V_RP)\r |
| 362 | #define INT_TS (1u << INT_V_TS)\r |
| 363 | #define INT_TQ (1u << INT_V_TQ)\r |
| 364 | #define INT_XQ (1u << INT_V_XQ)\r |
| 365 | #define INT_RY (1u << INT_V_RY)\r |
| 366 | #define INT_TTI (1u << INT_V_TTI)\r |
| 367 | #define INT_TTO (1u << INT_V_TTO)\r |
| 368 | #define INT_PTR (1u << INT_V_PTR)\r |
| 369 | #define INT_PTP (1u << INT_V_PTP)\r |
| 370 | #define INT_LPT (1u << INT_V_LPT)\r |
| 371 | #define INT_CSI (1u << INT_V_CSI)\r |
| 372 | #define INT_CSO (1u << INT_V_CSO)\r |
| 373 | #define INT_TMR0 (1u << INT_V_TMR0)\r |
| 374 | #define INT_TMR1 (1u << INT_V_TMR1)\r |
| 375 | #define INT_VHRX (1u << INT_V_VHRX)\r |
| 376 | #define INT_VHTX (1u << INT_V_VHTX)\r |
| 377 | #define INT_QDSS (1u << INT_V_QDSS)\r |
| 378 | #define INT_CR (1u << INT_V_CR)\r |
| 379 | \r |
| 380 | #define IPL_CLK (0x16 - IPL_HMIN) /* relative IPL */\r |
| 381 | #define IPL_RQ (0x15 - IPL_HMIN)\r |
| 382 | #define IPL_RL (0x15 - IPL_HMIN)\r |
| 383 | #define IPL_DZRX (0x15 - IPL_HMIN)\r |
| 384 | #define IPL_DZTX (0x15 - IPL_HMIN)\r |
| 385 | #define IPL_RP (0x15 - IPL_HMIN)\r |
| 386 | #define IPL_TS (0x15 - IPL_HMIN)\r |
| 387 | #define IPL_TQ (0x15 - IPL_HMIN)\r |
| 388 | #define IPL_XQ (0x15 - IPL_HMIN)\r |
| 389 | #define IPL_RY (0x15 - IPL_HMIN)\r |
| 390 | #define IPL_TTI (0x14 - IPL_HMIN)\r |
| 391 | #define IPL_TTO (0x14 - IPL_HMIN)\r |
| 392 | #define IPL_PTR (0x14 - IPL_HMIN)\r |
| 393 | #define IPL_PTP (0x14 - IPL_HMIN)\r |
| 394 | #define IPL_LPT (0x14 - IPL_HMIN)\r |
| 395 | #define IPL_CSI (0x14 - IPL_HMIN)\r |
| 396 | #define IPL_CSO (0x14 - IPL_HMIN)\r |
| 397 | #define IPL_TMR0 (0x14 - IPL_HMIN)\r |
| 398 | #define IPL_TMR1 (0x14 - IPL_HMIN)\r |
| 399 | #define IPL_VHRX (0x14 - IPL_HMIN)\r |
| 400 | #define IPL_VHTX (0x14 - IPL_HMIN)\r |
| 401 | #define IPL_QDSS (0x14 - IPL_HMIN)\r |
| 402 | #define IPL_CR (0x14 - IPL_HMIN)\r |
| 403 | \r |
| 404 | #define IPL_HMAX 0x17 /* highest hwre level */\r |
| 405 | #define IPL_HMIN 0x14 /* lowest hwre level */\r |
| 406 | #define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */\r |
| 407 | #define IPL_SMAX 0xF /* highest swre level */\r |
| 408 | \r |
| 409 | /* Device vectors */\r |
| 410 | \r |
| 411 | #define VEC_Q 0x200 /* Qbus vector offset */\r |
| 412 | #define VEC_PTR (VEC_Q + 0070)\r |
| 413 | #define VEC_PTP (VEC_Q + 0074)\r |
| 414 | #define VEC_XQ (VEC_Q + 0120)\r |
| 415 | #define VEC_XU (VEC_Q + 0120)\r |
| 416 | #define VEC_RQ (VEC_Q + 0154)\r |
| 417 | #define VEC_RL (VEC_Q + 0160)\r |
| 418 | #define VEC_LPT (VEC_Q + 0200)\r |
| 419 | #define VEC_TS (VEC_Q + 0224)\r |
| 420 | #define VEC_CR (VEC_Q + 0230)\r |
| 421 | #define VEC_RP (VEC_Q + 0254)\r |
| 422 | #define VEC_TQ (VEC_Q + 0260)\r |
| 423 | #define VEC_RX (VEC_Q + 0264)\r |
| 424 | #define VEC_RY (VEC_Q + 0264)\r |
| 425 | #define VEC_DZRX (VEC_Q + 0300)\r |
| 426 | #define VEC_DZTX (VEC_Q + 0304)\r |
| 427 | #define VEC_VHRX (VEC_Q + 0310) \r |
| 428 | #define VEC_VHTX (VEC_Q + 0314)\r |
| 429 | \r |
| 430 | /* Interrupt macros */\r |
| 431 | \r |
| 432 | #define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv)\r |
| 433 | #define IREQ(dv) int_req[IPL_##dv]\r |
| 434 | #define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)\r |
| 435 | #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)\r |
| 436 | #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */\r |
| 437 | \r |
| 438 | /* Logging */\r |
| 439 | \r |
| 440 | #define LOG_CPU_I 0x1 /* intexc */\r |
| 441 | #define LOG_CPU_R 0x2 /* REI */\r |
| 442 | #define LOG_CPU_P 0x4 /* context */\r |
| 443 | \r |
| 444 | /* Function prototypes for virtual memory interface */\r |
| 445 | \r |
| 446 | int32 Read (uint32 va, int32 lnt, int32 acc);\r |
| 447 | void Write (uint32 va, int32 val, int32 lnt, int32 acc);\r |
| 448 | \r |
| 449 | /* Function prototypes for physical memory interface (inlined) */\r |
| 450 | \r |
| 451 | SIM_INLINE_GCC int32 ReadB (uint32 pa);\r |
| 452 | SIM_INLINE_GCC int32 ReadW (uint32 pa);\r |
| 453 | SIM_INLINE_GCC int32 ReadL (uint32 pa);\r |
| 454 | SIM_INLINE_GCC int32 ReadLP (uint32 pa);\r |
| 455 | SIM_INLINE_GCC void WriteB (uint32 pa, int32 val);\r |
| 456 | SIM_INLINE_GCC void WriteW (uint32 pa, int32 val);\r |
| 457 | SIM_INLINE_GCC void WriteL (uint32 pa, int32 val);\r |
| 458 | void WriteLP (uint32 pa, int32 val);\r |
| 459 | \r |
| 460 | /* Function prototypes for I/O */\r |
| 461 | \r |
| 462 | int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);\r |
| 463 | int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);\r |
| 464 | int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf);\r |
| 465 | int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf);\r |
| 466 | \r |
| 467 | t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 468 | t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 469 | t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 470 | t_stat set_vec (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 471 | t_stat show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 472 | t_stat auto_config (char *name, int32 num);\r |
| 473 | \r |
| 474 | int32 clk_cosched (int32 wait);\r |
| 475 | \r |
| 476 | #endif\r |