| 1 | /* id_defs.h: Interdata 16b/32b simulator definitions\r |
| 2 | \r |
| 3 | Copyright (c) 2000-2006, Robert M. Supnik\r |
| 4 | \r |
| 5 | Permission is hereby granted, free of charge, to any person obtaining a\r |
| 6 | copy of this software and associated documentation files (the "Software"),\r |
| 7 | to deal in the Software without restriction, including without limitation\r |
| 8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r |
| 9 | and/or sell copies of the Software, and to permit persons to whom the\r |
| 10 | Software is furnished to do so, subject to the following conditions:\r |
| 11 | \r |
| 12 | The above copyright notice and this permission notice shall be included in\r |
| 13 | all copies or substantial portions of the Software.\r |
| 14 | \r |
| 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r |
| 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r |
| 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r |
| 18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r |
| 19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r |
| 20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r |
| 21 | \r |
| 22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r |
| 23 | used in advertising or otherwise to promote the sale, use or other dealings\r |
| 24 | in this Software without prior written authorization from Robert M Supnik.\r |
| 25 | \r |
| 26 | The author gratefully acknowledges the help of Carl Friend and Al Kossow,\r |
| 27 | who provided key documents about the Interdata product line.\r |
| 28 | \r |
| 29 | 09-Mar-06 RMS Increased register sets to architectural limit\r |
| 30 | 25-Jan-04 RMS Removed local logging support\r |
| 31 | 22-Sep-03 RMS Added additional instruction decode types\r |
| 32 | 21-Jun-03 RMS Changed subroutine argument for ARM compiler conflict\r |
| 33 | 25-Apr-03 RMS Revised for extended file support\r |
| 34 | 28-Feb-03 RMS Changed magtape device default to 0x85\r |
| 35 | */\r |
| 36 | \r |
| 37 | #ifndef _ID_DEFS_H_\r |
| 38 | #define _ID_DEFS_H_ 0\r |
| 39 | \r |
| 40 | #include "sim_defs.h" /* simulator defns */\r |
| 41 | \r |
| 42 | /* Simulator stop codes */\r |
| 43 | \r |
| 44 | #define STOP_RSRV 1 /* undef instr */\r |
| 45 | #define STOP_HALT 2 /* HALT */\r |
| 46 | #define STOP_IBKPT 3 /* breakpoint */\r |
| 47 | #define STOP_WAIT 4 /* wait */\r |
| 48 | #define STOP_VFU 5 /* runaway VFU */\r |
| 49 | \r |
| 50 | /* Memory */\r |
| 51 | \r |
| 52 | #define PAWIDTH16 16\r |
| 53 | #define PAWIDTH16E 18\r |
| 54 | #define PAWIDTH32 20\r |
| 55 | #define MAXMEMSIZE16 (1u << PAWIDTH16) /* max mem size, 16b */\r |
| 56 | #define MAXMEMSIZE16E (1u << PAWIDTH16E) /* max mem size, 16b E */\r |
| 57 | #define MAXMEMSIZE32 (1u << PAWIDTH32) /* max mem size, 32b */\r |
| 58 | #define PAMASK16 (MAXMEMSIZE16 - 1) /* phys mem mask */\r |
| 59 | #define PAMASK16E (MAXMEMSIZE16E - 1)\r |
| 60 | #define PAMASK32 (MAXMEMSIZE32 - 1)\r |
| 61 | \r |
| 62 | #define MEMSIZE (cpu_unit.capac) /* act memory size */\r |
| 63 | #define MEM_ADDR_OK(x) (((uint32) (x)) < MEMSIZE)\r |
| 64 | \r |
| 65 | /* Single precision floating point registers */\r |
| 66 | \r |
| 67 | #if defined (IFP_IN_MEM)\r |
| 68 | #define ReadFReg(r) (fp_in_hwre? \\r |
| 69 | F[(r) >> 1]: ReadF (((r) << 1) & ~3, P))\r |
| 70 | #define WriteFReg(r,v) if (fp_in_hwre) F[(r) >> 1] = (v); \\r |
| 71 | else WriteF (((r) << 1) & ~3, (v), P)\r |
| 72 | #else\r |
| 73 | #define ReadFReg(r) (F[(r) >> 1])\r |
| 74 | #define WriteFReg(r,v) F[(r) >> 1] = (v)\r |
| 75 | #endif\r |
| 76 | \r |
| 77 | /* Double precision floating point registers */\r |
| 78 | \r |
| 79 | typedef struct {\r |
| 80 | uint32 h; /* high 32b */\r |
| 81 | uint32 l; /* low 32b */\r |
| 82 | } dpr_t;\r |
| 83 | \r |
| 84 | /* Architectural constants */\r |
| 85 | \r |
| 86 | #define VAMASK16 (0xFFFF) /* 16b virt addr */\r |
| 87 | #define VAMASK32 (0x000FFFFF) /* 32b virt addr */\r |
| 88 | \r |
| 89 | #define SIGN8 0x80 /* 8b sign bit */\r |
| 90 | #define DMASK8 0xFF /* 8b data mask */\r |
| 91 | #define MMASK8 0x7F /* 8b magnitude mask */\r |
| 92 | #define SIGN16 0x8000 /* 16b sign bit */\r |
| 93 | #define DMASK16 0xFFFF /* 16b data mask */\r |
| 94 | #define MMASK16 0x7FFF /* 16b magnitude mask */\r |
| 95 | #define SIGN32 0x80000000 /* 32b sign bit */\r |
| 96 | #define DMASK32 0xFFFFFFFF /* 32b data mask */\r |
| 97 | #define MMASK32 0x7FFFFFFF /* 32b magn mask */\r |
| 98 | \r |
| 99 | #define CC_C 0x8 /* carry */\r |
| 100 | #define CC_V 0x4 /* overflow */\r |
| 101 | #define CC_G 0x2 /* greater than */\r |
| 102 | #define CC_L 0x1 /* less than */\r |
| 103 | #define CC_MASK (CC_C | CC_V | CC_G | CC_L)\r |
| 104 | \r |
| 105 | #define PSW_WAIT 0x8000 /* wait */ \r |
| 106 | #define PSW_EXI 0x4000 /* ext intr enable */\r |
| 107 | #define PSW_MCI 0x2000 /* machine check enable */\r |
| 108 | #define PSW_AFI 0x1000 /* arith fault enb */\r |
| 109 | #define PSW_AIO 0x0800 /* auto I/O int enable */\r |
| 110 | #define PSW_FPF 0x0400 /* flt fault enb, 16b */\r |
| 111 | #define PSW_REL 0x0400 /* reloc enb, 32b */\r |
| 112 | #define PSW_SQI 0x0200 /* sys q int enable */\r |
| 113 | #define PSW_PRO 0x0100 /* protect mode */\r |
| 114 | #define PSW_V_MAP 4 /* mem map, 16b */\r |
| 115 | #define PSW_M_MAP 0xF\r |
| 116 | #define PSW_MAP (PSW_M_MAP << PSW_V_MAP)\r |
| 117 | #define PSW_V_REG 4 /* reg set, 32b */\r |
| 118 | #define PSW_M_REG 0xF\r |
| 119 | #define PSW_ID4 0xF40F /* I3, I4 PSW */\r |
| 120 | #define PSW_x16 0xFF0F /* 7/16, 8/16 PSW */\r |
| 121 | #define PSW_816E 0xFFFF /* 8/16E PSW */\r |
| 122 | #define PSW_x32 0xFFFF /* 7/32, 8/32 PSW */\r |
| 123 | \r |
| 124 | #define MCKOPSW 0x20 /* mchk old PSW, 32b */\r |
| 125 | #define FPFPSW 0x28 /* flt fault PSW, 16b */\r |
| 126 | #define ILOPSW 0x30 /* ill op PSW */\r |
| 127 | #define MCKPSW 0x38 /* mach chk PSW */\r |
| 128 | #define EXIPSW 0x40 /* ext intr PSW, 16b */\r |
| 129 | #define AFIPSW 0x48 /* arith flt PSW */\r |
| 130 | #define SQP 0x80 /* system queue ptr */\r |
| 131 | #define SQIPSW 0x82 /* sys q int PSW, 16b */\r |
| 132 | #define SQOP 0x8A /* sys q ovf ptr, 16b */\r |
| 133 | #define SQVPSW 0x8C /* sys q ovf PSW, 16b */\r |
| 134 | #define SQTPSW 0x88 /* sys q int PSW, 32b */\r |
| 135 | #define MPRPSW 0x90 /* mprot int PSW, 32b */\r |
| 136 | #define SVCAP 0x94 /* svc arg ptr, 16b */\r |
| 137 | #define SVOPS 0x96 /* svc old PS, 16b */\r |
| 138 | #define SVOPC 0x98 /* svc old PC, 16b */\r |
| 139 | #define SVNPS32 0x98 /* svc new PS, 32b */\r |
| 140 | #define SVNPS 0x9A /* svc new PS, 16b */\r |
| 141 | #define SVNPC 0x9C /* svc new PC */\r |
| 142 | #define INTSVT 0xD0 /* int service table */\r |
| 143 | \r |
| 144 | #define AL_DEV 0x78 /* autoload: dev */\r |
| 145 | #define AL_IOC 0x79 /* command */\r |
| 146 | #define AL_DSKU 0x7A /* disk unit */\r |
| 147 | #define AL_DSKT 0x7B /* disk type */\r |
| 148 | #define AL_DSKC 0x7C /* disk ctrl */\r |
| 149 | #define AL_SCH 0x7D /* sel chan */\r |
| 150 | #define AL_EXT 0x7E /* OS extension */\r |
| 151 | #define AL_BUF 0x80 /* buffer start */\r |
| 152 | \r |
| 153 | #define Q16_SLT 0 /* list: # slots */\r |
| 154 | #define Q16_USD 1 /* # in use */\r |
| 155 | #define Q16_TOP 2 /* current top */\r |
| 156 | #define Q16_BOT 3 /* next bottom */\r |
| 157 | #define Q16_BASE 4 /* base of q */\r |
| 158 | #define Q16_SLNT 2 /* slot length */\r |
| 159 | \r |
| 160 | #define Q32_SLT 0 /* list: # slots */\r |
| 161 | #define Q32_USD 2 /* # in use */\r |
| 162 | #define Q32_TOP 4 /* current top */\r |
| 163 | #define Q32_BOT 6 /* next bottom */\r |
| 164 | #define Q32_BASE 8 /* base of q */\r |
| 165 | #define Q32_SLNT 4 /* slot length */\r |
| 166 | \r |
| 167 | /* CPU event flags */\r |
| 168 | \r |
| 169 | #define EV_MAC 0x01 /* MAC interrupt */\r |
| 170 | #define EV_BLK 0x02 /* block I/O in prog */\r |
| 171 | #define EV_INT 0x04 /* interrupt pending */\r |
| 172 | #define EV_WAIT 0x08 /* wait state pending */\r |
| 173 | \r |
| 174 | /* Block I/O state */\r |
| 175 | \r |
| 176 | struct BlockIO {\r |
| 177 | uint32 dfl; /* devno, flags */\r |
| 178 | uint32 cur; /* current addr */\r |
| 179 | uint32 end; /* end addr */\r |
| 180 | };\r |
| 181 | \r |
| 182 | #define BL_RD 0x8000 /* block read */\r |
| 183 | #define BL_LZ 0x4000 /* skip 0's */\r |
| 184 | \r |
| 185 | /* Instruction decode ROM, for all, 16b, 32b */\r |
| 186 | \r |
| 187 | #define OP_UNDEF 0x0000 /* undefined */\r |
| 188 | #define OP_NO 0x0001 /* all: short or fp rr */\r |
| 189 | #define OP_RR 0x0002 /* all: reg-reg */\r |
| 190 | #define OP_RS 0x0003 /* 16b: reg-storage */\r |
| 191 | #define OP_RI1 0x0003 /* 32b: reg-imm 16b */\r |
| 192 | #define OP_RX 0x0004 /* all: reg-mem */\r |
| 193 | #define OP_RXB 0x0005 /* all: reg-mem, rd BY */\r |
| 194 | #define OP_RXH 0x0006 /* all: reg-mem, rd HW */\r |
| 195 | #define OP_RXF 0x0007 /* 32b: reg-mem, rd FW */\r |
| 196 | #define OP_RI2 0x0008 /* 32b: reg-imm 32b */\r |
| 197 | #define OP_MASK 0x000F\r |
| 198 | \r |
| 199 | #define OP_ID4 0x0010 /* 16b: ID4 */\r |
| 200 | #define OP_716 0x0020 /* 16b: 7/16 */\r |
| 201 | #define OP_816 0x0040 /* 16b: 8/16 */\r |
| 202 | #define OP_816E 0x0080 /* 16b: 8/16E */\r |
| 203 | \r |
| 204 | #define OP_DPF 0x4000 /* all: hwre FP */\r |
| 205 | #define OP_PRV 0x8000 /* all: privileged */\r |
| 206 | \r |
| 207 | #define OP_TYPE(x) (decrom[(x)] & OP_MASK)\r |
| 208 | #define OP_DPFP(x) (decrom[(x)] & OP_DPF)\r |
| 209 | \r |
| 210 | /* Device information block */\r |
| 211 | \r |
| 212 | typedef struct {\r |
| 213 | uint32 dno; /* device number */\r |
| 214 | int32 sch; /* sch */\r |
| 215 | uint32 irq; /* interrupt */\r |
| 216 | uint8 *tplte; /* template */\r |
| 217 | uint32 (*iot)(uint32 d, uint32 o, uint32 dat);\r |
| 218 | void (*ini)(t_bool f);\r |
| 219 | } DIB;\r |
| 220 | \r |
| 221 | #define TPL_END 0xFF /* template end */\r |
| 222 | \r |
| 223 | /* Device select return codes */\r |
| 224 | \r |
| 225 | #define BY 0 /* 8b only */\r |
| 226 | #define HW 1 /* 8b/16b */\r |
| 227 | \r |
| 228 | /* I/O operations */\r |
| 229 | \r |
| 230 | #define IO_ADR 0x0 /* address select */\r |
| 231 | #define IO_RD 0x1 /* read byte */\r |
| 232 | #define IO_RH 0x2 /* read halfword */\r |
| 233 | #define IO_WD 0x3 /* write byte */\r |
| 234 | #define IO_WH 0x4 /* write halfword */\r |
| 235 | #define IO_OC 0x5 /* output command */\r |
| 236 | #define IO_SS 0x6 /* sense status */\r |
| 237 | \r |
| 238 | /* Device command byte */\r |
| 239 | \r |
| 240 | #define CMD_V_INT 6 /* interrupt control */\r |
| 241 | #define CMD_M_INT 0x3\r |
| 242 | #define CMD_IENB 1 /* enable */\r |
| 243 | #define CMD_IDIS 2 /* disable */\r |
| 244 | #define CMD_IDSA 3 /* disarm */\r |
| 245 | #define CMD_GETINT(x) (((x) >> CMD_V_INT) & CMD_M_INT)\r |
| 246 | \r |
| 247 | /* Device status byte */\r |
| 248 | \r |
| 249 | #define STA_BSY 0x8 /* busy */\r |
| 250 | #define STA_EX 0x4 /* examine status */\r |
| 251 | #define STA_EOM 0x2 /* end of medium */\r |
| 252 | #define STA_DU 0x1 /* device unavailable */\r |
| 253 | \r |
| 254 | /* Default device numbers */\r |
| 255 | \r |
| 256 | #define DEV_LOW 0x01 /* lowest intr dev */\r |
| 257 | #define DEV_MAX 0xFF /* highest intr dev */\r |
| 258 | #define DEVNO (DEV_MAX + 1) /* number of devices */\r |
| 259 | #define d_DS 0x01 /* display, switches */\r |
| 260 | #define d_TT 0x02 /* teletype */\r |
| 261 | #define d_PT 0x03 /* reader */\r |
| 262 | #define d_CD 0x04 /* card reader */\r |
| 263 | #define d_TTP 0x10 /* PAS as console */\r |
| 264 | #define d_PAS 0x10 /* first PAS */\r |
| 265 | #define o_PASX 0x01 /* offset to xmt */\r |
| 266 | #define d_LPT 0x62 /* line printer */\r |
| 267 | #define d_PIC 0x6C /* interval timer */\r |
| 268 | #define d_LFC 0x6D /* line freq clk */\r |
| 269 | #define d_MT 0x85 /* magtape */\r |
| 270 | #define o_MT0 0x10\r |
| 271 | #define d_DPC 0xB6 /* disk controller */\r |
| 272 | #define o_DP0 0x10\r |
| 273 | #define o_DPF 0x01 /* offset to fixed */\r |
| 274 | #define d_FD 0xC1 /* floppy disk */\r |
| 275 | #define d_SCH 0xF0 /* selector chan */\r |
| 276 | #define d_IDC 0xFB /* MSM disk ctrl */\r |
| 277 | #define o_ID0 0x01\r |
| 278 | \r |
| 279 | /* Interrupts\r |
| 280 | \r |
| 281 | To make interrupt flags independent of device numbers, each device is\r |
| 282 | assigned an interrupt flag in one of four interrupt words\r |
| 283 | \r |
| 284 | word 0 DMA devices\r |
| 285 | word 1 programmed I/O devices\r |
| 286 | word 2-3 PAS devices\r |
| 287 | \r |
| 288 | Devices are identified by a level and a bit within a level. Priorities\r |
| 289 | run low to high in the array, right to left within words\r |
| 290 | */\r |
| 291 | \r |
| 292 | #define INTSZ 4 /* interrupt words */\r |
| 293 | #define SCH_NUMCH 4 /* #channels */\r |
| 294 | #define ID_NUMDR 4 /* # MSM drives */\r |
| 295 | #define DP_NUMDR 4 /* # DPC drives */\r |
| 296 | #define MT_NUMDR 4 /* # MT drives */\r |
| 297 | \r |
| 298 | /* Word 0, DMA devices */\r |
| 299 | \r |
| 300 | #define i_SCH 0 /* highest priority */\r |
| 301 | #define i_IDC (i_SCH + SCH_NUMCH) /* MSM disk ctrl */\r |
| 302 | #define i_DPC (i_IDC + ID_NUMDR + 1) /* cartridge disk ctrl */\r |
| 303 | #define i_MT (i_DPC + DP_NUMDR + 1) /* magtape */\r |
| 304 | \r |
| 305 | #define l_SCH 0\r |
| 306 | #define l_IDC 0\r |
| 307 | #define l_DPC 0\r |
| 308 | #define l_MT 0\r |
| 309 | \r |
| 310 | #define v_SCH (l_SCH * 32) + i_SCH\r |
| 311 | #define v_IDC (l_IDC * 32) + i_IDC\r |
| 312 | #define v_DPC (l_DPC * 32) + i_DPC\r |
| 313 | #define v_MT (l_MT * 32) + i_MT\r |
| 314 | \r |
| 315 | /* Word 1, programmed I/O devices */\r |
| 316 | \r |
| 317 | #define i_PIC 0 /* precision clock */\r |
| 318 | #define i_LFC 1 /* line clock */\r |
| 319 | #define i_FD 2 /* floppy disk */\r |
| 320 | #define i_CD 3 /* card reader */\r |
| 321 | #define i_LPT 4 /* line printer */\r |
| 322 | #define i_PT 5 /* paper tape */\r |
| 323 | #define i_TT 6 /* teletype */\r |
| 324 | #define i_DS 7 /* display */\r |
| 325 | #define i_TTP 10 /* PAS console */\r |
| 326 | \r |
| 327 | #define l_PIC 1\r |
| 328 | #define l_LFC 1\r |
| 329 | #define l_FD 1\r |
| 330 | #define l_CD 1\r |
| 331 | #define l_LPT 1\r |
| 332 | #define l_PT 1\r |
| 333 | #define l_TT 1\r |
| 334 | #define l_DS 1\r |
| 335 | #define l_TTP 1\r |
| 336 | \r |
| 337 | #define v_PIC (l_PIC * 32) + i_PIC\r |
| 338 | #define v_LFC (l_LFC * 32) + i_LFC\r |
| 339 | #define v_FD (l_FD * 32) + i_FD\r |
| 340 | #define v_CD (l_CD * 32) + i_CD\r |
| 341 | #define v_LPT (l_LPT * 32) + i_LPT\r |
| 342 | #define v_PT (l_PT * 32) + i_PT\r |
| 343 | #define v_TT (l_TT * 32) + i_TT\r |
| 344 | #define v_DS (l_DS * 32) + i_DS\r |
| 345 | #define v_TTP (l_TTP * 32) + i_TTP\r |
| 346 | \r |
| 347 | /* Word 2-3, PAS devices */\r |
| 348 | \r |
| 349 | #define i_PAS 0\r |
| 350 | #define l_PAS 2\r |
| 351 | #define v_PAS (l_PAS * 32) + i_PAS\r |
| 352 | #define v_PASX (v_PAS + 1) /* offset to xmt */\r |
| 353 | \r |
| 354 | /* I/O macros */\r |
| 355 | \r |
| 356 | #define SET_INT(v) int_req[(v) >> 5] = int_req[(v) >> 5] | (1u << ((v) & 0x1F))\r |
| 357 | #define CLR_INT(v) int_req[(v) >> 5] = int_req[(v) >> 5] & ~(1u << ((v) & 0x1F))\r |
| 358 | #define SET_ENB(v) int_enb[(v) >> 5] = int_enb[(v) >> 5] | (1u << ((v) & 0x1F))\r |
| 359 | #define CLR_ENB(v) int_enb[(v) >> 5] = int_enb[(v) >> 5] & ~(1u << ((v) & 0x1F))\r |
| 360 | \r |
| 361 | #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* stop on error */\r |
| 362 | \r |
| 363 | /* Device accessible macro */\r |
| 364 | \r |
| 365 | #define DEV_ACC(d) (dev_tab[d] && !sch_blk (d))\r |
| 366 | \r |
| 367 | /* Automatic I/O channel programs, 16b */\r |
| 368 | \r |
| 369 | #define CCB16_CHN -4 /* chain */\r |
| 370 | #define CCB16_DEV -2 /* dev no */\r |
| 371 | #define CCB16_STS -1 /* status */\r |
| 372 | #define CCB16_CCW 0 /* cmd wd */\r |
| 373 | #define CCB16_STR 2 /* start */\r |
| 374 | #define CCB16_END 4 /* end */\r |
| 375 | #define CCB16_IOC 6 /* OC byte */\r |
| 376 | #define CCB16_TRM 7 /* term byte */\r |
| 377 | \r |
| 378 | #define CCW16_INIT 0x8000 /* init */\r |
| 379 | #define CCW16_NOP 0x4000 /* nop */\r |
| 380 | #define CCW16_V_FNC 12 /* function */\r |
| 381 | #define CCW16_M_FNC 0x3\r |
| 382 | #define CCW16_FNC(x) (((x) >> CCW16_V_FNC) & CCW16_M_FNC)\r |
| 383 | #define CCW16_RD 0 /* read */\r |
| 384 | #define CCW16_WR 1 /* write */\r |
| 385 | #define CCW16_DMT 2 /* dec mem */\r |
| 386 | #define CCW16_NUL 3 /* null */\r |
| 387 | #define CCW16_TRM 0x0400 /* term char */\r |
| 388 | #define CCW16_Q 0x0200 /* queue */\r |
| 389 | #define CCW16_HI 0x0100 /* queue hi */\r |
| 390 | #define CCW16_OC 0x0080 /* OC */\r |
| 391 | #define CCW16_CHN 0x0020 /* chain */\r |
| 392 | #define CCW16_CON 0x0010 /* continue */\r |
| 393 | #define CCW16_V_BPI 0 /* bytes per int */\r |
| 394 | #define CCW16_M_BPI 0xF\r |
| 395 | #define CCW16_BPI(x) (((x) >> CCW16_V_BPI) & CCW16_M_BPI)\r |
| 396 | \r |
| 397 | /* Automatic I/O channel programs, 32b */\r |
| 398 | \r |
| 399 | #define CCB32_CCW 0 /* cmd wd */\r |
| 400 | #define CCB32_B0C 2 /* buf 0 cnt */\r |
| 401 | #define CCB32_B0E 4 /* buf 0 end */\r |
| 402 | #define CCB32_CHK 8 /* check word */\r |
| 403 | #define CCB32_B1C 10 /* buf 1 cnt */\r |
| 404 | #define CCB32_B1E 12 /* buf 1 end */\r |
| 405 | #define CCB32_TAB 16 /* trans table */\r |
| 406 | #define CCB32_SUB 20 /* subroutine */\r |
| 407 | \r |
| 408 | #define CCW32_V_STA 8 /* status */\r |
| 409 | #define CCW32_M_STA 0xFF\r |
| 410 | #define CCW32_STA(x) (((x) >> CCW32_V_STA) & CCW32_M_STA)\r |
| 411 | #define CCW32_EXE 0x80 /* execute */\r |
| 412 | #define CCW32_CRC 0x10\r |
| 413 | #define CCW32_B1 0x08 /* buffer 1 */\r |
| 414 | #define CCW32_WR 0x04 /* write */\r |
| 415 | #define CCW32_TL 0x02 /* translate */\r |
| 416 | #define CCW32_FST 0x01 /* fast mode */\r |
| 417 | \r |
| 418 | /* MAC, 32b */\r |
| 419 | \r |
| 420 | #define P 0 /* physical */\r |
| 421 | #define VE 1 /* virtual inst */ \r |
| 422 | #define VR 2 /* virtual read */\r |
| 423 | #define VW 3 /* virtual write */\r |
| 424 | \r |
| 425 | #define MAC_BASE 0x300 /* MAC base */\r |
| 426 | #define MAC_STA 0x340 /* MAC status */\r |
| 427 | #define MAC_LNT 16\r |
| 428 | #define VA_V_OFF 0 /* offset */\r |
| 429 | #define VA_M_OFF 0xFFFF\r |
| 430 | #define VA_GETOFF(x) (((x) >> VA_V_OFF) & VA_M_OFF)\r |
| 431 | #define VA_V_SEG 16 /* segment */\r |
| 432 | #define VA_M_SEG 0xF\r |
| 433 | #define VA_GETSEG(x) (((x) >> VA_V_SEG) & VA_M_SEG)\r |
| 434 | \r |
| 435 | #define SRF_MASK 0x000FFF00 /* base mask */\r |
| 436 | #define SRL_MASK 0x0FF00000 /* limit mask */\r |
| 437 | #define GET_SRL(x) ((((x) & SRL_MASK) >> 12) + 0x100)\r |
| 438 | #define SR_EXP 0x80 /* execute prot */\r |
| 439 | #define SR_WPI 0x40 /* wr prot int */\r |
| 440 | #define SR_WRP 0x20 /* wr prot */\r |
| 441 | #define SR_PRS 0x10 /* present */\r |
| 442 | #define SR_MASK (SRF_MASK|SRL_MASK|SR_EXP|SR_WPI|SR_WRP|SR_PRS)\r |
| 443 | \r |
| 444 | #define MACS_L 0x10 /* limit viol */\r |
| 445 | #define MACS_NP 0x08 /* not present */\r |
| 446 | #define MACS_WP 0x04 /* write prot */\r |
| 447 | #define MACS_WI 0x02 /* write int */\r |
| 448 | #define MACS_EX 0x01 /* exec prot */\r |
| 449 | \r |
| 450 | /* Miscellaneous */\r |
| 451 | \r |
| 452 | #define TMR_LFC 0 /* LFC = timer 0 */\r |
| 453 | #define TMR_PIC 1 /* PIC = timer 1 */\r |
| 454 | #define LPT_WIDTH 132\r |
| 455 | #define VFU_LNT 132\r |
| 456 | #define MIN(x,y) (((x) < (y))? (x): (y))\r |
| 457 | #define MAX(x,y) (((x) > (y))? (x): (y))\r |
| 458 | \r |
| 459 | /* Function prototypes */\r |
| 460 | \r |
| 461 | int32 int_chg (uint32 irq, int32 dat, int32 armdis);\r |
| 462 | int32 io_2b (int32 val, int32 pos, int32 old);\r |
| 463 | uint32 IOReadB (uint32 loc);\r |
| 464 | void IOWriteB (uint32 loc, uint32 val);\r |
| 465 | uint32 IOReadH (uint32 loc);\r |
| 466 | void IOWriteH (uint32 loc, uint32 val);\r |
| 467 | uint32 ReadF (uint32 loc, uint32 rel);\r |
| 468 | void WriteF (uint32 loc, uint32 val, uint32 rel);\r |
| 469 | uint32 IOReadBlk (uint32 loc, uint32 cnt, uint8 *buf);\r |
| 470 | uint32 IOWriteBlk (uint32 loc, uint32 cnt, uint8 *buf);\r |
| 471 | void sch_adr (uint32 ch, uint32 dev);\r |
| 472 | t_bool sch_actv (uint32 sch, uint32 devno);\r |
| 473 | void sch_stop (uint32 sch);\r |
| 474 | uint32 sch_wrmem (uint32 sch, uint8 *buf, uint32 cnt);\r |
| 475 | uint32 sch_rdmem (uint32 sch, uint8 *buf, uint32 cnt);\r |
| 476 | t_stat set_sch (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 477 | t_stat set_dev (UNIT *uptr, int32 val, char *cptr, void *desc);\r |
| 478 | t_stat show_sch (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 479 | t_stat show_dev (FILE *st, UNIT *uptr, int32 val, void *desc);\r |
| 480 | \r |
| 481 | #endif\r |