| 1 | /PDP-8A OPTION 1 (100 HZ) CLOCK ROUTINE................CLK8A\r |
| 2 | /\r |
| 3 | /\r |
| 4 | /\r |
| 5 | /\r |
| 6 | /\r |
| 7 | /\r |
| 8 | /\r |
| 9 | /\r |
| 10 | /\r |
| 11 | /\r |
| 12 | /\r |
| 13 | /\r |
| 14 | /COPYRIGHT (C) 1975\r |
| 15 | /DIGITAL EQUIPMENT CORPORATION, MAYNARD, MASS.\r |
| 16 | /\r |
| 17 | /\r |
| 18 | /\r |
| 19 | /THIS SOFTWARE IS FURNISHED UNDER A LICENSE FOR USE ONLY ON A\r |
| 20 | /SINGLE COMPUTER SYSTEM AND MAY BE COPIED ONLY WITH THE INCLU-\r |
| 21 | /SION OF THE ABOVE COPYRIGHT NOTICE. THIS SOFTWARE,OR ANY OTHER\r |
| 22 | /COPIES THEREOF, MAY NOT BE PROVIDED OR OTHERWISE MADE AVAILABLE\r |
| 23 | /TO ANY OTHER PERSON EXCEPT FOR USE ON SUCH A SYSTEM AND TO ONE WHO\r |
| 24 | /AGREES TO THESE LICENSE TERMS. TITLE TO AND OWNERSHIP OF THE\r |
| 25 | /SOFTWARE SHALL AT ALL TIMES REMAIN IN DEC.\r |
| 26 | /\r |
| 27 | /\r |
| 28 | /THE INFORMATION IN THIS SOFTWARE IS SUBJECT TO CHANGE WITHOUT\r |
| 29 | /NOTICE AND SHOULD NOT BE CONSTRUED AS A COMMITMENT BY DIGITAL\r |
| 30 | /EQUIPMENT CORPORATION.\r |
| 31 | /\r |
| 32 | /\r |
| 33 | /DEC ASSUMES NO RESPONSIBILITY FOR THE USEOR RELIABILITY OF ITS\r |
| 34 | /SOFTWARE ON EQUIPMENT WHICH IS NOT SUPPLIED BY DEC.\r |
| 35 | /\r |
| 36 | /\r |
| 37 | /\r |
| 38 | /\r |
| 39 | /\r |
| 40 | /\r |
| 41 | /\r |
| 42 | /\r |
| 43 | /\r |
| 44 | /\r |
| 45 | /\r |
| 46 | /\r |
| 47 | \r |
| 48 | \r |
| 49 | \r |
| 50 | \r |
| 51 | /\r |
| 52 | /E.P. 11/6/75\r |
| 53 | /\r |
| 54 | /\r |
| 55 | \r |
| 56 | \f\r |
| 57 | \r |
| 58 | \r |
| 59 | \r |
| 60 | \r |
| 61 | \r |
| 62 | EXTERN #DISP /SYSTEM PAGE 0,NEEDED TO\r |
| 63 | /PUT CLOCK STATUS ON PG0\r |
| 64 | /(CSTAT) FOR USE BY GEN\r |
| 65 | /USER CLOCK SERVICE ROUTS\r |
| 66 | EXTERN #T812 /RTS CPTYP\r |
| 67 | EXTERN ONQI /INTERRUPT QUEUER\r |
| 68 | CLLE= 6135 /AC11=1 INTRRUPTS ON.\r |
| 69 | CLCL= 6136 /CLEAR CLOCK FLAG\r |
| 70 | CLSK= 6137 /SKIP ON CLOCK FLAG.\r |
| 71 | CSTAT=157 /IDOCLK PUTS CLSA BITS\r |
| 72 | /IN HERE\r |
| 73 | BASE FTMP0\r |
| 74 | INDEX FCNWD\r |
| 75 | FIELD1 SYNC\r |
| 76 | JSA SETUP /HERE TO READ A STRIG\r |
| 77 | /INITIALIZE ARGS\r |
| 78 | TRAP4 DOSYNC /FCNWD (XR) HOLDS STRIG\r |
| 79 | /TO READ\r |
| 80 | XTA FCNWD /=ANS=0,1\r |
| 81 | FSTA% FTMP1 /GIVE ANS TO CALLER\r |
| 82 | JA GOBAK\r |
| 83 | FTMP0, F 0.0 /BASE PAGE\r |
| 84 | FTMP1, F 0.0\r |
| 85 | RPTR, 27;ADDR RTBL /PTR TO RATE TBL, ALSO\r |
| 86 | /USED TO FLT OVRCNT (NOTE\r |
| 87 | /THAT THE EXPONENT=27)\r |
| 88 | MINRAT, F .02 /MIN ALLOWABLE RATE\r |
| 89 | TOVR, F 0.0\r |
| 90 | NAME, TEXT +CLOCK +\r |
| 91 | ORG 10*3+FTMP0\r |
| 92 | FNOP\r |
| 93 | JA NAME+3\r |
| 94 | 0\r |
| 95 | GOBAK, JA .\r |
| 96 | RTBL, F 16.0 /CONSTANT USED TO CHK FOR\r |
| 97 | /EXT CLK BIT IN FCNWD\r |
| 98 | /THIS CONST MUST BE NE 0\r |
| 99 | MAXRAT,\r |
| 100 | F4096, F 4096.0 /USED TO GET OVRFLO COUNT\r |
| 101 | F 100000.0 /FASTEST RATE IN HERTZ\r |
| 102 | F 10000.0 /NEXT FASTEST RATE\r |
| 103 | F 1000.0\r |
| 104 | F 100.0 /SLOWEST RATE\r |
| 105 | F 1.0 /USED BY TIME FOR EXT CLK\r |
| 106 | \f BASE 0\r |
| 107 | \r |
| 108 | SETUP, 0;0 /HERE TO INIT ALL FPP SUBS\r |
| 109 | STARTD\r |
| 110 | FLDA 30 /PICK UP RTN TO CALLER\r |
| 111 | FSTA GOBAK\r |
| 112 | FLDA 0 /GET PTR TO CALLERS ARGS\r |
| 113 | SETX FCNWD /CLOCK XR AND BASE\r |
| 114 | SETB FTMP0\r |
| 115 | BASE FTMP0\r |
| 116 | FSTA FTMP1\r |
| 117 | FLDA% FTMP1,P1\r |
| 118 | FSTA FTMP0 /PTR TO 1ST ARG\r |
| 119 | FLDA% FTMP1,P2\r |
| 120 | FSTA FTMP1 /PTR TO 2ND ARG\r |
| 121 | FLDA #T812 /TELLS PDP8,PDP12\r |
| 122 | ATX CPTYP /0=8=DK8ES,1=12=KW12A\r |
| 123 | STARTF\r |
| 124 | FLDA% FTMP0 /=1ST ARG\r |
| 125 | ATX FCNWD /ALWAYS IN FCNWD\r |
| 126 | JA SETUP\r |
| 127 | \f ENTRY CLOCK\r |
| 128 | CLOCK, JSA SETUP /HERE FOR CLOCK START\r |
| 129 | FLDA% FTMP0\r |
| 130 | FSUB RTBL /FCNWD IS IN FAC,IF GE 16\r |
| 131 | JGE ITSEXT /(RTBL=16.0) THEN USER IS\r |
| 132 | /REQUESTING AN EXTERNAL\r |
| 133 | /CLOCK I.E. B8 OF FCNWD\r |
| 134 | /IS SET.\r |
| 135 | FLDA% FTMP1 /=REQUESTED RATE IN HERTZ\r |
| 136 | FSUB MINRAT /.LE. MINUMUM RATE\r |
| 137 | JLE GOTR-2 /MEANS STOP CLOCK.\r |
| 138 | FADD MINRAT\r |
| 139 | FSUB MAXRAT /CHK FOR TOO FAST\r |
| 140 | JGT GOTR-2\r |
| 141 | LDX -4,OVRFLO /THERE ARE 4 BASIC RATES\r |
| 142 | LDX 1,RATE /=INDEX INTO RTBL; UPON\r |
| 143 | /TRAP(CLOCK) RATE=(0,\r |
| 144 | /2,3,4,5,6) 0=STOP,\r |
| 145 | /6=EXTERNAL\r |
| 146 | /2-5=PROGRAMMABLE RATES\r |
| 147 | LOP0, FLDA% RPTR,RATE+\r |
| 148 | /GET NEXT SLOWEST RATE\r |
| 149 | FDIV% FTMP1 /=REQUESTED RATE IN HZ.\r |
| 150 | /FAC=OVRFLO COUNT;\r |
| 151 | FSUB F4096 /MUST BE MODULO 12 BITS.\r |
| 152 | JLE GOTR /FOUND IT\r |
| 153 | JXN LOP0,OVRFLO+\r |
| 154 | LDX 0,RATE /RATE IS TOO SLOW, STOP\r |
| 155 | /CLOCK.\r |
| 156 | GOTR, FADD F4096 /RESTORE\r |
| 157 | FSTA TOVR\r |
| 158 | ATX OVRFLO /OVER FLOW COUNT\r |
| 159 | TRAP4 SETCLK /GO START CLOCK\r |
| 160 | JA GOBAK /RTN TO CALLER\r |
| 161 | ITSEXT, LDX 6,RATE /=RATE FOR EXT CLK\r |
| 162 | FLDA% FTMP1 /REQUESTED RATE IS\r |
| 163 | /INTERPRETED AS OVRFLO\r |
| 164 | JA GOTR+1 /WHEN RATE IS EXTERNAL\r |
| 165 | \f/MAGIC TABLE USED BY SETCLK TO SET CLOCK ENABLE\r |
| 166 | /BITS. EVEN NUMBERED ENTRIES ARE FOR THE DK8ES;\r |
| 167 | /ODD NUMBERED ONES ARE FOR THE KW12A.\r |
| 168 | \r |
| 169 | CLKTBL, 0675 /"STANDARD" DK BITS\r |
| 170 | 300 /STND KW BITS\r |
| 171 | 1 /DK STRIG1 BIT\r |
| 172 | 60 /KW STRIG1 BITS\r |
| 173 | 2 /DK S2\r |
| 174 | 14 /KW S2\r |
| 175 | 4 /S3\r |
| 176 | P3, 3 /S3\r |
| 177 | 40 /DK ADC ON OVR BIT\r |
| 178 | 400 /KW ADC ON OVR BIT\r |
| 179 | \r |
| 180 | /IF NOT NEXT PAGE DO ORG\r |
| 181 | IFNEG .-200 < ORG .-SYNC&7600+200+SYNC >\r |
| 182 | \fSETCLK, 0 /TRAP HERE TO START CLK\r |
| 183 | /THIS ROUT HANDLES BOTH\r |
| 184 | /DK8ES AND KW12A.\r |
| 185 | CLCL /TRY AND CLEAR IT HERE????\r |
| 186 | / CLLR /STOP KW AND SET MODE 0;\r |
| 187 | /NOP FOR DK.\r |
| 188 | / CLEN /CLR KW12 ENABLE OR\r |
| 189 | /READ DK ENABLE.\r |
| 190 | / CLA\r |
| 191 | / TAD P7540 /TOGGLE KW MODE 0 TO 1 TO\r |
| 192 | / CLLR /CLR CLK COUNTER, OR SET\r |
| 193 | /DK ENABLE BITS, RATE FOR\r |
| 194 | / CLA CMA /BOTH NOW=7=STOP.\r |
| 195 | / CLZE /CLR ALL DK ENABLE BITS,\r |
| 196 | / CLSA /CLR STATUS OF BOTH, ALL \r |
| 197 | CLA /IS NOW CLEAR.\r |
| 198 | TAD FCNTBL+1 /SET PTR TO CLKTBL FOR\r |
| 199 | /SETTING OF ENABLE REGS.\r |
| 200 | TAD CPTYP /=0 IF PDP8 =1 IF PDP12\r |
| 201 | DCA FCNPTR /TBL ENTRIES ALTERNATE\r |
| 202 | /FOR 8 AND 12. CPTYP SETS\r |
| 203 | /PTR TO 1ST 8 OR 1ST 12\r |
| 204 | /ENTRY\r |
| 205 | TAD IDOCLK /(AC=JMP AROUND). THE\r |
| 206 | /FOLLOWING IS ONCE ONLY\r |
| 207 | /CODE. THESE LOCS ARE\r |
| 208 | /SUBSEQUENTLY USED AS\r |
| 209 | /OPERANDS\r |
| 210 | DCA .-1\r |
| 211 | /THE TAG "ISVBIT" MUST BE\r |
| 212 | /IN FRONT OF THE STRIG\r |
| 213 | /FLAGS (STFLG) TO COVER\r |
| 214 | /THE ILLEGAL CASE OF\r |
| 215 | /STRIG 0 IN A FORT CALL\r |
| 216 | /TO SYNC.\r |
| 217 | ISVBIT, TAD CPTYP /(AC=0,1) MAKE THE INST\r |
| 218 | /RAR CLL (FOR DK) OR THE\r |
| 219 | /INST RTR CLL FOR IDOCLK;\r |
| 220 | STFLG, RAL CLL /BECAUSE STATUS BITS FOR\r |
| 221 | TAD RARCLL /STRIGS DIFFER ON DK,KW.\r |
| 222 | DCA LOP2+1 /SEE SUB IDOCLK.\r |
| 223 | /THE ABOVE 3 LOCS ARE\r |
| 224 | /SCHMITT TRIGGER FLAGS.\r |
| 225 | /THE ORDER IS S1,S2,S3\r |
| 226 | /FOR PDP8 AND S3,S2,S1\r |
| 227 | /FOR PDP12. (CHK THE STATUS\r |
| 228 | /BITS FOR DK AND KW).\r |
| 229 | JMS% KONQI+1 /PUT CLOCK ON THE\r |
| 230 | ITMP0, CLSK /INTERRUPT QUE\r |
| 231 | /VIA ONQI.\r |
| 232 | CLENAB, ADDR IDOCLK /THIS LOC WILL HOLD THE\r |
| 233 | /ENABLE BITS FOR DK,KW\r |
| 234 | AROUND, TAD RATE /(AC=0,2,3,4,5,6) RATE IS\r |
| 235 | /SET BY FPP\r |
| 236 | RTR CLL /START TO POSITION RATE\r |
| 237 | RAR /BITS. B3-B5 FOR DK\r |
| 238 | /B0-B2 FOR KW\r |
| 239 | TAD CPTYP /(THIS IS TRICKY) NEED\r |
| 240 | RAR /CPTYP IN LNK BECAUSE\r |
| 241 | /POSITION OF RATE BITS\r |
| 242 | /DIFFER FOR DK KW.\r |
| 243 | TAD% FCNPTR /AC="STANDARD"\r |
| 244 | /ENABLE BITS FOR DK,KW.\r |
| 245 | SZL /IF ITS A KW THE RATE AND\r |
| 246 | /AND STND BITS ARE ALREADY\r |
| 247 | /POSITIONED AS FOLLOWS:\r |
| 248 | /RRR011000000\r |
| 249 | /B0-B3 AND B5 WILL GO TO\r |
| 250 | /KW CONTROL. B4,B5 WILL\r |
| 251 | /GO TO ENABLE. B3 IS ADC\r |
| 252 | /ON OVRFLO AND MAY BE SET\r |
| 253 | /BELOW. B5 ON CONTROL IS\r |
| 254 | /MODE 1. B4 AND B5 ON\r |
| 255 | /ENABLE ARE BUFF PRESET TO\r |
| 256 | /CLOCK COUNTER AND INTRUPT\r |
| 257 | /ON OVRFLO RESPECTIVELY.\r |
| 258 | JMP NOBIT-1 /ITS KW GO PUT IN CLENAB.\r |
| 259 | RTR /ITS DK; POSITION RATE TO\r |
| 260 | RAR /B3-B5. NOTE THAT THE LNK\r |
| 261 | /(CPTYP=0) IS BEING USED.\r |
| 262 | CMA /NOTE ALSO THAT THE RATE\r |
| 263 | /AND STND BITS ARE THE 1S\r |
| 264 | /COMP. OF WHAT THEY SHOULD\r |
| 265 | /BE, IE CPTYP=LNK=0\r |
| 266 | /BECOMES\r |
| 267 | /B2=1 OF ENABLE=BUFF\r |
| 268 | /PRESET TO CLK CNTR ON\r |
| 269 | /OVERFLO. LOOK AT THE RATE\r |
| 270 | /BITS IN THE HANDBOOK FOR\r |
| 271 | /BOTH DK,KW. R2,R5\r |
| 272 | /FOR DK IS 100HZ, 100KHZ\r |
| 273 | /RESPECTIVELY. R2,R5 FOR\r |
| 274 | /KW IS 100KHZ,100HZ.\r |
| 275 | /1S COMP.OF 2=5 ETC.\r |
| 276 | /SMARTEN UP STEVE!\r |
| 277 | /THE FINAL VALUE OF THE\r |
| 278 | /STND DK ENABLE BITS (1ST\r |
| 279 | /ENTRY IN CLKTBL) IS LEFT\r |
| 280 | /AS AN EXERCISE FOR THE\r |
| 281 | /PROGRAMMER.\r |
| 282 | JMP NOBIT-1 /GO PUT IN CLENAB\r |
| 283 | LOP1, RAR CLL /ROT 1 FCN BIT INTO LNK.\r |
| 284 | /B7=EXT CLK AND IS\r |
| 285 | /IGNORED HERE. B8=ADC ON\r |
| 286 | /OVRFLO, B9-B11 ARE STRIG3\r |
| 287 | /-STRIG1 RESP. BX=1=ENABLE\r |
| 288 | /FCN. 0=DISABLE\r |
| 289 | DCA FCNWD /PUT IT BACK (FCNWD IS\r |
| 290 | /SET BY FPP)\r |
| 291 | SNL /ENABLE FCN ?\r |
| 292 | JMP NOBIT /NO\r |
| 293 | TAD% FCNPTR /GET BITS FROM THE MAGIC\r |
| 294 | TAD CLENAB /TABLE.\r |
| 295 | DCA CLENAB /UPDATE ENABLE WORD.\r |
| 296 | NOBIT, ISZ FCNPTR /ADV TO NEXT\r |
| 297 | ISZ FCNPTR /TBL ENTRY.\r |
| 298 | TAD FCNWD /WHEN FCNWD GOES TO 0\r |
| 299 | AND P17 /WE ARE ALL DONE.\r |
| 300 | /THE "AND" IS DONE TO\r |
| 301 | /PROTECT AGAINST A BAD\r |
| 302 | /ARG FROM THE FORT CALL.\r |
| 303 | P7540, SMA SZA /SMA IS SUPERFLOUS TO\r |
| 304 | /THE ROUT; BUT IT\r |
| 305 | /CREATES A NICE CONST.\r |
| 306 | JMP LOP1 /MORE TO DO\r |
| 307 | DCA STFLG /CLR THE SCHMITT\r |
| 308 | \f DCA STFLG+1 /TRIGGER FLAGS.\r |
| 309 | \f DCA STFLG+2\r |
| 310 | TAD OVRFLO /SET BUFF PRESET\r |
| 311 | CIA /(FPP SET THIS ARG)\r |
| 312 | / CLAB\r |
| 313 | CLA\r |
| 314 | TAD CLENAB /THIS IS FOR KW ONLY.\r |
| 315 | AND P377 /AC=3XX. 3= OR BUFF PRE\r |
| 316 | /INTO CLK CNTR AND ENAB\r |
| 317 | /INT ON OVRFLO.\r |
| 318 | /XX ARE THE STRIGS.\r |
| 319 | / CLEN /SET KW ENABLE OR\r |
| 320 | CLA /READ DK ENABLE.\r |
| 321 | DCA OVRCNT+1 /CLR NUM OF CLK OVRFLOS\r |
| 322 | DCA OVRCNT /SINCE TIME 0.\r |
| 323 | TAD CPTYP /NEED TYPE IN ORDER TO\r |
| 324 | RARCLL, RAR CLL /ISOLATE CONTROL\r |
| 325 | TAD CLENAB /BITS FOR\r |
| 326 | SZL /KW ?\r |
| 327 | AND P7540 /YES, B0-B2 IS RATE,\r |
| 328 | /B3 IS ADC, B5 IS BUFF\r |
| 329 | /PRE TO CLK CNTR ON\r |
| 330 | /OVRFLO, B6 IS MOX NIX.\r |
| 331 | /IF DK ALL BITS MAY HAVE\r |
| 332 | /MEANING\r |
| 333 | CLA IAC /SET BIT 11\r |
| 334 | CLLE /ENABLE THE CLOCK INTERRUPTS\r |
| 335 | / CLLR /START THE CLOCK\r |
| 336 | CLA\r |
| 337 | CIF CDF\r |
| 338 | JMP% SETCLK /RTN TO RTS\r |
| 339 | \fDOSYNC, 0 /HERE TO DISPOSITION A\r |
| 340 | /A SCHMITT TRIGGER.\r |
| 341 | TAD CPTYP /DK AND KW FLAGS ARE IN\r |
| 342 | RAR CLL /REVERSE ORDER. IF DK\r |
| 343 | /ARG IS OK; IF KW THEN\r |
| 344 | /MUST SET 1=3, 2=2, 3=1\r |
| 345 | /TO GET INDEX TO\r |
| 346 | /CORRECT FLAG.\r |
| 347 | TAD FCNWD /=REQUESTED STRIG=1,2,3\r |
| 348 | /(SET BY FPP)\r |
| 349 | SZL /DK ?\r |
| 350 | CIA /NO KW\r |
| 351 | AND P3 /IE 1 GOES TO -1 GOES\r |
| 352 | /TO 3 ETC. "AND" ALSO\r |
| 353 | /INSURES RANGE IS 0-3.\r |
| 354 | /IF ARG IS 0 RESULT IS\r |
| 355 | /ALWAYS 0.\r |
| 356 | TAD KSTFLG+1 /GET PTR TO FLAG\r |
| 357 | DCA SETCLK\r |
| 358 | TAD% SETCLK /FLAG=0 IF TRIG HAS NOT\r |
| 359 | /TRIPPED SINCE THE LAST\r |
| 360 | /CALL TO SYNC; =1\r |
| 361 | /OTHERWISE IE RTN 0=FALSE\r |
| 362 | DCA FCNWD /,1=TRUE (FPP WILL PICK\r |
| 363 | / UP FCNWD)\r |
| 364 | DCA% SETCLK /CLR FLAG ANYWAY\r |
| 365 | CIF CDF\r |
| 366 | JMP% DOSYNC /RTN TO RTS\r |
| 367 | \fIDOCLK, JMP AROUND /HERE ON CLOCK INTERRUPT\r |
| 368 | /(JMP AROUND IS A ONCE\r |
| 369 | /ONLY CONSTANT).\r |
| 370 | CLCL /JUST TO MAKE SURE!\r |
| 371 | TAD KSTFLG+1 /SET PTR TO STRIG FLAGS.\r |
| 372 | DCA ITMP0\r |
| 373 | / CLSA /GET CLOCK BITS.\r |
| 374 | CLA CLL CML RAR /SIMULATE TICK\r |
| 375 | DCAZ CSTAT /SAVE THEM FOR SOME\r |
| 376 | TADZ CSTAT /BODY ELSE.\r |
| 377 | SPA /OVER FLOW ?\r |
| 378 | ISZ OVRCNT+1 /YES BUMP LO ORD CNTR\r |
| 379 | SKP\r |
| 380 | ISZ OVRCNT /BUMP HI ORD\r |
| 381 | JMP DOTRIG /(HI ORD ISZ SKP IS\r |
| 382 | /HARMLESS)\r |
| 383 | LOP2, ISZ ITMP0 /ADV STRIG FLAG PTR.\r |
| 384 | RAR CLL /(OR RTR CLL IF KW)\r |
| 385 | /IE PUT STRIG BIT IN LNK.\r |
| 386 | /IF DK THE ORDER OF\r |
| 387 | /INTERROGATION IS S1,S2,S3\r |
| 388 | /IF KW THE ORDER IS S3,\r |
| 389 | /S2,S1. THE STATUS BITS\r |
| 390 | /FOR DK ARE ADJACENT IE\r |
| 391 | / B9(S3),B10(S2),B11(S1)\r |
| 392 | /FOR KW ITS EVERY OTHER,\r |
| 393 | /B6(S1),B8(S2),B10(S3).\r |
| 394 | DCA ISVBIT /SAVE WHATS LEFT.\r |
| 395 | RAL /COPY LNK INTO FLAG IF=1\r |
| 396 | SZA /IE DONT CLR FLAG WHEN\r |
| 397 | DCA% ITMP0 /ITS SET.\r |
| 398 | TAD ISVBIT\r |
| 399 | DOTRIG, AND P377 /THE "AND" INSURES THAT\r |
| 400 | /THE HI ORD BITS ARE\r |
| 401 | /CLRED SO THAT ISVBIT\r |
| 402 | /GOES TO 0 WHEN ALL\r |
| 403 | /STRIGS HAVE BEEN\r |
| 404 | /DISPOSITIONED. IE\r |
| 405 | /CLR OVRFLO BIT FOR DK,KW\r |
| 406 | /AND CLR PRE-EVENT BIT\r |
| 407 | /ON KW IF IT IS SET\r |
| 408 | SZA /DONE ?\r |
| 409 | JMP LOP2 /NO\r |
| 410 | TAD #CLINT /CALL USER EXTENDED\r |
| 411 | SZA CLA /CLOCK ROUT ?\r |
| 412 | JMS% #CLINT+1 /YES\r |
| 413 | JMP% IDOCLK /RTN TO IHANDL\r |
| 414 | \fFCNPTR,\r |
| 415 | OVRCNT,\r |
| 416 | KONQI, ADDR ONQI\r |
| 417 | P17, 17\r |
| 418 | P377, 377\r |
| 419 | FCNWD, 0 /FPP XRS\r |
| 420 | CPTYP, 0\r |
| 421 | RATE, 0\r |
| 422 | P1, 1\r |
| 423 | P2, 2\r |
| 424 | OVRFLO,\r |
| 425 | FCNTBL, ADDR CLKTBL\r |
| 426 | KSTFLG, ADDR STFLG-1\r |
| 427 | ENTRY #CLINT\r |
| 428 | #CLINT, 0;0\r |
| 429 | ENTRY TIME /FIGURE WHAT TIME IT IS\r |
| 430 | TIME, JSA SETUP\r |
| 431 | FLDA RPTR /=27;X;X IS USED TO FLOAT\r |
| 432 | STARTD\r |
| 433 | FLDA# OVRCNT /NUM OF CLK OVRFLOS SINCE\r |
| 434 | STARTF /TIME 0\r |
| 435 | FNORM\r |
| 436 | FMUL TOVR /=NUM OF BASIC TICKS PER\r |
| 437 | /CLOCK OVER FLOW.\r |
| 438 | /FAC=NUM OF TICKS SINCE\r |
| 439 | /TIME 0.\r |
| 440 | FDIV% RPTR,RATE /DIV BY BASIC RATE IN HZ\r |
| 441 | /OR 1 IF EXTERNAL CLK.\r |
| 442 | FSTA% FTMP0 /GIVE ANS TO CALLER, ALSO\r |
| 443 | /LEAVE ANS IN FAC IN\r |
| 444 | /CASE TIME WAS A FCN\r |
| 445 | /CALL. ANS=ELAPSED TIME IN\r |
| 446 | /SECONDS SINCE TIME 0 OR\r |
| 447 | /NUM OF EXTERNAL UNIT\r |
| 448 | JA GOBAK /TICKS\r |
| 449 | \f\1a\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0 |