| 1 | / -+-+-+-+-+ \ e H P X O U T. R A \ e -+-+-+-+-+\r |
| 2 | /\r |
| 3 | / F 4 SUBROUTINE XOUT (LEVEL)\r |
| 4 | /\r |
| 5 | / THE INTEGER LEVEL IS LOADED INTO THE VC8E DISPLAY X REGISTER\r |
| 6 | /\r |
| 7 | / THE VC8-E ENABLE REGISTER IS CLEARED AND THEN WE LOAD THE X REGISTER.\r |
| 8 | / THE DONE FLAG IS NOT TESTED.\r |
| 9 | /\r |
| 10 | / HARDWARE REQUIRED: LAB8/E, HARD/SOFT FPP12, VC8-E\r |
| 11 | /\r |
| 12 | / VER 0.0 12-MAR-81 HA\r |
| 13 | /\r |
| 14 | /\r |
| 15 | SECT XOUT\r |
| 16 | / ENTRY XOUT / CALL XOUT (LEVEL); INTEGER LEVEL\r |
| 17 | ENTRY YOUT / CALL YOUT (LEVEL); INTEGER LEVEL\r |
| 18 | JA #XOUT / HERE TO REDUCE # OF EXT. REFS FOR THE LOADER\r |
| 19 | /\r |
| 20 | DILE= 6056 / LOAD DISPLAY ENABLE REGISTER\r |
| 21 | DILX= 6053 / LOAD VC8E X REGISTER\r |
| 22 | DILY= 6054 / LOAD VC8E Y REGISTER\r |
| 23 | CDI= 6203 / COMBINED CDF++CIF\r |
| 24 | /\r |
| 25 | /\r |
| 26 | TWO, 0;2 / USED TO FETCH THE ARGUMENT LIST\r |
| 27 | CXOUT, DILX; NOP / LOADS X REGISTER\r |
| 28 | CYOUT, DILY; NOP / LOADS Y REGISTER (MUST BE TWO WORDS FOR FPP 2 WORD STORE)\r |
| 29 | BASE 0 / STAY ON CALLERS BASE PAGE\r |
| 30 | /\r |
| 31 | #XOUT, STARTD / CALL XOUT (LEVEL)\r |
| 32 | FLDA CXOUT / INSERT CORRECT COMMAND INTO THE 8 CODE ROUTINE\r |
| 33 | JMP STORIT\r |
| 34 | YOUT, STARTD / CALL YOUT (LEVEL)\r |
| 35 | FLDA CYOUT\r |
| 36 | STORIT, FSTA COMAND / INSERT CODE ONTO 8 MODE SCTION\r |
| 37 | /\r |
| 38 | FLDA 10*3 / SAVE THE RETURN ADR.\r |
| 39 | FSTA GOBAK\r |
| 40 | FLDA 0 / LOAD THE ADR. OF THE ARGUMENT LIST\r |
| 41 | FADD TWO / INCREMENT TO GET THE FIRST ARGUMENT\r |
| 42 | FSTA 3 / TEMP FOR INDIRECT REF.\r |
| 43 | FLDA% 3 / GET THE ADR. OF THE ARGUMENT\r |
| 44 | FSTA 3\r |
| 45 | STARTF\r |
| 46 | FLDA% 3 / AND LOAD THE ARGUMENT\r |
| 47 | SETX XR / WE CONVERT THE FRACTIONAL INTO INTEGER\r |
| 48 | ATX X1 / FOR THE PDP CODE\r |
| 49 | TRAP4 OUT8 / PDP8/E DOES THE WORK\r |
| 50 | GOBAK, JA . / HOME\r |
| 51 | /\r |
| 52 | / \ eC H S L . R A\r |
| 53 | /\r |
| 54 | / F 4 SUBROUTINE CHSL (SELECT BIT)\r |
| 55 | /\r |
| 56 | / THE INTEGER SELECT BIT IS LOADED INTO THE VC8E DISPLAY CHANNEL SELECT BIT OF THE ENABLE REGISTER\r |
| 57 | /\r |
| 58 | / THE VC8-E INTERRUPT BIT IS ALWAYS CLEARED.\r |
| 59 | /\r |
| 60 | / HARDWARE REQUIRED: LAB8/E, HARD/SOFT FPP12, VC8-E\r |
| 61 | /\r |
| 62 | / VER 0.0 12-MAY-81 HA\r |
| 63 | /\r |
| 64 | /\r |
| 65 | ENTRY CHSL / CALL CHSL (LEVEL); INTEGER LEVEL\r |
| 66 | /\r |
| 67 | /\r |
| 68 | BASE 0 / STAY ON CALLERS BASE PAGE\r |
| 69 | CHSL, STARTD / CALL CHSL (LEVEL)\r |
| 70 | FLDA 10*3 / SAVE THE RETURN ADR.\r |
| 71 | FSTA GOHOME\r |
| 72 | FLDA 0 / LOAD THE ADR. OF THE ARGUMENT LIST\r |
| 73 | FADD TWO / INCREMENT TO GET THE FIRST ARGUMENT\r |
| 74 | FSTA 3 / TEMP FOR INDIRECT REF.\r |
| 75 | FLDA% 3 / GET THE ADR. OF THE ARGUMENT\r |
| 76 | FSTA 3\r |
| 77 | STARTF\r |
| 78 | FLDA% 3 / AND LOAD THE ARGUMENT\r |
| 79 | SETX XR / WE CONVERT THE FRACTIONAL INTO INTEGER\r |
| 80 | ATX X1 / FOR THE PDP CODE\r |
| 81 | TRAP4 CHSL8 / PDP8/E DOES THE WORK\r |
| 82 | GOHOME, JA . / HOME\r |
| 83 | /\r |
| 84 | /\r |
| 85 | SECT8 #OUT8\r |
| 86 | XR, ORG .+2 / X REGISTER SET\r |
| 87 | X0= 0 / NOT USED\r |
| 88 | X1= X0+1 / THE LEVEL LOADED INTO THE X REGISTER\r |
| 89 | /\r |
| 90 | /\r |
| 91 | OUT8, 0 / \r |
| 92 | CLA / CLEAR THE VC8-E ENABLE REGISTER\r |
| 93 | DILE\r |
| 94 | TAD X1 / AND THEN WE LOAD\r |
| 95 | COMAND, DILX; NOP / THE X REGISTER (NOP MUST BE HERE FOR FPP 2 WORD STORE)\r |
| 96 | CDI\r |
| 97 | JMP% OUT8 / SEE YOU LATER\r |
| 98 | /\r |
| 99 | /\r |
| 100 | /\r |
| 101 | CHSL8, 0 / \r |
| 102 | CLA / CLEAR THE VC8-E ENABLE REGISTER\r |
| 103 | TAD X1 / AND LOAD THE CHANNEL SELECT BIT\r |
| 104 | RAL / SHIFT INTO THE CORRECT POSITION\r |
| 105 | DILE\r |
| 106 | CDI\r |
| 107 | JMP% CHSL8 / SEE YOU LATER\r |
| 108 | END\r |
| 109 | \1a\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0 |