1 /*************************************************************************
3 * $Id: s100_selchan.c 1771 2008-01-09 07:10:46Z hharte $ *
5 * Copyright (c) 2007-2008 Howard M. Harte. *
6 * http://www.hartetec.com *
8 * Permission is hereby granted, free of charge, to any person obtaining *
9 * a copy of this software and associated documentation files (the *
10 * "Software"), to deal in the Software without restriction, including *
11 * without limitation the rights to use, copy, modify, merge, publish, *
12 * distribute, sublicense, and/or sell copies of the Software, and to *
13 * permit persons to whom the Software is furnished to do so, subject to *
14 * the following conditions: *
16 * The above copyright notice and this permission notice shall be *
17 * included in all copies or substantial portions of the Software. *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND *
22 * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY *
23 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, *
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE *
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *
27 * Except as contained in this notice, the name of Howard M. Harte shall *
28 * not be used in advertising or otherwise to promote the sale, use or *
29 * other dealings in this Software without prior written authorization *
32 * SIMH Interface based on altairz80_hdsk.c, by Peter Schorn. *
34 * Module Description: *
35 * CompuPro Selector Channel module for SIMH. *
40 *************************************************************************/
44 #include "altairz80_defs.h"
51 #define DBG_PRINT(args) printf args
53 #define DBG_PRINT(args)
56 #define TRACE_MSG 0x01
59 #define SELCHAN_MAX_DRIVES 1
61 #define UNIT_V_SELCHAN_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */
62 #define UNIT_SELCHAN_VERBOSE (1 << UNIT_V_SELCHAN_VERBOSE)
65 PNP_INFO pnp
; /* Plug and Play */
66 uint32 selchan
; /* Selector Channel Register */
67 uint32 dma_addr
; /* DMA Transfer Address */
68 uint32 dma_mode
; /* DMA Mode register */
69 uint8 reg_cnt
; /* Counter for selchan register */
72 static SELCHAN_INFO selchan_info_data
= { { 0x0, 0, 0xF0, 1 } };
73 static SELCHAN_INFO
*selchan_info
= &selchan_info_data
;
74 int32
selchan_dma(uint8
*buf
, uint32 len
);
76 extern t_stat
set_iobase(UNIT
*uptr
, int32 val
, char *cptr
, void *desc
);
77 extern t_stat
show_iobase(FILE *st
, UNIT
*uptr
, int32 val
, void *desc
);
78 extern uint32
sim_map_resource(uint32 baseaddr
, uint32 size
, uint32 resource_type
,
79 int32 (*routine
)(const int32
, const int32
, const int32
), uint8 unmap
);
83 /* These are needed for DMA. PIO Mode has not been implemented yet. */
84 extern void PutBYTEWrapper(const uint32 Addr
, const uint32 Value
);
85 extern uint8
GetBYTEWrapper(const uint32 Addr
);
87 static t_stat
selchan_reset(DEVICE
*selchan_dev
);
89 static int32
selchandev(const int32 port
, const int32 io
, const int32 data
);
91 static int32 trace_level
= 0; /* Disable all tracing by default */
93 static UNIT selchan_unit
[] = {
94 { UDATA (NULL
, UNIT_FIX
+ UNIT_DISABLE
+ UNIT_ROABLE
, 0) }
97 static REG selchan_reg
[] = {
98 { HRDATA (TRACELEVEL
, trace_level
, 16), },
102 static MTAB selchan_mod
[] = {
103 { MTAB_XTD
|MTAB_VDV
, 0, "IOBASE", "IOBASE", &set_iobase
, &show_iobase
, NULL
},
104 /* quiet, no warning messages */
105 { UNIT_SELCHAN_VERBOSE
, 0, "QUIET", "QUIET", NULL
},
106 /* verbose, show warning messages */
107 { UNIT_SELCHAN_VERBOSE
, UNIT_SELCHAN_VERBOSE
, "VERBOSE", "VERBOSE", NULL
},
111 DEVICE selchan_dev
= {
112 "SELCHAN", selchan_unit
, selchan_reg
, selchan_mod
,
113 SELCHAN_MAX_DRIVES
, 10, 31, 1, SELCHAN_MAX_DRIVES
, SELCHAN_MAX_DRIVES
,
114 NULL
, NULL
, &selchan_reset
,
116 &selchan_info_data
, (DEV_DISABLE
| DEV_DIS
), 0,
121 static t_stat
selchan_reset(DEVICE
*dptr
)
123 PNP_INFO
*pnp
= (PNP_INFO
*)dptr
->ctxt
;
125 if(dptr
->flags
& DEV_DIS
) { /* Disconnect I/O Ports */
126 sim_map_resource(pnp
->io_base
, pnp
->io_size
, RESOURCE_TYPE_IO
, &selchandev
, TRUE
);
128 /* Connect SELCHAN at base address */
129 if(sim_map_resource(pnp
->io_base
, pnp
->io_size
, RESOURCE_TYPE_IO
, &selchandev
, FALSE
) != 0) {
130 printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__
, pnp
->io_base
);
137 #define SELCHAN_MODE_WRITE 0x80 /* Selector Channel Memory or I/O Write */
138 #define SELCHAN_MODE_IO 0x40 /* Set if I/O Access, otherwise memory */
139 #define SELCHAN_MODE_CNT_UP 0x20 /* Set = DMA Address Count Up, otherwise down. (Mem only */
140 #define SELCHAN_MODE_WAIT 0x10 /* Insert one wait state. */
141 #define SELCHAN_MODE_DMA_MASK 0x0F /* Mask for DMA Priority field */
143 static int32
selchandev(const int32 port
, const int32 io
, const int32 data
)
145 DBG_PRINT(("SELCHAN: IO %s, Port %02x" NLP
, io
? "WR" : "RD", port
));
147 selchan_info
->selchan
<<= 8;
148 selchan_info
->selchan
&= 0xFFFFFF00;
149 selchan_info
->selchan
|= data
;
151 selchan_info
->dma_addr
= (selchan_info
->selchan
& 0xFFFFF00) >> 8;
152 selchan_info
->dma_mode
= (selchan_info
->selchan
& 0xFF);
154 selchan_info
->reg_cnt
++;
156 if(selchan_info
->reg_cnt
== 4) {
157 TRACE_PRINT(TRACE_MSG
, ("SELCHAN: " ADDRESS_FORMAT
" DMA=0x%06x, Mode=0x%02x (%s, %s, %s)" NLP
,
159 selchan_info
->dma_addr
,
160 selchan_info
->dma_mode
,
161 selchan_info
->dma_mode
& SELCHAN_MODE_WRITE
? "WR" : "RD",
162 selchan_info
->dma_mode
& SELCHAN_MODE_IO
? "I/O" : "MEM",
163 selchan_info
->dma_mode
& SELCHAN_MODE_IO
? "FIX" : selchan_info
->dma_mode
& SELCHAN_MODE_CNT_UP
? "INC" : "DEC"));
168 TRACE_PRINT(TRACE_MSG
, ("SELCHAN: " ADDRESS_FORMAT
" Reset" NLP
, PCX
));
169 selchan_info
->reg_cnt
= 0;
174 int32
selchan_dma(uint8
*buf
, uint32 len
)
178 if(selchan_info
->reg_cnt
!= 4) {
179 printf("SELCHAN: " ADDRESS_FORMAT
" Programming error: selector channel disabled." NLP
,
184 if(selchan_info
->dma_mode
& SELCHAN_MODE_IO
)
186 printf("SELCHAN: " ADDRESS_FORMAT
" I/O Not supported" NLP
, PCX
);
189 TRACE_PRINT(DMA_MSG
, ("SELCHAN: " ADDRESS_FORMAT
" DMA %s Transfer, len=%d" NLP
,
191 (selchan_info
->dma_mode
& SELCHAN_MODE_WRITE
) ? "WR" : "RD", len
));
193 if(selchan_info
->dma_mode
& SELCHAN_MODE_WRITE
) {
194 PutBYTEWrapper(selchan_info
->dma_addr
+ i
, buf
[i
]);
196 buf
[i
] = GetBYTEWrapper(selchan_info
->dma_addr
+ i
);
200 if(selchan_info
->dma_mode
& SELCHAN_MODE_CNT_UP
) {
201 selchan_info
->dma_addr
+= i
;
203 selchan_info
->dma_addr
-= i
;