1 /*************************************************************************
3 * $Id: s100_ss1.c 1773 2008-01-11 05:46:19Z hharte $ *
5 * Copyright (c) 2007-2008 Howard M. Harte. *
6 * http://www.hartetec.com *
8 * Permission is hereby granted, free of charge, to any person obtaining *
9 * a copy of this software and associated documentation files (the *
10 * "Software"), to deal in the Software without restriction, including *
11 * without limitation the rights to use, copy, modify, merge, publish, *
12 * distribute, sublicense, and/or sell copies of the Software, and to *
13 * permit persons to whom the Software is furnished to do so, subject to *
14 * the following conditions: *
16 * The above copyright notice and this permission notice shall be *
17 * included in all copies or substantial portions of the Software. *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *
20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND *
22 * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY *
23 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, *
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE *
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *
27 * Except as contained in this notice, the name of Howard M. Harte shall *
28 * not be used in advertising or otherwise to promote the sale, use or *
29 * other dealings in this Software without prior written authorization *
32 * SIMH Interface based on altairz80_hdsk.c, by Peter Schorn. *
34 * Module Description: *
35 * CompuPro System Support 1 module for SIMH. *
36 * Note this does not include the Boot ROM on the System Support 1 Card *
41 *************************************************************************/
45 #include "altairz80_defs.h"
52 #define DBG_PRINT(args) printf args
54 #define DBG_PRINT(args)
57 #define TRACE_MSG 0x01
60 #define SS1_MAX_DRIVES 1
62 #define UNIT_V_SS1_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */
63 #define UNIT_SS1_VERBOSE (1 << UNIT_V_SS1_VERBOSE)
66 PNP_INFO pnp
; /* Plug and Play */
69 static SS1_INFO ss1_info_data
= { { 0x0, 0, 0x50, 12 } };
70 /* static SS1_INFO *ss1_info = &ss1_info_data;*/
72 extern t_stat
set_iobase(UNIT
*uptr
, int32 val
, char *cptr
, void *desc
);
73 extern t_stat
show_iobase(FILE *st
, UNIT
*uptr
, int32 val
, void *desc
);
74 extern uint32
sim_map_resource(uint32 baseaddr
, uint32 size
, uint32 resource_type
,
75 int32 (*routine
)(const int32
, const int32
, const int32
), uint8 unmap
);
79 /* These are needed for DMA. PIO Mode has not been implemented yet. */
80 extern void PutBYTEWrapper(const uint32 Addr
, const uint32 Value
);
81 extern uint8
GetBYTEWrapper(const uint32 Addr
);
83 static t_stat
ss1_reset(DEVICE
*ss1_dev
);
84 static uint8
SS1_Read(const uint32 Addr
);
85 static uint8
SS1_Write(const uint32 Addr
, uint8 cData
);
88 static int32
ss1dev(const int32 port
, const int32 io
, const int32 data
);
90 static int32 trace_level
= 0x00; /* Disable all tracing by default */
92 static UNIT ss1_unit
[] = {
93 { UDATA (NULL
, UNIT_FIX
+ UNIT_DISABLE
+ UNIT_ROABLE
, 0) }
96 static REG ss1_reg
[] = {
97 { HRDATA (TRACELEVEL
, trace_level
, 16), },
101 static MTAB ss1_mod
[] = {
102 { MTAB_XTD
|MTAB_VDV
, 0, "IOBASE", "IOBASE", &set_iobase
, &show_iobase
, NULL
},
103 /* quiet, no warning messages */
104 { UNIT_SS1_VERBOSE
, 0, "QUIET", "QUIET", NULL
},
105 /* verbose, show warning messages */
106 { UNIT_SS1_VERBOSE
, UNIT_SS1_VERBOSE
, "VERBOSE", "VERBOSE", NULL
},
111 "SS1", ss1_unit
, ss1_reg
, ss1_mod
,
112 SS1_MAX_DRIVES
, 10, 31, 1, SS1_MAX_DRIVES
, SS1_MAX_DRIVES
,
113 NULL
, NULL
, &ss1_reset
,
115 &ss1_info_data
, (DEV_DISABLE
| DEV_DIS
), 0,
120 static t_stat
ss1_reset(DEVICE
*dptr
)
122 PNP_INFO
*pnp
= (PNP_INFO
*)dptr
->ctxt
;
124 if(dptr
->flags
& DEV_DIS
) { /* Disconnect I/O Ports */
125 sim_map_resource(pnp
->io_base
, pnp
->io_size
, RESOURCE_TYPE_IO
, &ss1dev
, TRUE
);
127 /* Connect SS1 at base address */
128 if(sim_map_resource(pnp
->io_base
, pnp
->io_size
, RESOURCE_TYPE_IO
, &ss1dev
, FALSE
) != 0) {
129 printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__
, pnp
->io_base
);
136 static int32
ss1dev(const int32 port
, const int32 io
, const int32 data
)
138 DBG_PRINT(("SS1: IO %s, Port %02x\n", io
? "WR" : "RD", port
));
140 SS1_Write(port
, data
);
143 return(SS1_Read(port
));
147 #define SS1_M8259_L 0x00
148 #define SS1_M8259_H 0x01
149 #define SS1_S8259_L 0x02
150 #define SS1_S8259_H 0x03
151 #define SS1_8253_TC0 0x04
152 #define SS1_8253_TC1 0x05
153 #define SS1_8253_TC2 0x06
154 #define SS1_8253_CTL 0x07
155 #define SS1_9511A_DATA 0x08
156 #define SS1_9511A_CMD 0x09
157 #define SS1_RTC_CMD 0x0A
158 #define SS1_RTC_DATA 0x0B
159 #define SS1_UART_DATA 0x0C
160 #define SS1_UART_STAT 0x0D
161 #define SS1_UART_MODE 0x0E
162 #define SS1_UART_CMD 0x0F
164 extern int32
sio0d(const int32 port
, const int32 io
, const int32 data
);
165 extern int32
sio0s(const int32 port
, const int32 io
, const int32 data
);
167 static uint8
SS1_Read(const uint32 Addr
)
171 switch(Addr
& 0x0F) {
176 TRACE_PRINT(TRACE_MSG
, ("SS1: " ADDRESS_FORMAT
" RD: Interrupt Controller not Implemented." NLP
, PCX
));
182 TRACE_PRINT(TRACE_MSG
, ("SS1: " ADDRESS_FORMAT
" RD: Timer not Implemented." NLP
, PCX
));
186 TRACE_PRINT(TRACE_MSG
, ("SS1: " ADDRESS_FORMAT
" RD: Math Coprocessor not Implemented." NLP
, PCX
));
190 TRACE_PRINT(TRACE_MSG
, ("SS1: " ADDRESS_FORMAT
" RD: RTC not Implemented." NLP
, PCX
));
193 cData
= sio0d(Addr
, 0, 0);
196 cData
= sio0s(Addr
, 0, 0);
200 TRACE_PRINT(TRACE_MSG
, ("SS1: " ADDRESS_FORMAT
" RD: UART not Implemented." NLP
, PCX
));
208 static uint8
SS1_Write(const uint32 Addr
, uint8 cData
)
211 switch(Addr
& 0x0F) {
216 TRACE_PRINT(TRACE_MSG
, ("SS1: " ADDRESS_FORMAT
" WR: Interrupt Controller not Implemented." NLP
, PCX
));
222 TRACE_PRINT(TRACE_MSG
, ("SS1: " ADDRESS_FORMAT
" WR: Timer not Implemented." NLP
, PCX
));
226 TRACE_PRINT(TRACE_MSG
, ("SS1: " ADDRESS_FORMAT
" WR: Math Coprocessor not Implemented." NLP
, PCX
));
230 TRACE_PRINT(TRACE_MSG
, ("SS1: " ADDRESS_FORMAT
" WR: RTC not Implemented." NLP
, PCX
));
233 sio0d(Addr
, 1, cData
);
236 sio0s(Addr
, 1, cData
);
240 TRACE_PRINT(TRACE_MSG
, ("SS1: " ADDRESS_FORMAT
" WR: UART not Implemented." NLP
, PCX
));