1 /* i7094_clk.c: IBM 7094 clock
3 Copyright (c) 2003-2006, Robert M. Supnik
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
26 clk RPQ F89349 interval timer
27 Chronolog calendar clock
30 #include "i7094_defs.h"
36 t_stat
clk_svc (UNIT
*uptr
);
37 t_stat
clk_reset (DEVICE
*dptr
);
38 uint8
bcd_2d (uint32 n
, uint8
*b2
);
40 /* CLK data structures
42 clk_dev CLK device descriptor
44 clk_reg CLK register list
47 UNIT clk_unit
= { UDATA (&clk_svc
, 0, 0), 16000 };
50 { FLDATA (TRAP
, chtr_clk
, 0) },
51 { DRDATA (TIME
, clk_unit
.wait
, 24), REG_NZ
+ PV_LEFT
},
56 "CLK", &clk_unit
, clk_reg
, NULL
,
58 NULL
, NULL
, &clk_reset
,
60 NULL
, DEV_DISABLE
+DEV_DIS
63 /* Clock unit service */
65 t_stat
clk_svc (UNIT
*uptr
)
69 if ((clk_dev
.flags
& DEV_DIS
) == 0) { /* clock enabled? */
70 ctr
= ReadP (CLK_CTR
);
71 ctr
= (ctr
+ 1) & DMASK
; /* increment */
72 WriteP (CLK_CTR
, ctr
);
73 if ((ctr
& MMASK
) == 0) chtr_clk
= 1; /* overflow? req trap */
74 sim_activate (uptr
, sim_rtcn_calb (CLK_TPS
, TMR_CLK
)); /* reactivate unit */
81 uint32
chrono_rd (uint8
*buf
, uint32 bufsiz
)
87 if (bufsiz
< 12) return 0;
88 curtim
= time (NULL
); /* get time */
89 tptr
= localtime (&curtim
); /* decompose */
90 if (tptr
== NULL
) return 0; /* error? */
92 buf
[0] = bcd_2d (tptr
->tm_mon
+ 1, buf
+ 1);
93 buf
[2] = bcd_2d (tptr
->tm_mday
, buf
+ 3);
94 buf
[4] = bcd_2d (tptr
->tm_hour
, buf
+ 5);
95 buf
[6] = bcd_2d (tptr
->tm_min
, buf
+ 7);
96 buf
[8] = bcd_2d (tptr
->tm_sec
, buf
+ 9);
97 ctr
= ReadP (CLK_CTR
);
98 buf
[10] = bcd_2d ((uint32
) (ctr
% 60), buf
+ 11);
102 /* Convert number (0-99) to BCD */
104 uint8
bcd_2d (uint32 n
, uint8
*b2
)
110 if (d1
== 0) d1
= BCD_ZERO
;
111 if (d2
== 0) d2
= BCD_ZERO
;
112 if (b2
!= NULL
) *b2
= d2
;
118 t_stat
clk_reset (DEVICE
*dptr
)
121 if (clk_dev
.flags
& DEV_DIS
) sim_cancel (&clk_unit
);
122 else sim_activate (&clk_unit
, sim_rtcn_init (clk_unit
.wait
, TMR_CLK
));