1 /* pdp1_clk.c: PDP-1D clock simulator
3 Copyright (c) 2006, Robert M. Supnik
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 bused in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
28 Note that the clock is run at 1/8 of real speed (125Hz instead of 1Khz), to
29 provide for eventual implementation of idling.
32 #include "pdp1_defs.h"
34 #define CLK_HWRE_TPS 1000 /* hardware freq */
35 #define CLK_TPS 125 /* sim freq */
36 #define CLK_CNTS (CLK_HWRE_TPS / CLK_TPS) /* counts per tick */
37 #define CLK_C1MIN (1000 * 60) /* counts per min */
38 #define CLK_C32MS 32 /* counts per 32ms */
40 int32 clk32ms_sbs
= 0; /* 32ms SBS level */
41 int32 clk1min_sbs
= 0; /* 1min SBS level */
43 int32 tmxr_poll
= 5000;
45 extern int32 stop_inst
;
47 t_stat
clk_svc (UNIT
*uptr
);
48 t_stat
clk_reset (DEVICE
*dptr
);
50 /* CLK data structures
52 clk_dev CLK device descriptor
54 clk_reg CLK register list
58 UDATA (&clk_svc
, 0, 0), 5000
62 { ORDATA (CNTR
, clk_cntr
, 16) },
63 { DRDATA (SBS32LVL
, clk32ms_sbs
, 4), REG_HRO
},
64 { DRDATA (SBS1MLVL
, clk1min_sbs
, 4), REG_HRO
},
69 { MTAB_XTD
|MTAB_VDV
, 0, "SBS32MSLVL", "SBS32MSLVL",
70 &dev_set_sbs
, &dev_show_sbs
, (void *) &clk32ms_sbs
},
71 { MTAB_XTD
|MTAB_VDV
, 0, "SBS1MINLVL", "SBS1MINLVL",
72 &dev_set_sbs
, &dev_show_sbs
, (void *) &clk1min_sbs
},
77 "CLK", &clk_unit
, clk_reg
, clk_mod
,
79 NULL
, NULL
, &clk_reset
,
81 NULL
, DEV_DISABLE
| DEV_DIS
84 /* Clock IOT routine */
86 int32
clk (int32 inst
, int32 dev
, int32 dat
)
90 if (clk_dev
.flags
& DEV_DIS
) /* disabled? */
91 return (stop_inst
<< IOT_V_REASON
) | dat
; /* illegal inst */
92 used
= tmxr_poll
- (sim_is_active (&clk_unit
) - 1);
93 incr
= (used
* CLK_CNTS
) / tmxr_poll
;
94 return clk_cntr
+ incr
;
97 /* Unit service, generate appropriate interrupts */
99 t_stat
clk_svc (UNIT
*uptr
)
101 if (clk_dev
.flags
& DEV_DIS
) return SCPE_OK
; /* disabled? */
102 tmxr_poll
= sim_rtcn_calb (CLK_TPS
, TMR_CLK
); /* calibrate clock */
103 sim_activate (&clk_unit
, tmxr_poll
); /* reactivate unit */
104 clk_cntr
= clk_cntr
+ CLK_CNTS
; /* incr counter */
105 if ((clk_cntr
% CLK_C32MS
) == 0) /* 32ms interval? */
106 dev_req_int (clk32ms_sbs
); /* req intr */
107 if (clk_cntr
>= CLK_C1MIN
) { /* 1min interval? */
108 dev_req_int (clk1min_sbs
); /* req intr */
109 clk_cntr
= 0; /* reset counter */
116 t_stat
clk_reset (DEVICE
*dptr
)
118 if (clk_dev
.flags
& DEV_DIS
) sim_cancel (&clk_unit
); /* disabled? */
120 tmxr_poll
= sim_rtcn_init (clk_unit
.wait
, TMR_CLK
);
121 sim_activate_abs (&clk_unit
, tmxr_poll
); /* activate unit */
123 clk_cntr
= 0; /* clear counter */