1 /* pdp11_rl.c: RL11 (RLV12) cartridge disk simulator
3 Copyright (c) 1993-2005, Robert M Supnik
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
26 rl RL11(RLV12)/RL01/RL02 cartridge disk
28 22-Sep-05 RMS Fixed declarations (from Sterling Garwood)
29 16-Aug-05 RMS Fixed C++ declaration and cast problems
30 07-Jul-05 RMS Removed extraneous externs
31 30-Sep-04 RMS Revised Unibus interface
32 04-Jan-04 RMS Changed sim_fsize calling sequence
33 19-May-03 RMS Revised for new conditional compilation scheme
34 25-Apr-03 RMS Revised for extended file support
35 29-Sep-02 RMS Added variable address support to bootstrap
36 Added vector change/display support
37 Revised mapping nomenclature
39 26-Jan-02 RMS Revised bootstrap to conform to M9312
40 06-Jan-02 RMS Revised enable/disable support
41 30-Nov-01 RMS Added read only, extended SET/SHOW support
42 26-Nov-01 RMS Fixed per-drive error handling
43 24-Nov-01 RMS Converted FLG, CAPAC to arrays
44 19-Nov-01 RMS Fixed signed/unsigned mismatch in write check
45 09-Nov-01 RMS Added bus map, VAX support
46 07-Sep-01 RMS Revised device disable and interrupt mechanisms
47 20-Aug-01 RMS Added bad block option in attach
48 17-Jul-01 RMS Fixed warning from VC++ 6.0
49 26-Apr-01 RMS Added device enable/disable support
50 25-Mar-01 RMS Fixed block fill calculation
51 15-Feb-01 RMS Corrected bootstrap string
52 12-Nov-97 RMS Added bad block table command
53 25-Nov-96 RMS Default units to autosize
54 29-Jun-96 RMS Added unit disable support
56 The RL11 is a four drive cartridge disk subsystem. An RL01 drive
57 consists of 256 cylinders, each with 2 surfaces containing 40 sectors
58 of 256 bytes. An RL02 drive has 512 cylinders. The RLV12 is a
59 controller variant which supports 22b direct addressing.
61 The most complicated part of the RL11 controller is the way it does
62 seeks. Seeking is relative to the current disk address; this requires
63 keeping accurate track of the current cylinder. The RL11 will not
64 switch heads or cross cylinders during transfers.
66 The RL11 functions in three environments:
68 - PDP-11 Q22 systems - the I/O map is one for one, so it's safe to
69 go through the I/O map
70 - PDP-11 Unibus 22b systems - the RL11 behaves as an 18b Unibus
71 peripheral and must go through the I/O map
72 - VAX Q22 systems - the RL11 must go through the I/O map
75 #if defined (VM_PDP10) /* PDP10 version */
76 #error "RL11 is not supported on the PDP-10!"
78 #elif defined (VM_VAX) /* VAX version */
81 #else /* PDP-11 version */
82 #include "pdp11_defs.h"
83 extern uint32 cpu_opt
;
88 #define RL_NUMWD 128 /* words/sector */
89 #define RL_NUMSC 40 /* sectors/surface */
90 #define RL_NUMSF 2 /* surfaces/cylinder */
91 #define RL_NUMCY 256 /* cylinders/drive */
92 #define RL_NUMDR 4 /* drives/controller */
93 #define RL_MAXFR (1 << 16) /* max transfer */
94 #define RL01_SIZE (RL_NUMCY * RL_NUMSF * RL_NUMSC * RL_NUMWD) /* words/drive */
95 #define RL02_SIZE (RL01_SIZE * 2) /* words/drive */
97 /* Flags in the unit flags word */
99 #define UNIT_V_WLK (UNIT_V_UF + 0) /* hwre write lock */
100 #define UNIT_V_RL02 (UNIT_V_UF + 1) /* RL01 vs RL02 */
101 #define UNIT_V_AUTO (UNIT_V_UF + 2) /* autosize enable */
102 #define UNIT_V_DUMMY (UNIT_V_UF + 3) /* dummy flag */
103 #define UNIT_DUMMY (1 << UNIT_V_DUMMY)
104 #define UNIT_WLK (1u << UNIT_V_WLK)
105 #define UNIT_RL02 (1u << UNIT_V_RL02)
106 #define UNIT_AUTO (1u << UNIT_V_AUTO)
107 #define UNIT_WPRT (UNIT_WLK | UNIT_RO) /* write protected */
109 /* Parameters in the unit descriptor */
111 #define TRK u3 /* current track */
112 #define STAT u4 /* status */
114 /* RLDS, NI = not implemented, * = kept in STAT, ^ = kept in TRK */
116 #define RLDS_LOAD 0 /* no cartridge */
117 #define RLDS_LOCK 5 /* lock on */
118 #define RLDS_BHO 0000010 /* brushes home NI */
119 #define RLDS_HDO 0000020 /* heads out NI */
120 #define RLDS_CVO 0000040 /* cover open NI */
121 #define RLDS_HD 0000100 /* head select ^ */
122 #define RLDS_RL02 0000200 /* RL02 */
123 #define RLDS_DSE 0000400 /* drv sel err NI */
124 #define RLDS_VCK 0001000 /* vol check * */
125 #define RLDS_WGE 0002000 /* wr gate err * */
126 #define RLDS_SPE 0004000 /* spin err * */
127 #define RLDS_STO 0010000 /* seek time out NI */
128 #define RLDS_WLK 0020000 /* wr locked */
129 #define RLDS_HCE 0040000 /* hd curr err NI */
130 #define RLDS_WDE 0100000 /* wr data err NI */
131 #define RLDS_ATT (RLDS_HDO+RLDS_BHO+RLDS_LOCK) /* att status */
132 #define RLDS_UNATT (RLDS_CVO+RLDS_LOAD) /* unatt status */
133 #define RLDS_ERR (RLDS_WDE+RLDS_HCE+RLDS_STO+RLDS_SPE+RLDS_WGE+ \
134 RLDS_VCK+RLDS_DSE) /* errors bits */
138 #define RLCS_DRDY 0000001 /* drive ready */
139 #define RLCS_M_FUNC 0000007 /* function */
147 #define RLCS_RNOHDR 7
148 #define RLCS_V_FUNC 1
149 #define RLCS_M_MEX 03 /* memory extension */
151 #define RLCS_MEX (RLCS_M_MEX << RLCS_V_MEX)
152 #define RLCS_M_DRIVE 03
153 #define RLCS_V_DRIVE 8
154 #define RLCS_INCMP 0002000 /* incomplete */
155 #define RLCS_CRC 0004000 /* CRC error */
156 #define RLCS_HDE 0010000 /* header error */
157 #define RLCS_NXM 0020000 /* non-exist memory */
158 #define RLCS_DRE 0040000 /* drive error */
159 #define RLCS_ERR 0100000 /* error summary */
160 #define RLCS_ALLERR (RLCS_ERR+RLCS_DRE+RLCS_NXM+RLCS_HDE+RLCS_CRC+RLCS_INCMP)
161 #define RLCS_RW 0001776 /* read/write */
162 #define GET_FUNC(x) (((x) >> RLCS_V_FUNC) & RLCS_M_FUNC)
163 #define GET_DRIVE(x) (((x) >> RLCS_V_DRIVE) & RLCS_M_DRIVE)
167 #define RLDA_SK_DIR 0000004 /* direction */
168 #define RLDA_GS_CLR 0000010 /* clear errors */
169 #define RLDA_SK_HD 0000020 /* head select */
171 #define RLDA_V_SECT 0 /* sector */
172 #define RLDA_M_SECT 077
173 #define RLDA_V_TRACK 6 /* track */
174 #define RLDA_M_TRACK 01777
175 #define RLDA_HD0 (0 << RLDA_V_TRACK)
176 #define RLDA_HD1 (1u << RLDA_V_TRACK)
177 #define RLDA_V_CYL 7 /* cylinder */
178 #define RLDA_M_CYL 0777
179 #define RLDA_TRACK (RLDA_M_TRACK << RLDA_V_TRACK)
180 #define RLDA_CYL (RLDA_M_CYL << RLDA_V_CYL)
181 #define GET_SECT(x) (((x) >> RLDA_V_SECT) & RLDA_M_SECT)
182 #define GET_CYL(x) (((x) >> RLDA_V_CYL) & RLDA_M_CYL)
183 #define GET_TRACK(x) (((x) >> RLDA_V_TRACK) & RLDA_M_TRACK)
184 #define GET_DA(x) ((GET_TRACK (x) * RL_NUMSC) + GET_SECT (x))
188 #define RLBA_IMP 0177776 /* implemented */
192 #define RLBAE_IMP 0000077 /* implemented */
194 extern int32 int_req
[IPL_HLVL
];
196 uint16
*rlxb
= NULL
; /* xfer buffer */
197 int32 rlcs
= 0; /* control/status */
198 int32 rlba
= 0; /* memory address */
199 int32 rlbae
= 0; /* mem addr extension */
200 int32 rlda
= 0; /* disk addr */
201 int32 rlmp
= 0, rlmp1
= 0, rlmp2
= 0; /* mp register queue */
202 int32 rl_swait
= 10; /* seek wait */
203 int32 rl_rwait
= 10; /* rotate wait */
204 int32 rl_stopioe
= 1; /* stop on error */
207 t_stat
rl_rd (int32
*data
, int32 PA
, int32 access
);
208 t_stat
rl_wr (int32 data
, int32 PA
, int32 access
);
209 t_stat
rl_svc (UNIT
*uptr
);
210 t_stat
rl_reset (DEVICE
*dptr
);
211 void rl_set_done (int32 error
);
212 t_stat
rl_boot (int32 unitno
, DEVICE
*dptr
);
213 t_stat
rl_attach (UNIT
*uptr
, char *cptr
);
214 t_stat
rl_set_size (UNIT
*uptr
, int32 val
, char *cptr
, void *desc
);
215 t_stat
rl_set_bad (UNIT
*uptr
, int32 val
, char *cptr
, void *desc
);
216 extern t_stat
pdp11_bad_block (UNIT
*uptr
, int32 sec
, int32 wds
);
218 /* RL11 data structures
220 rl_dev RL device descriptor
222 rl_reg RL register list
223 rl_mod RL modifier list
227 IOBA_RL
, IOLN_RL
, &rl_rd
, &rl_wr
,
228 1, IVCL (RL
), VEC_RL
, { NULL
} };
231 { UDATA (&rl_svc
, UNIT_FIX
+UNIT_ATTABLE
+UNIT_DISABLE
+
232 UNIT_ROABLE
+UNIT_AUTO
, RL01_SIZE
) },
233 { UDATA (&rl_svc
, UNIT_FIX
+UNIT_ATTABLE
+UNIT_DISABLE
+
234 UNIT_ROABLE
+UNIT_AUTO
, RL01_SIZE
) },
235 { UDATA (&rl_svc
, UNIT_FIX
+UNIT_ATTABLE
+UNIT_DISABLE
+
236 UNIT_ROABLE
+UNIT_AUTO
, RL01_SIZE
) },
237 { UDATA (&rl_svc
, UNIT_FIX
+UNIT_ATTABLE
+UNIT_DISABLE
+
238 UNIT_ROABLE
+UNIT_AUTO
, RL01_SIZE
) }
242 { GRDATA (RLCS
, rlcs
, DEV_RDX
, 16, 0) },
243 { GRDATA (RLDA
, rlda
, DEV_RDX
, 16, 0) },
244 { GRDATA (RLBA
, rlba
, DEV_RDX
, 16, 0) },
245 { GRDATA (RLBAE
, rlbae
, DEV_RDX
, 6, 0) },
246 { GRDATA (RLMP
, rlmp
, DEV_RDX
, 16, 0) },
247 { GRDATA (RLMP1
, rlmp1
, DEV_RDX
, 16, 0) },
248 { GRDATA (RLMP2
, rlmp2
, DEV_RDX
, 16, 0) },
249 { FLDATA (INT
, IREQ (RL
), INT_V_RL
) },
250 { FLDATA (ERR
, rlcs
, CSR_V_ERR
) },
251 { FLDATA (DONE
, rlcs
, CSR_V_DONE
) },
252 { FLDATA (IE
, rlcs
, CSR_V_IE
) },
253 { DRDATA (STIME
, rl_swait
, 24), PV_LEFT
},
254 { DRDATA (RTIME
, rl_rwait
, 24), PV_LEFT
},
255 { URDATA (CAPAC
, rl_unit
[0].capac
, 10, T_ADDR_W
, 0,
256 RL_NUMDR
, PV_LEFT
+ REG_HRO
) },
257 { FLDATA (STOP_IOE
, rl_stopioe
, 0) },
258 { GRDATA (DEVADDR
, rl_dib
.ba
, DEV_RDX
, 32, 0), REG_HRO
},
259 { GRDATA (DEVVEC
, rl_dib
.vec
, DEV_RDX
, 16, 0), REG_HRO
},
264 { UNIT_WLK
, 0, "write enabled", "WRITEENABLED", NULL
},
265 { UNIT_WLK
, UNIT_WLK
, "write locked", "LOCKED", NULL
},
266 { UNIT_DUMMY
, 0, NULL
, "BADBLOCK", &rl_set_bad
},
267 { (UNIT_RL02
+UNIT_ATT
), UNIT_ATT
, "RL01", NULL
, NULL
},
268 { (UNIT_RL02
+UNIT_ATT
), (UNIT_RL02
+UNIT_ATT
), "RL02", NULL
, NULL
},
269 { (UNIT_AUTO
+UNIT_RL02
+UNIT_ATT
), 0, "RL01", NULL
, NULL
},
270 { (UNIT_AUTO
+UNIT_RL02
+UNIT_ATT
), UNIT_RL02
, "RL02", NULL
, NULL
},
271 { (UNIT_AUTO
+UNIT_ATT
), UNIT_AUTO
, "autosize", NULL
, NULL
},
272 { UNIT_AUTO
, UNIT_AUTO
, NULL
, "AUTOSIZE", NULL
},
273 { (UNIT_AUTO
+UNIT_RL02
), 0, NULL
, "RL01", &rl_set_size
},
274 { (UNIT_AUTO
+UNIT_RL02
), UNIT_RL02
, NULL
, "RL02", &rl_set_size
},
275 { MTAB_XTD
|MTAB_VDV
, 010, "ADDRESS", "ADDRESS",
276 &set_addr
, &show_addr
, NULL
},
277 { MTAB_XTD
|MTAB_VDV
, 0, "VECTOR", "VECTOR",
278 &set_vec
, &show_vec
, NULL
},
283 "RL", rl_unit
, rl_reg
, rl_mod
,
284 RL_NUMDR
, DEV_RDX
, 24, 1, DEV_RDX
, 16,
285 NULL
, NULL
, &rl_reset
,
286 &rl_boot
, &rl_attach
, NULL
,
287 &rl_dib
, DEV_DISABLE
| DEV_UBUS
| DEV_QBUS
290 /* I/O dispatch routines, I/O addresses 17774400 - 17774407
292 17774400 RLCS read/write
293 17774402 RLBA read/write
294 17774404 RLDA read/write
295 17774406 RLMP read/write
296 17774410 RLBAE read/write
299 t_stat
rl_rd (int32
*data
, int32 PA
, int32 access
)
303 switch ((PA
>> 1) & 07) { /* decode PA<2:1> */
306 rlcs
= (rlcs
& ~RLCS_MEX
) | ((rlbae
& RLCS_M_MEX
) << RLCS_V_MEX
);
307 if (rlcs
& RLCS_ALLERR
) rlcs
= rlcs
| RLCS_ERR
;
308 uptr
= rl_dev
.units
+ GET_DRIVE (rlcs
);
309 if (sim_is_active (uptr
)) rlcs
= rlcs
& ~RLCS_DRDY
;
310 else rlcs
= rlcs
| RLCS_DRDY
; /* see if ready */
315 *data
= rlba
& RLBA_IMP
;
324 rlmp
= rlmp1
; /* ripple data */
329 if (UNIBUS
) return SCPE_NXM
; /* not in RL11 */
330 *data
= rlbae
& RLBAE_IMP
;
337 t_stat
rl_wr (int32 data
, int32 PA
, int32 access
)
339 int32 curr
, offs
, newc
, maxc
;
342 switch ((PA
>> 1) & 07) { /* decode PA<2:1> */
345 rlcs
= (rlcs
& ~RLCS_MEX
) | ((rlbae
& RLCS_M_MEX
) << RLCS_V_MEX
);
346 if (rlcs
& RLCS_ALLERR
) rlcs
= rlcs
| RLCS_ERR
;
347 uptr
= rl_dev
.units
+ GET_DRIVE (data
); /* get new drive */
348 if (sim_is_active (uptr
)) rlcs
= rlcs
& ~RLCS_DRDY
;
349 else rlcs
= rlcs
| RLCS_DRDY
; /* see if ready */
351 if (access
== WRITEB
) data
= (PA
& 1)?
352 (rlcs
& 0377) | (data
<< 8): (rlcs
& ~0377) | data
;
353 rlcs
= (rlcs
& ~RLCS_RW
) | (data
& RLCS_RW
);
354 rlbae
= (rlbae
& ~RLCS_M_MEX
) | ((rlcs
>> RLCS_V_MEX
) & RLCS_M_MEX
);
355 if (data
& CSR_DONE
) { /* ready set? */
356 if ((data
& CSR_IE
) == 0) CLR_INT (RL
);
357 else if ((rlcs
& (CSR_DONE
+ CSR_IE
)) == CSR_DONE
)
362 CLR_INT (RL
); /* clear interrupt */
363 rlcs
= rlcs
& ~RLCS_ALLERR
; /* clear errors */
364 switch (GET_FUNC (rlcs
)) { /* case on RLCS<3:1> */
365 case RLCS_NOP
: /* nop */
368 case RLCS_SEEK
: /* seek */
369 curr
= GET_CYL (uptr
->TRK
); /* current cylinder */
370 offs
= GET_CYL (rlda
); /* offset */
371 if (rlda
& RLDA_SK_DIR
) { /* in or out? */
372 newc
= curr
+ offs
; /* out */
373 maxc
= (uptr
->flags
& UNIT_RL02
)?
374 RL_NUMCY
* 2: RL_NUMCY
;
375 if (newc
>= maxc
) newc
= maxc
- 1;
378 newc
= curr
- offs
; /* in */
379 if (newc
< 0) newc
= 0;
381 uptr
->TRK
= (newc
<< RLDA_V_CYL
) | /* put on track */
382 ((rlda
& RLDA_SK_HD
)? RLDA_HD1
: RLDA_HD0
);
383 sim_activate (uptr
, rl_swait
* abs (newc
- curr
));
385 default: /* data transfer */
386 sim_activate (uptr
, rl_swait
); /* activate unit */
388 } /* end switch func */
389 break; /* end case RLCS */
392 if (access
== WRITEB
) data
= (PA
& 1)?
393 (rlba
& 0377) | (data
<< 8): (rlba
& ~0377) | data
;
394 rlba
= data
& RLBA_IMP
;
398 if (access
== WRITEB
) data
= (PA
& 1)?
399 (rlda
& 0377) | (data
<< 8): (rlda
& ~0377) | data
;
404 if (access
== WRITEB
) data
= (PA
& 1)?
405 (rlmp
& 0377) | (data
<< 8): (rlmp
& ~0377) | data
;
406 rlmp
= rlmp1
= rlmp2
= data
;
410 if (UNIBUS
) return SCPE_NXM
; /* not in RL11 */
411 if (PA
& 1) return SCPE_OK
;
412 rlbae
= data
& RLBAE_IMP
;
413 rlcs
= (rlcs
& ~RLCS_MEX
) | ((rlbae
& RLCS_M_MEX
) << RLCS_V_MEX
);
420 /* Service unit timeout
422 If seek in progress, complete seek command
423 Else complete data transfer command
425 The unit control block contains the function and cylinder for
429 t_stat
rl_svc (UNIT
*uptr
)
431 int32 err
, wc
, maxwc
, t
;
432 int32 i
, func
, da
, awc
;
436 func
= GET_FUNC (rlcs
); /* get function */
437 if (func
== RLCS_GSTA
) { /* get status */
438 if (rlda
& RLDA_GS_CLR
) uptr
->STAT
= uptr
->STAT
& ~RLDS_ERR
;
439 rlmp
= uptr
->STAT
| (uptr
->TRK
& RLDS_HD
) |
440 ((uptr
->flags
& UNIT_ATT
)? RLDS_ATT
: RLDS_UNATT
);
441 if (uptr
->flags
& UNIT_RL02
) rlmp
= rlmp
| RLDS_RL02
;
442 if (uptr
->flags
& UNIT_WPRT
) rlmp
= rlmp
| RLDS_WLK
;
443 rlmp2
= rlmp1
= rlmp
;
444 rl_set_done (0); /* done */
448 if ((uptr
->flags
& UNIT_ATT
) == 0) { /* attached? */
449 rlcs
= rlcs
& ~RLCS_DRDY
; /* clear drive ready */
450 uptr
->STAT
= uptr
->STAT
| RLDS_SPE
; /* spin error */
451 rl_set_done (RLCS_ERR
| RLCS_INCMP
); /* flag error */
452 return IORETURN (rl_stopioe
, SCPE_UNATT
);
455 if ((func
== RLCS_WRITE
) && (uptr
->flags
& UNIT_WPRT
)) {
456 uptr
->STAT
= uptr
->STAT
| RLDS_WGE
; /* write and locked */
457 rl_set_done (RLCS_ERR
| RLCS_DRE
);
461 if (func
== RLCS_SEEK
) { /* seek? */
462 rl_set_done (0); /* done */
466 if (func
== RLCS_RHDR
) { /* read header? */
467 rlmp
= (uptr
->TRK
& RLDA_TRACK
) | GET_SECT (rlda
);
469 rl_set_done (0); /* done */
473 if (((func
!= RLCS_RNOHDR
) && ((uptr
->TRK
& RLDA_CYL
) != (rlda
& RLDA_CYL
)))
474 || (GET_SECT (rlda
) >= RL_NUMSC
)) { /* bad cyl or sector? */
475 rl_set_done (RLCS_ERR
| RLCS_HDE
| RLCS_INCMP
); /* wrong cylinder? */
479 ma
= (rlbae
<< 16) | rlba
; /* get mem addr */
480 da
= GET_DA (rlda
) * RL_NUMWD
; /* get disk addr */
481 wc
= 0200000 - rlmp
; /* get true wc */
483 maxwc
= (RL_NUMSC
- GET_SECT (rlda
)) * RL_NUMWD
; /* max transfer */
484 if (wc
> maxwc
) wc
= maxwc
; /* track overrun? */
485 err
= fseek (uptr
->fileref
, da
* sizeof (int16
), SEEK_SET
);
487 if ((func
>= RLCS_READ
) && (err
== 0)) { /* read (no hdr)? */
488 i
= fxread (rlxb
, sizeof (int16
), wc
, uptr
->fileref
);
489 err
= ferror (uptr
->fileref
);
490 for ( ; i
< wc
; i
++) rlxb
[i
] = 0; /* fill buffer */
491 if (t
= Map_WriteW (ma
, wc
<< 1, rlxb
)) { /* store buffer */
492 rlcs
= rlcs
| RLCS_ERR
| RLCS_NXM
; /* nxm */
493 wc
= wc
- t
; /* adjust wc */
497 if ((func
== RLCS_WRITE
) && (err
== 0)) { /* write? */
498 if (t
= Map_ReadW (ma
, wc
<< 1, rlxb
)) { /* fetch buffer */
499 rlcs
= rlcs
| RLCS_ERR
| RLCS_NXM
; /* nxm */
500 wc
= wc
- t
; /* adj xfer lnt */
502 if (wc
) { /* any xfer? */
503 awc
= (wc
+ (RL_NUMWD
- 1)) & ~(RL_NUMWD
- 1); /* clr to */
504 for (i
= wc
; i
< awc
; i
++) rlxb
[i
] = 0; /* end of blk */
505 fxwrite (rlxb
, sizeof (int16
), awc
, uptr
->fileref
);
506 err
= ferror (uptr
->fileref
);
510 if ((func
== RLCS_WCHK
) && (err
== 0)) { /* write check? */
511 i
= fxread (rlxb
, sizeof (int16
), wc
, uptr
->fileref
);
512 err
= ferror (uptr
->fileref
);
513 for ( ; i
< wc
; i
++) rlxb
[i
] = 0; /* fill buffer */
514 awc
= wc
; /* save wc */
515 for (wc
= 0; (err
== 0) && (wc
< awc
); wc
++) { /* loop thru buf */
516 if (Map_ReadW (ma
+ (wc
<< 1), 2, &comp
)) { /* mem wd */
517 rlcs
= rlcs
| RLCS_ERR
| RLCS_NXM
; /* nxm */
520 if (comp
!= rlxb
[wc
]) /* check to buf */
521 rlcs
= rlcs
| RLCS_ERR
| RLCS_CRC
;
525 rlmp
= (rlmp
+ wc
) & 0177777; /* final word count */
526 if (rlmp
!= 0) rlcs
= rlcs
| RLCS_ERR
| RLCS_INCMP
; /* completed? */
527 ma
= ma
+ (wc
<< 1); /* final byte addr */
528 rlbae
= (ma
>> 16) & RLBAE_IMP
; /* upper 6b */
529 rlba
= ma
& RLBA_IMP
; /* lower 16b */
530 rlcs
= (rlcs
& ~RLCS_MEX
) | ((rlbae
& RLCS_M_MEX
) << RLCS_V_MEX
);
531 rlda
= rlda
+ ((wc
+ (RL_NUMWD
- 1)) / RL_NUMWD
);
534 if (err
!= 0) { /* error? */
535 perror ("RL I/O error");
536 clearerr (uptr
->fileref
);
542 /* Set done and possibly errors */
544 void rl_set_done (int32 status
)
546 rlcs
= rlcs
| status
| CSR_DONE
; /* set done */
547 if (rlcs
& CSR_IE
) SET_INT (RL
);
554 Note that the RL11 does NOT recalibrate its drives on RESET
557 t_stat
rl_reset (DEVICE
*dptr
)
563 rlda
= rlba
= rlbae
= rlmp
= rlmp1
= rlmp2
= 0;
565 for (i
= 0; i
< RL_NUMDR
; i
++) {
566 uptr
= rl_dev
.units
+ i
;
570 if (rlxb
== NULL
) rlxb
= (uint16
*) calloc (RL_MAXFR
, sizeof (uint16
));
571 if (rlxb
== NULL
) return SCPE_MEM
;
577 t_stat
rl_attach (UNIT
*uptr
, char *cptr
)
582 uptr
->capac
= (uptr
->flags
& UNIT_RL02
)? RL02_SIZE
: RL01_SIZE
;
583 r
= attach_unit (uptr
, cptr
); /* attach unit */
584 if (r
!= SCPE_OK
) return r
; /* error? */
585 uptr
->TRK
= 0; /* cylinder 0 */
586 uptr
->STAT
= RLDS_VCK
; /* new volume */
587 if ((p
= sim_fsize (uptr
->fileref
)) == 0) { /* new disk image? */
588 if (uptr
->flags
& UNIT_RO
) return SCPE_OK
; /* if ro, done */
589 return pdp11_bad_block (uptr
, RL_NUMSC
, RL_NUMWD
);
591 if ((uptr
->flags
& UNIT_AUTO
) == 0) return SCPE_OK
; /* autosize? */
592 if (p
> (RL01_SIZE
* sizeof (int16
))) {
593 uptr
->flags
= uptr
->flags
| UNIT_RL02
;
594 uptr
->capac
= RL02_SIZE
;
597 uptr
->flags
= uptr
->flags
& ~UNIT_RL02
;
598 uptr
->capac
= RL01_SIZE
;
603 /* Set size routine */
605 t_stat
rl_set_size (UNIT
*uptr
, int32 val
, char *cptr
, void *desc
)
607 if (uptr
->flags
& UNIT_ATT
) return SCPE_ALATT
;
608 uptr
->capac
= (val
& UNIT_RL02
)? RL02_SIZE
: RL01_SIZE
;
612 /* Set bad block routine */
614 t_stat
rl_set_bad (UNIT
*uptr
, int32 val
, char *cptr
, void *desc
)
616 return pdp11_bad_block (uptr
, RL_NUMSC
, RL_NUMWD
);
619 /* Device bootstrap */
621 #if defined (VM_PDP11)
623 #define BOOT_START 02000 /* start */
624 #define BOOT_ENTRY (BOOT_START + 002) /* entry */
625 #define BOOT_UNIT (BOOT_START + 010) /* unit number */
626 #define BOOT_CSR (BOOT_START + 020) /* CSR */
627 #define BOOT_LEN (sizeof (boot_rom) / sizeof (int16))
629 static const uint16 boot_rom
[] = {
631 0012706, BOOT_START
, /* MOV #boot_start, SP */
632 0012700, 0000000, /* MOV #unit, R0 */
633 0010003, /* MOV R0, R3 */
634 0000303, /* SWAB R3 */
635 0012701, 0174400, /* MOV #RLCS, R1 ; csr */
636 0012761, 0000013, 0000004, /* MOV #13, 4(R1) ; clr err */
637 0052703, 0000004, /* BIS #4, R3 ; unit+gstat */
638 0010311, /* MOV R3, (R1) ; issue cmd */
639 0105711, /* TSTB (R1) ; wait */
640 0100376, /* BPL .-2 */
641 0105003, /* CLRB R3 */
642 0052703, 0000010, /* BIS #10, R3 ; unit+rdhdr */
643 0010311, /* MOV R3, (R1) ; issue cmd */
644 0105711, /* TSTB (R1) ; wait */
645 0100376, /* BPL .-2 */
646 0016102, 0000006, /* MOV 6(R1), R2 ; get hdr */
647 0042702, 0000077, /* BIC #77, R2 ; clr sector */
648 0005202, /* INC R2 ; magic bit */
649 0010261, 0000004, /* MOV R2, 4(R1) ; seek to 0 */
650 0105003, /* CLRB R3 */
651 0052703, 0000006, /* BIS #6, R3 ; unit+seek */
652 0010311, /* MOV R3, (R1) ; issue cmd */
653 0105711, /* TSTB (R1) ; wait */
654 0100376, /* BPL .-2 */
655 0005061, 0000002, /* CLR 2(R1) ; clr ba */
656 0005061, 0000004, /* CLR 4(R1) ; clr da */
657 0012761, 0177000, 0000006, /* MOV #-512., 6(R1) ; set wc */
658 0105003, /* CLRB R3 */
659 0052703, 0000014, /* BIS #14, R3 ; unit+read */
660 0010311, /* MOV R3, (R1) ; issue cmd */
661 0105711, /* TSTB (R1) ; wait */
662 0100376, /* BPL .-2 */
663 0042711, 0000377, /* BIC #377, (R1) */
664 0005002, /* CLR R2 */
665 0005003, /* CLR R3 */
666 0012704, BOOT_START
+020, /* MOV #START+20, R4 */
667 0005005, /* CLR R5 */
671 t_stat
rl_boot (int32 unitno
, DEVICE
*dptr
)
675 extern int32 saved_PC
;
677 for (i
= 0; i
< BOOT_LEN
; i
++) M
[(BOOT_START
>> 1) + i
] = boot_rom
[i
];
678 M
[BOOT_UNIT
>> 1] = unitno
& RLCS_M_DRIVE
;
679 M
[BOOT_CSR
>> 1] = rl_dib
.ba
& DMASK
;
680 saved_PC
= BOOT_ENTRY
;
686 t_stat
rl_boot (int32 unitno
, DEVICE
*dptr
)