1 /* pdp8_clk.c: PDP-8 real-time clock simulator
3 Copyright (c) 1993-2007, Robert M Supnik
5 Permission is hereby granted, free of charge, to any person obtaining a
6 copy of this software and associated documentation files (the "Software"),
7 to deal in the Software without restriction, including without limitation
8 the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 and/or sell copies of the Software, and to permit persons to whom the
10 Software is furnished to do so, subject to the following conditions:
12 The above copyright notice and this permission notice shall be included in
13 all copies or substantial portions of the Software.
15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22 Except as contained in this notice, the name of Robert M Supnik shall not be
23 used in advertising or otherwise to promote the sale, use or other dealings
24 in this Software without prior written authorization from Robert M Supnik.
28 18-Jun-07 RMS Added UNIT_IDLE flag
29 01-Mar-03 RMS Aded SET/SHOW CLK FREQ support
30 04-Oct-02 RMS Added DIB, device number support
31 30-Dec-01 RMS Removed for generalized timers
32 05-Sep-01 RMS Added terminal multiplexor support
33 17-Jul-01 RMS Moved function prototype
34 05-Mar-01 RMS Added clock calibration support
36 Note: includes the IOT's for both the PDP-8/E and PDP-8/A clocks
39 #include "pdp8_defs.h"
41 extern int32 int_req
, int_enable
, dev_done
, stop_inst
;
43 int32 clk_tps
= 60; /* ticks/second */
44 int32 tmxr_poll
= 16000; /* term mux poll */
46 int32
clk (int32 IR
, int32 AC
);
47 t_stat
clk_svc (UNIT
*uptr
);
48 t_stat
clk_reset (DEVICE
*dptr
);
49 t_stat
clk_set_freq (UNIT
*uptr
, int32 val
, char *cptr
, void *desc
);
50 t_stat
clk_show_freq (FILE *st
, UNIT
*uptr
, int32 val
, void *desc
);
52 /* CLK data structures
54 clk_dev CLK device descriptor
55 clk_unit CLK unit descriptor
56 clk_reg CLK register list
59 DIB clk_dib
= { DEV_CLK
, 1, { &clk
} };
61 UNIT clk_unit
= { UDATA (&clk_svc
, UNIT_IDLE
, 0), 16000 };
64 { FLDATA (DONE
, dev_done
, INT_V_CLK
) },
65 { FLDATA (ENABLE
, int_enable
, INT_V_CLK
) },
66 { FLDATA (INT
, int_req
, INT_V_CLK
) },
67 { DRDATA (TIME
, clk_unit
.wait
, 24), REG_NZ
+ PV_LEFT
},
68 { DRDATA (TPS
, clk_tps
, 8), PV_LEFT
+ REG_HRO
},
73 { MTAB_XTD
|MTAB_VDV
, 50, NULL
, "50HZ",
74 &clk_set_freq
, NULL
, NULL
},
75 { MTAB_XTD
|MTAB_VDV
, 60, NULL
, "60HZ",
76 &clk_set_freq
, NULL
, NULL
},
77 { MTAB_XTD
|MTAB_VDV
, 0, "FREQUENCY", NULL
,
78 NULL
, &clk_show_freq
, NULL
},
79 { MTAB_XTD
|MTAB_VDV
, 0, "DEVNO", NULL
, NULL
, &show_dev
},
84 "CLK", &clk_unit
, clk_reg
, clk_mod
,
86 NULL
, NULL
, &clk_reset
,
93 IOT's 6131-6133 are the PDP-8/E clock
94 IOT's 6135-6137 are the PDP-8/A clock
97 int32
clk (int32 IR
, int32 AC
)
99 switch (IR
& 07) { /* decode IR<9:11> */
102 int_enable
= int_enable
| INT_CLK
; /* enable clk ints */
103 int_req
= INT_UPDATE
; /* update interrupts */
107 int_enable
= int_enable
& ~INT_CLK
; /* disable clk ints */
108 int_req
= int_req
& ~INT_CLK
; /* update interrupts */
112 if (dev_done
& INT_CLK
) { /* flag set? */
113 dev_done
= dev_done
& ~INT_CLK
; /* clear flag */
114 int_req
= int_req
& ~INT_CLK
; /* clear int req */
120 if (AC
& 1) int_enable
= int_enable
| INT_CLK
; /* test AC<11> */
121 else int_enable
= int_enable
& ~INT_CLK
;
122 int_req
= INT_UPDATE
; /* update interrupts */
126 dev_done
= dev_done
& ~INT_CLK
; /* clear flag */
127 int_req
= int_req
& ~INT_CLK
; /* clear int req */
131 return (dev_done
& INT_CLK
)? IOT_SKP
+ AC
: AC
;
134 return (stop_inst
<< IOT_V_REASON
) + AC
;
140 t_stat
clk_svc (UNIT
*uptr
)
144 dev_done
= dev_done
| INT_CLK
; /* set done */
145 int_req
= INT_UPDATE
; /* update interrupts */
146 t
= sim_rtcn_calb (clk_tps
, TMR_CLK
); /* calibrate clock */
147 sim_activate (&clk_unit
, t
); /* reactivate unit */
148 tmxr_poll
= t
; /* set mux poll */
154 t_stat
clk_reset (DEVICE
*dptr
)
158 dev_done
= dev_done
& ~INT_CLK
; /* clear done, int */
159 int_req
= int_req
& ~INT_CLK
;
160 int_enable
= int_enable
& ~INT_CLK
; /* clear enable */
161 t
= sim_rtcn_init (clk_unit
.wait
, TMR_CLK
);
162 sim_activate_abs (&clk_unit
, t
); /* activate unit */
169 t_stat
clk_set_freq (UNIT
*uptr
, int32 val
, char *cptr
, void *desc
)
171 if (cptr
) return SCPE_ARG
;
172 if ((val
!= 50) && (val
!= 60)) return SCPE_IERR
;
179 t_stat
clk_show_freq (FILE *st
, UNIT
*uptr
, int32 val
, void *desc
)
181 fprintf (st
, (clk_tps
== 50)? "50Hz": "60Hz");