1 / -+-+-+-+-+
\ e H P X O U T. R A
\ e -+-+-+-+-+
3 / F 4 SUBROUTINE XOUT (LEVEL)
5 / THE INTEGER LEVEL IS LOADED INTO THE VC8E DISPLAY X REGISTER
7 / THE VC8-E ENABLE REGISTER IS CLEARED AND THEN WE LOAD THE X REGISTER.
8 / THE DONE FLAG IS NOT TESTED.
10 / HARDWARE REQUIRED: LAB8/E, HARD/SOFT FPP12, VC8-E
12 / VER 0.0 12-MAR-81 HA
16 / ENTRY XOUT / CALL XOUT (LEVEL); INTEGER LEVEL
17 ENTRY YOUT / CALL YOUT (LEVEL); INTEGER LEVEL
18 JA #XOUT / HERE TO REDUCE # OF EXT. REFS FOR THE LOADER
20 DILE= 6056 / LOAD DISPLAY ENABLE REGISTER
21 DILX= 6053 / LOAD VC8E X REGISTER
22 DILY= 6054 / LOAD VC8E Y REGISTER
23 CDI= 6203 / COMBINED CDF++CIF
26 TWO, 0;2 / USED TO FETCH THE ARGUMENT LIST
27 CXOUT, DILX; NOP / LOADS X REGISTER
28 CYOUT, DILY; NOP / LOADS Y REGISTER (MUST BE TWO WORDS FOR FPP 2 WORD STORE)
29 BASE 0 / STAY ON CALLERS BASE PAGE
31 #XOUT, STARTD / CALL XOUT (LEVEL)
32 FLDA CXOUT / INSERT CORRECT COMMAND INTO THE 8 CODE ROUTINE
34 YOUT, STARTD / CALL YOUT (LEVEL)
36 STORIT, FSTA COMAND / INSERT CODE ONTO 8 MODE SCTION
38 FLDA 10*3 / SAVE THE RETURN ADR.
40 FLDA 0 / LOAD THE ADR. OF THE ARGUMENT LIST
41 FADD TWO / INCREMENT TO GET THE FIRST ARGUMENT
42 FSTA 3 / TEMP FOR INDIRECT REF.
43 FLDA% 3 / GET THE ADR. OF THE ARGUMENT
46 FLDA% 3 / AND LOAD THE ARGUMENT
47 SETX XR / WE CONVERT THE FRACTIONAL INTO INTEGER
48 ATX X1 / FOR THE PDP CODE
49 TRAP4 OUT8 / PDP8/E DOES THE WORK
54 / F 4 SUBROUTINE CHSL (SELECT BIT)
56 / THE INTEGER SELECT BIT IS LOADED INTO THE VC8E DISPLAY CHANNEL SELECT BIT OF THE ENABLE REGISTER
58 / THE VC8-E INTERRUPT BIT IS ALWAYS CLEARED.
60 / HARDWARE REQUIRED: LAB8/E, HARD/SOFT FPP12, VC8-E
62 / VER 0.0 12-MAY-81 HA
65 ENTRY CHSL / CALL CHSL (LEVEL); INTEGER LEVEL
68 BASE 0 / STAY ON CALLERS BASE PAGE
69 CHSL, STARTD / CALL CHSL (LEVEL)
70 FLDA 10*3 / SAVE THE RETURN ADR.
72 FLDA 0 / LOAD THE ADR. OF THE ARGUMENT LIST
73 FADD TWO / INCREMENT TO GET THE FIRST ARGUMENT
74 FSTA 3 / TEMP FOR INDIRECT REF.
75 FLDA% 3 / GET THE ADR. OF THE ARGUMENT
78 FLDA% 3 / AND LOAD THE ARGUMENT
79 SETX XR / WE CONVERT THE FRACTIONAL INTO INTEGER
80 ATX X1 / FOR THE PDP CODE
81 TRAP4 CHSL8 / PDP8/E DOES THE WORK
86 XR, ORG .+2 / X REGISTER SET
88 X1= X0+1 / THE LEVEL LOADED INTO THE X REGISTER
92 CLA / CLEAR THE VC8-E ENABLE REGISTER
94 TAD X1 / AND THEN WE LOAD
95 COMAND, DILX; NOP / THE X REGISTER (NOP MUST BE HERE FOR FPP 2 WORD STORE)
97 JMP% OUT8 / SEE YOU LATER
102 CLA / CLEAR THE VC8-E ENABLE REGISTER
103 TAD X1 / AND LOAD THE CHANNEL SELECT BIT
104 RAL / SHIFT INTO THE CORRECT POSITION
107 JMP% CHSL8 / SEE YOU LATER