1 EXTERN #DISP /SYSTEM PAGE 0,NEEDED TO
2 /PUT CLOCK STATUS ON PG0
3 /(CSTAT) FOR USE BY GEN
4 /USER CLOCK SERVICE ROUTS
5 EXTERN #T812 /RTS CPTYP
6 EXTERN ONQI /INTERRUPT QUEUER
13 CSTAT=157 /IDOCLK PUTS CLSA BITS
18 JSA SETUP /HERE TO READ A STRIG
20 TRAP4 DOSYNC /FCNWD (XR) HOLDS STRIG
23 FSTA% FTMP1 /GIVE ANS TO CALLER
25 FTMP0, F 0.0 /BASE PAGE
27 RPTR, 27;ADDR RTBL /PTR TO RATE TBL, ALSO
28 /USED TO FLT OVRCNT (NOTE
29 /THAT THE EXPONENT=27)
30 MINRAT, F .02 /MIN ALLOWABLE RATE
38 RTBL, F 16.0 /CONSTANT USED TO CHK FOR
40 /THIS CONST MUST BE NE 0
42 F4096, F 4096.0 /USED TO GET OVRFLO COUNT
43 F 100000.0 /FASTEST RATE IN HERTZ
44 F 10000.0 /NEXT FASTEST RATE
47 F 1.0 /USED BY TIME FOR EXT CLK
50 SETUP, 0;0 /HERE TO INIT ALL FPP SUBS
52 FLDA 30 /PICK UP RTN TO CALLER
54 FLDA 0 /GET PTR TO CALLERS ARGS
55 SETX FCNWD /CLOCK XR AND BASE
60 FSTA FTMP0 /PTR TO 1ST ARG
62 FSTA FTMP1 /PTR TO 2ND ARG
63 FLDA #T812 /TELLS PDP8,PDP12
64 ATX CPTYP /0=8=DK8ES,1=12=KW12A
67 ATX FCNWD /ALWAYS IN FCNWD
70 CLOCK, JSA SETUP /HERE FOR CLOCK START
72 FSUB RTBL /FCNWD IS IN FAC,IF GE 16
73 JGE ITSEXT /(RTBL=16.0) THEN USER IS
74 /REQUESTING AN EXTERNAL
75 /CLOCK I.E. B8 OF FCNWD
77 FLDA% FTMP1 /=REQUESTED RATE IN HERTZ
78 FSUB MINRAT /.LE. MINUMUM RATE
79 JLE GOTR-2 /MEANS STOP CLOCK.
81 FSUB MAXRAT /CHK FOR TOO FAST
83 LDX -4,OVRFLO /THERE ARE 4 BASIC RATES
84 LDX 1,RATE /=INDEX INTO RTBL; UPON
88 /2-5=PROGRAMMABLE RATES
89 LOP0, FLDA% RPTR,RATE+
90 /GET NEXT SLOWEST RATE
91 FDIV% FTMP1 /=REQUESTED RATE IN HZ.
93 FSUB F4096 /MUST BE MODULO 12 BITS.
96 LDX 0,RATE /RATE IS TOO SLOW, STOP
98 GOTR, FADD F4096 /RESTORE
100 ATX OVRFLO /OVER FLOW COUNT
101 TRAP4 SETCLK /GO START CLOCK
102 JA GOBAK /RTN TO CALLER
103 ITSEXT, LDX 6,RATE /=RATE FOR EXT CLK
104 FLDA% FTMP1 /REQUESTED RATE IS
105 /INTERPRETED AS OVRFLO
106 JA GOTR+1 /WHEN RATE IS EXTERNAL
107 \f/MAGIC TABLE USED BY SETCLK TO SET CLOCK ENABLE
108 /BITS. EVEN NUMBERED ENTRIES ARE FOR THE DK8ES;
109 /ODD NUMBERED ONES ARE FOR THE KW12A.
111 CLKTBL, 0675 /"STANDARD" DK BITS
119 40 /DK ADC ON OVR BIT
120 400 /KW ADC ON OVR BIT
122 /IF NOT NEXT PAGE DO ORG
123 IFNEG .-200 < ORG .-SYNC&7600+200+SYNC >
124 \fSETCLK, 0 /TRAP HERE TO START CLK
125 /THIS ROUT HANDLES BOTH
127 CLLR /STOP KW AND SET MODE 0;
129 CLEN /CLR KW12 ENABLE OR
132 TAD P7540 /TOGGLE KW MODE 0 TO 1 TO
133 CLLR /CLR CLK COUNTER, OR SET
134 /DK ENABLE BITS, RATE FOR
135 CLA CMA /BOTH NOW=7=STOP.
136 CLZE /CLR ALL DK ENABLE BITS,
137 CLSA /CLR STATUS OF BOTH, ALL
139 TAD FCNTBL+1 /SET PTR TO CLKTBL FOR
140 /SETTING OF ENABLE REGS.
141 TAD CPTYP /=0 IF PDP8 =1 IF PDP12
142 DCA FCNPTR /TBL ENTRIES ALTERNATE
143 /FOR 8 AND 12. CPTYP SETS
144 /PTR TO 1ST 8 OR 1ST 12
146 TAD IDOCLK /(AC=JMP AROUND). THE
147 /FOLLOWING IS ONCE ONLY
148 /CODE. THESE LOCS ARE
149 /SUBSEQUENTLY USED AS
152 /THE TAG "ISVBIT" MUST BE
153 /IN FRONT OF THE STRIG
154 /FLAGS (STFLG) TO COVER
156 /STRIG 0 IN A FORT CALL
158 ISVBIT, TAD CPTYP /(AC=0,1) MAKE THE INST
159 /RAR CLL (FOR DK) OR THE
160 /INST RTR CLL FOR IDOCLK;
161 STFLG, RAL CLL /BECAUSE STATUS BITS FOR
162 TAD RARCLL /STRIGS DIFFER ON DK,KW.
163 DCA LOP2+1 /SEE SUB IDOCLK.
164 /THE ABOVE 3 LOCS ARE
165 /SCHMITT TRIGGER FLAGS.
166 /THE ORDER IS S1,S2,S3
167 /FOR PDP8 AND S3,S2,S1
169 /REASON FOR REVERSING
170 /THE ORDER IS BECAUSE
171 /ENGINEERS NEVER CONSULT
172 /PROGRAMMERS WHEN THEY
174 /HARDWARE (CHK THE STATUS
175 /BITS FOR DK AND KW).
176 JMS% KONQI+1 /PUT CLOCK ON THE
177 ITMP0, CLSK /INTERRUPT QUE
179 CLENAB, ADDR IDOCLK /THIS LOC WILL HOLD THE
180 /ENABLE BITS FOR DK,KW
181 AROUND, TAD RATE /(AC=0,2,3,4,5,6) RATE IS
183 RTR CLL /START TO POSITION RATE
184 RAR /BITS. B3-B5 FOR DK
186 TAD CPTYP /(THIS IS TRICKY) NEED
187 RAR /CPTYP IN LNK BECAUSE
188 /POSITION OF RATE BITS
190 TAD% FCNPTR /AC="STANDARD"
191 /ENABLE BITS FOR DK,KW.
192 SZL /IF ITS A KW THE RATE AND
193 /AND STND BITS ARE ALREADY
194 /POSITIONED AS FOLLOWS:
196 /B0-B3 AND B5 WILL GO TO
197 /KW CONTROL. B4,B5 WILL
198 /GO TO ENABLE. B3 IS ADC
199 /ON OVRFLO AND MAY BE SET
200 /BELOW. B5 ON CONTROL IS
201 /MODE 1. B4 AND B5 ON
202 /ENABLE ARE BUFF PRESET TO
203 /CLOCK COUNTER AND INTRUPT
204 /ON OVRFLO RESPECTIVELY.
205 JMP NOBIT-1 /ITS KW GO PUT IN CLENAB.
206 RTR /ITS DK; POSITION RATE TO
207 RAR /B3-B5. NOTE THAT THE LNK
208 /(CPTYP=0) IS BEING USED.
209 CMA /NOTE ALSO THAT THE RATE
210 /AND STND BITS ARE THE 1S
211 /COMP. OF WHAT THEY SHOULD
215 /PRESET TO CLK CNTR ON
216 /OVERFLO. LOOK AT THE RATE
217 /BITS IN THE HANDBOOK FOR
219 /FOR DK IS 100HZ, 100KHZ
220 /RESPECTIVELY. R2,R5 FOR
224 /THE FINAL VALUE OF THE
225 /STND DK ENABLE BITS (1ST
226 /ENTRY IN CLKTBL) IS LEFT
227 /AS AN EXERCISE FOR THE
229 JMP NOBIT-1 /GO PUT IN CLENAB
230 LOP1, RAR CLL /ROT 1 FCN BIT INTO LNK.
232 /IGNORED HERE. B8=ADC ON
233 /OVRFLO, B9-B11 ARE STRIG3
234 /-STRIG1 RESP. BX=1=ENABLE
236 DCA FCNWD /PUT IT BACK (FCNWD IS
240 TAD% FCNPTR /GET BITS FROM THE MAGIC
242 DCA CLENAB /UPDATE ENABLE WORD.
243 NOBIT, ISZ FCNPTR /ADV TO NEXT
244 ISZ FCNPTR /TBL ENTRY.
245 TAD FCNWD /WHEN FCNWD GOES TO 0
246 AND P17 /WE ARE ALL DONE.
247 /THE "AND" IS DONE TO
248 /PROTECT AGAINST A BAD
249 /ARG FROM THE FORT CALL.
250 /IN A FRIENDLY ENIVORN,
252 /NEVER TRUST A FORTRAN
254 P7540, SMA SZA /SMA IS SUPERFLOUS TO
256 /CREATES A NICE CONST.
258 DCA STFLG /CLR THE SCHMITT
259 DCA STFLG+1 /TRIGGER FLAGS.
261 TAD OVRFLO /SET BUFF PRESET
262 CIA /(FPP SET THIS ARG)
265 TAD CLENAB /THIS IS FOR KW ONLY.
266 AND P377 /AC=3XX. 3= OR BUFF PRE
267 /INTO CLK CNTR AND ENAB
270 CLEN /SET KW ENABLE OR
272 DCA OVRCNT+1 /CLR NUM OF CLK OVRFLOS
273 DCA OVRCNT /SINCE TIME 0.
274 TAD CPTYP /NEED TYPE IN ORDER TO
275 RARCLL, RAR CLL /ISOLATE CONTROL
278 AND P7540 /YES, B0-B2 IS RATE,
279 /B3 IS ADC, B5 IS BUFF
281 /OVRFLO, B6 IS MOX NIX.
282 /IF DK ALL BITS MAY HAVE
284 CLLR /START THE CLOCK
287 JMP% SETCLK /RTN TO RTS
288 \fDOSYNC, 0 /HERE TO DISPOSITION A
290 TAD CPTYP /DK AND KW FLAGS ARE IN
291 RAR CLL /REVERSE ORDER. IF DK
292 /ARG IS OK; IF KW THEN
293 /MUST SET 1=3, 2=2, 3=1
296 TAD FCNWD /=REQUESTED STRIG=1,2,3
300 AND P3 /IE 1 GOES TO -1 GOES
301 /TO 3 ETC. "AND" ALSO
302 /INSURES RANGE IS 0-3.
303 /IF ARG IS 0 RESULT IS
305 TAD KSTFLG+1 /GET PTR TO FLAG
307 TAD% SETCLK /FLAG=0 IF TRIG HAS NOT
308 /TRIPPED SINCE THE LAST
310 /OTHERWISE IE RTN 0=FALSE
311 DCA FCNWD /,1=TRUE (FPP WILL PICK
313 DCA% SETCLK /CLR FLAG ANYWAY
315 JMP% DOSYNC /RTN TO RTS
316 \fIDOCLK, JMP AROUND /HERE ON CLOCK INTERRUPT
317 /(JMP AROUND IS A ONCE
319 TAD KSTFLG+1 /SET PTR TO STRIG FLAGS.
321 CLSA /GET CLOCK BITS.
322 DCAZ CSTAT /SAVE THEM FOR SOME
323 TADZ CSTAT /BODY ELSE.
325 ISZ OVRCNT+1 /YES BUMP LO ORD CNTR
327 ISZ OVRCNT /BUMP HI ORD
328 JMP DOTRIG /(HI ORD ISZ SKP IS
330 LOP2, ISZ ITMP0 /ADV STRIG FLAG PTR.
331 RAR CLL /(OR RTR CLL IF KW)
332 /IE PUT STRIG BIT IN LNK.
334 /INTERROGATION IS S1,S2,S3
335 /IF KW THE ORDER IS S3,
336 /S2,S1. THE STATUS BITS
337 /FOR DK ARE ADJACENT IE
338 / B9(S3),B10(S2),B11(S1)
339 /FOR KW ITS EVERY OTHER,
340 /B6(S1),B8(S2),B10(S3).
341 DCA ISVBIT /SAVE WHATS LEFT.
342 RAL /COPY LNK INTO FLAG IF=1
343 SZA /IE DONT CLR FLAG WHEN
346 DOTRIG, AND P377 /THE "AND" INSURES THAT
348 /CLRED SO THAT ISVBIT
352 /CLR OVRFLO BIT FOR DK,KW
353 /AND CLR PRE-EVENT BIT
357 TAD #CLINT /CALL USER EXTENDED
358 SZA CLA /CLOCK ROUT ?
360 JMP% IDOCLK /RTN TO IHANDL
376 ENTRY TIME /FIGURE WHAT TIME IT IS
378 FLDA RPTR /=27;X;X IS USED TO FLOAT
380 FLDA# OVRCNT /NUM OF CLK OVRFLOS SINCE
383 FMUL TOVR /=NUM OF BASIC TICKS PER
385 /FAC=NUM OF TICKS SINCE
387 FDIV% RPTR,RATE /DIV BY BASIC RATE IN HZ
388 /OR 1 IF EXTERNAL CLK.
389 FSTA% FTMP0 /GIVE ANS TO CALLER, ALSO
392 /CALL. ANS=ELAPSED TIME IN
393 /SECONDS SINCE TIME 0 OR
394 /NUM OF EXTERNAL UNIT