trennfix/sw: Single timer version

[eisenbahn.git] / trennfix / sw / hardware.h

diff --git a/trennfix/sw/hardware.h b/trennfix/sw/hardware.h
new file mode 100644 (file)
index 0000000..edcd7ff
--- /dev/null
+++ b/trennfix/sw/hardware.h
@@ -0,0 +1,68 @@
+#ifndef __HARDWARE_H
+#define __HARDWARE_H
+
+
+#include "pin_magic.h"
+
+#define PIN_LED   _PIN(PORTB, PORTB2)
+#define PIN_SENSE _PIN(PORTB, PORTB4)
+#define PIN_DRIVE _PIN(PORTB, PORTB3)
+#define PIN_BTN   _PIN(PORTB, PB1)
+
+#define MM_SENSE (!PINVAL(PIN_SENSE))
+#define BTN_PRESSED (!PINVAL(PIN_BTN))
+
+#define START_TIMER0 ({TCNT0 = 0; TCCR0B = 2;})
+#define START_TIMER1 ({TCNT1 = 1; TCCR1 = 7; GTCCR |= 2;})
+#define STOP_TIMER1 ({TCCR1 = 0; TCNT1 = 1;})
+
+
+static inline void setup_hw(void)
+{
+       /* Turn off the 1/8 clock prescaler - now running at 16MHz*/
+       CLKPR = (1 << CLKPCE);
+       CLKPR = 0;
+
+       INPUT_PIN(PIN_SENSE);
+       INPUT_PIN(PIN_BTN);
+       OUTPUT_PIN(PIN_DRIVE);
+       OUTPUT_PIN(PIN_LED);
+       setpin(PIN_BTN, 1);   /* Need pullup              */
+       
+       GIMSK |= _BV(PCIE);     /* Enable pin change interrupt for sense port */
+       PCMSK |= _BV(PCINT4);    /* PB4, Rail sense input */
+
+       /* Change interrupt for button */
+       PCMSK |= _BV(PCINT1);    /* PB1 */
+
+       /* Setup timer 0, used for mm_switch */
+        TCCR0A = 0; /* Normal mode */
+       TCCR0B = 0; /* Timer off */
+       TIMSK |= _BV(OCIE0A);   /* Get a match interrupt */
+       
+       /* We need 13 + 45,5 us delay, That's 464 clocks @8MHz*/
+       //OCR0A = 91; /* Prescaler 8 is used */
+
+       /* Timer 1 for timeout */
+       /* We set it to 1024us by prescaler 64 and running full 256 */
+       // TCCR1 = 7;
+       //      TIMSK |= _BV(TOIE1); /* Overflow interrupt */
+}
+
+/* deprecated */
+#define START_TIMER0 ({TCNT0 = 0; TCCR0B = 2;})
+#define START_TIMER1 ({TCNT1 = 1; TCCR1 = 7; GTCCR |= 2;})
+#define STOP_TIMER0 (TCCR0B = 0)
+#define STOP_TIMER1 ({TCCR1 = 0; TCNT1 = 1;})
+
+#define TSTART_CLK_TO_SAMPLE_FAST ({TCNT0 = 0; GTCCR |= 1; OCR0A = 110; TCCR0B = 2;})
+#define TSTART_CLK_TO_SAMPLE_SLOW ({TCNT0 = 0; GTCCR |= 1; OCR0A = 220; TCCR0B = 2;})
+
+//#define TSTART_CLK_TO_SAMPLE_FAST ({TCNT0 = 0; GTCCR |= 1; OCR0A = 91; TCCR0B = 2;})
+//#define TSTART_CLK_TO_SAMPLE_SLOW ({TCNT0 = 0; GTCCR |= 1; OCR0A = 182; TCCR0B = 2;})
+
+#define TSTOP ({TCCR0B = 0;})
+
+
+
+#endif