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1 | /* pdp11_defs.h: PDP-11 simulator definitions\r |
2 | \r | |
3 | Copyright (c) 1993-2008, Robert M Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | The author gratefully acknowledges the help of Max Burnet, Megan Gentry,\r | |
27 | and John Wilson in resolving questions about the PDP-11\r | |
28 | \r | |
29 | 16-May-08 RMS Added KE11A, DC11 support\r | |
30 | 02-Feb-08 RMS Fixed DMA memory address limit test (found by John Dundas)\r | |
31 | 25-Jan-08 RMS Added RC11, KG11A support (from John Dundas)\r | |
32 | 16-Dec-06 RMS Added TA11 support\r | |
33 | 29-Oct-06 RMS Added clock coscheduling\r | |
34 | 06-Jul-06 RMS Added multiple KL11/DL11 support\r | |
35 | 26-Jun-06 RMS Added RF11 support\r | |
36 | 24-May-06 RMS Added 11/44 DR support (from CIS diagnostic)\r | |
37 | 17-May-06 RMS Added CR11/CD11 support (from John Dundas)\r | |
38 | 30-Sep-04 RMS Added Massbus support\r | |
39 | Removed Map_Addr prototype\r | |
40 | Removed map argument from Unibus routines\r | |
41 | Added framework for model selection\r | |
42 | 28-May-04 RMS Added DHQ support\r | |
43 | 25-Jan-04 RMS Removed local debug logging support\r | |
44 | 22-Dec-03 RMS Added second DEUNA/DELUA support\r | |
45 | 18-Oct-03 RMS Added DECtape off reel message\r | |
46 | 19-May-03 RMS Revised for new conditional compilation\r | |
47 | 05-Apr-03 RMS Fixed bug in MMR1 update (found by Tim Stark)\r | |
48 | 28-Feb-03 RMS Added TM logging support\r | |
49 | 19-Jan-03 RMS Changed mode definitions for Apple Dev Kit conflict\r | |
50 | 11-Nov-02 RMS Changed log definitions to be VAX compatible\r | |
51 | 10-Oct-02 RMS Added vector information to DIB\r | |
52 | Changed DZ11 vector to Unibus standard\r | |
53 | Added DEQNA/DELQA, DEUNA/DELUA support\r | |
54 | Added multiple RQDX3, autoconfigure support\r | |
55 | 12-Sep-02 RMS Added TMSCP, KW11P,and RX211 support\r | |
56 | 28-Apr-02 RMS Clarified PDF ACF mnemonics\r | |
57 | 22-Apr-02 RMS Added HTRAP, BPOK maint register flags, MT_MAXFR\r | |
58 | 06-Mar-02 RMS Changed system type to KDJ11A\r | |
59 | 20-Jan-02 RMS Added multiboard DZ11 support\r | |
60 | 09-Nov-01 RMS Added bus map support\r | |
61 | 07-Nov-01 RMS Added RQDX3 support\r | |
62 | 26-Oct-01 RMS Added symbolic definitions for IO page\r | |
63 | 19-Oct-01 RMS Added DZ definitions\r | |
64 | 15-Oct-01 RMS Added logging capabilities\r | |
65 | 07-Sep-01 RMS Revised for multilevel interrupts\r | |
66 | 01-Jun-01 RMS Added DZ11 support\r | |
67 | 23-Apr-01 RMS Added RK611 support\r | |
68 | 05-Apr-01 RMS Added TS11/TSV05 support\r | |
69 | 10-Feb-01 RMS Added DECtape support\r | |
70 | */\r | |
71 | \r | |
72 | #ifndef _PDP11_DEFS_H\r | |
73 | #define _PDP11_DEFS_H 0\r | |
74 | \r | |
75 | #ifndef VM_PDP11\r | |
76 | #define VM_PDP11 0\r | |
77 | #endif\r | |
78 | \r | |
79 | #include "sim_defs.h" /* simulator defns */\r | |
80 | #include <setjmp.h>\r | |
81 | \r | |
82 | /* Architectural constants */\r | |
83 | \r | |
84 | #define STKL_R 0340 /* stack limit */\r | |
85 | #define STKL_Y 0400\r | |
86 | #define VASIZE 0200000 /* 2**16 */\r | |
87 | #define VAMASK (VASIZE - 1) /* 2**16 - 1 */\r | |
88 | #define MEMSIZE64K 0200000 /* 2**16 */\r | |
89 | #define INIMEMSIZE 001000000 /* 2**18 */\r | |
90 | #define UNIMEMSIZE 001000000 /* 2**18 */\r | |
91 | #define UNIMASK (UNIMEMSIZE - 1) /* 2**18 - 1 */\r | |
92 | #define IOPAGEBASE 017760000 /* 2**22 - 2**13 */\r | |
93 | #define IOPAGESIZE 000020000 /* 2**13 */\r | |
94 | #define IOPAGEMASK (IOPAGESIZE - 1) /* 2**13 - 1 */\r | |
95 | #define MAXMEMSIZE 020000000 /* 2**22 */\r | |
96 | #define PAMASK (MAXMEMSIZE - 1) /* 2**22 - 1 */\r | |
97 | #define MEMSIZE (cpu_unit.capac)\r | |
98 | #define ADDR_IS_MEM(x) (((t_addr) (x)) < cpu_memsize) /* use only in sim! */\r | |
99 | #define DMASK 0177777\r | |
100 | \r | |
101 | /* CPU models */\r | |
102 | \r | |
103 | #define MOD_1103 0\r | |
104 | #define MOD_1104 1\r | |
105 | #define MOD_1105 2\r | |
106 | #define MOD_1120 3\r | |
107 | #define MOD_1123 4\r | |
108 | #define MOD_1123P 5\r | |
109 | #define MOD_1124 6\r | |
110 | #define MOD_1134 7\r | |
111 | #define MOD_1140 8\r | |
112 | #define MOD_1144 9\r | |
113 | #define MOD_1145 10\r | |
114 | #define MOD_1160 11\r | |
115 | #define MOD_1170 12\r | |
116 | #define MOD_1173 13\r | |
117 | #define MOD_1153 14\r | |
118 | #define MOD_1173B 15\r | |
119 | #define MOD_1183 16\r | |
120 | #define MOD_1184 17\r | |
121 | #define MOD_1193 18\r | |
122 | #define MOD_1194 19\r | |
123 | #define MOD_T 20\r | |
124 | \r | |
125 | #define CPUT_03 (1u << MOD_1103) /* LSI-11 */\r | |
126 | #define CPUT_04 (1u << MOD_1104) /* 11/04 */\r | |
127 | #define CPUT_05 (1u << MOD_1105) /* 11/05 */\r | |
128 | #define CPUT_20 (1u << MOD_1120) /* 11/20 */\r | |
129 | #define CPUT_23 (1u << MOD_1123) /* 11/23 */\r | |
130 | #define CPUT_23P (1u << MOD_1123P) /* 11/23+ */\r | |
131 | #define CPUT_24 (1u << MOD_1124) /* 11/24 */\r | |
132 | #define CPUT_34 (1u << MOD_1134) /* 11/34 */\r | |
133 | #define CPUT_40 (1u << MOD_1140) /* 11/40 */\r | |
134 | #define CPUT_44 (1u << MOD_1144) /* 11/44 */\r | |
135 | #define CPUT_45 (1u << MOD_1145) /* 11/45 */\r | |
136 | #define CPUT_60 (1u << MOD_1160) /* 11/60 */\r | |
137 | #define CPUT_70 (1u << MOD_1170) /* 11/70 */\r | |
138 | #define CPUT_73 (1u << MOD_1173) /* 11/73 */\r | |
139 | #define CPUT_53 (1u << MOD_1153) /* 11/53 */\r | |
140 | #define CPUT_73B (1u << MOD_1173B) /* 11/73B */\r | |
141 | #define CPUT_83 (1u << MOD_1183) /* 11/83 */\r | |
142 | #define CPUT_84 (1u << MOD_1184) /* 11/84 */\r | |
143 | #define CPUT_93 (1u << MOD_1193) /* 11/93 */\r | |
144 | #define CPUT_94 (1u << MOD_1194) /* 11/94 */\r | |
145 | #define CPUT_T (1u << MOD_T) /* T-11 */\r | |
146 | \r | |
147 | #define CPUT_F (CPUT_23|CPUT_23P|CPUT_24) /* all F11's */\r | |
148 | #define CPUT_J (CPUT_53|CPUT_73|CPUT_73B| \\r | |
149 | CPUT_83|CPUT_84|CPUT_93|CPUT_94)\r | |
150 | #define CPUT_JB (CPUT_73B|CPUT_83|CPUT_84) /* KDJ11B */\r | |
151 | #define CPUT_JE (CPUT_93|CPUT_94) /* KDJ11E */\r | |
152 | #define CPUT_JU (CPUT_84|CPUT_94) /* KTJ11B UBA */\r | |
153 | #define CPUT_ALL 0xFFFFFFFF\r | |
154 | \r | |
155 | /* CPU options */\r | |
156 | \r | |
157 | #define BUS_U (1u << 0) /* Unibus */\r | |
158 | #define BUS_Q (0) /* Qbus */\r | |
159 | #define OPT_EIS (1u << 1) /* EIS */\r | |
160 | #define OPT_FIS (1u << 2) /* FIS */\r | |
161 | #define OPT_FPP (1u << 3) /* FPP */\r | |
162 | #define OPT_CIS (1u << 4) /* CIS */\r | |
163 | #define OPT_MMU (1u << 5) /* MMU */\r | |
164 | #define OPT_RH11 (1u << 6) /* RH11 */\r | |
165 | #define OPT_PAR (1u << 7) /* parity */\r | |
166 | #define OPT_UBM (1u << 8) /* UBM */\r | |
167 | \r | |
168 | #define CPUT(x) ((cpu_type & (x)) != 0)\r | |
169 | #define CPUO(x) ((cpu_opt & (x)) != 0)\r | |
170 | #define UNIBUS (cpu_opt & BUS_U)\r | |
171 | \r | |
172 | /* Feature sets\r | |
173 | \r | |
174 | SDSD source addr, dest addr, source fetch, dest fetch\r | |
175 | SR switch register\r | |
176 | DR display register\r | |
177 | RTT RTT instruction\r | |
178 | SXS SXT, XOR, SOB instructions\r | |
179 | MARK MARK instruction\r | |
180 | SPL SPL instruction\r | |
181 | MXPY MTPI, MTPD, MFPI, MFPD instructions\r | |
182 | MXPS MTPS, MFPS instructions\r | |
183 | MFPT MFPT instruction\r | |
184 | CSM CSM instruction\r | |
185 | TSWLK TSTSET, WRLCK instructions\r | |
186 | PSW PSW register\r | |
187 | EXPT explicit PSW writes can alter T-bit\r | |
188 | IOSR general registers readable from programs in IO space\r | |
189 | 2REG dual register set\r | |
190 | MMR3 MMR3 register\r | |
191 | MMTR mem mgt traps\r | |
192 | STKLR STKLIM register\r | |
193 | STKLF fixed stack limit\r | |
194 | SID supervisor mode, I/D spaces\r | |
195 | ODD odd address trap\r | |
196 | HALT4 halt in kernel mode traps to 4\r | |
197 | JREG4 JMP/JSR R traps to 4\r | |
198 | STKA stop on stack abort\r | |
199 | LTCR LTC CSR\r | |
200 | LTCM LTC CSR<7>\r | |
201 | */\r | |
202 | \r | |
203 | #define IS_SDSD (CPUT_20|CPUT_F|CPUT_40|CPUT_60|CPUT_J|CPUT_T)\r | |
204 | #define HAS_SR (CPUT_04|CPUT_05|CPUT_20|CPUT_34|CPUT_40| \\r | |
205 | CPUT_44|CPUT_45|CPUT_60|CPUT_70)\r | |
206 | #define HAS_DR (CPUT_04|CPUT_05|CPUT_20|CPUT_24|CPUT_34| \\r | |
207 | CPUT_40|CPUT_44|CPUT_45|CPUT_60|CPUT_70)\r | |
208 | #define HAS_RTT (CPUT_03|CPUT_04|CPUT_F|CPUT_34|CPUT_40| \\r | |
209 | CPUT_44|CPUT_45|CPUT_60|CPUT_70|CPUT_J|CPUT_T)\r | |
210 | #define HAS_SXS (CPUT_03|CPUT_F|CPUT_34|CPUT_40|CPUT_44| \\r | |
211 | CPUT_45|CPUT_60|CPUT_70|CPUT_J|CPUT_T)\r | |
212 | #define HAS_MARK (CPUT_03|CPUT_F|CPUT_34|CPUT_40|CPUT_44| \\r | |
213 | CPUT_45|CPUT_60|CPUT_70|CPUT_J)\r | |
214 | #define HAS_SPL (CPUT_44|CPUT_45|CPUT_70|CPUT_J)\r | |
215 | #define HAS_MXPY (CPUT_F|CPUT_34|CPUT_40|CPUT_44|CPUT_45| \\r | |
216 | CPUT_60|CPUT_70|CPUT_J)\r | |
217 | #define HAS_MXPS (CPUT_03|CPUT_F|CPUT_34|CPUT_J|CPUT_T)\r | |
218 | #define HAS_MFPT (CPUT_F|CPUT_44|CPUT_J|CPUT_T)\r | |
219 | #define HAS_CSM (CPUT_44|CPUT_J)\r | |
220 | #define HAS_TSWLK (CPUT_J)\r | |
221 | #define HAS_PSW (CPUT_04|CPUT_05|CPUT_20|CPUT_F|CPUT_34|CPUT_40| \\r | |
222 | CPUT_44|CPUT_45|CPUT_60|CPUT_70|CPUT_J)\r | |
223 | #define HAS_EXPT (CPUT_04|CPUT_05|CPUT_20)\r | |
224 | #define HAS_IOSR (CPUT_04|CPUT_05)\r | |
225 | #define HAS_2REG (CPUT_45|CPUT_70|CPUT_J)\r | |
226 | #define HAS_MMR3 (CPUT_F|CPUT_44|CPUT_45|CPUT_70|CPUT_J)\r | |
227 | #define HAS_MMTR (CPUT_45|CPUT_70)\r | |
228 | #define HAS_STKLR (CPUT_45|CPUT_60|CPUT_70)\r | |
229 | #define HAS_STKLF (CPUT_04|CPUT_05|CPUT_20|CPUT_F|CPUT_34| \\r | |
230 | CPUT_40|CPUT_44|CPUT_J)\r | |
231 | #define HAS_SID (CPUT_44|CPUT_45|CPUT_70|CPUT_J)\r | |
232 | #define HAS_ODD (CPUT_04|CPUT_05|CPUT_20|CPUT_34|CPUT_40| \\r | |
233 | CPUT_44|CPUT_45|CPUT_60|CPUT_70|CPUT_J)\r | |
234 | #define HAS_HALT4 (CPUT_44|CPUT_45|CPUT_70|CPUT_J)\r | |
235 | #define HAS_JREG4 (CPUT_03|CPUT_04|CPUT_05|CPUT_20|CPUT_F| \\r | |
236 | CPUT_34|CPUT_40|CPUT_60|CPUT_T)\r | |
237 | #define STOP_STKA (CPUT_03|CPUT_04|CPUT_05|CPUT_20|CPUT_34|CPUT_44)\r | |
238 | #define HAS_LTCR (CPUT_04|CPUT_05|CPUT_20|CPUT_23P|CPUT_24| \\r | |
239 | CPUT_34|CPUT_40|CPUT_44|CPUT_45|CPUT_60| \\r | |
240 | CPUT_70|CPUT_J)\r | |
241 | #define HAS_LTCM (CPUT_04|CPUT_05|CPUT_20|CPUT_24|CPUT_34| \\r | |
242 | CPUT_40|CPUT_44|CPUT_45|CPUT_60|CPUT_70|CPUT_J)\r | |
243 | \r | |
244 | /* Protection modes */\r | |
245 | \r | |
246 | #define MD_KER 0\r | |
247 | #define MD_SUP 1\r | |
248 | #define MD_UND 2\r | |
249 | #define MD_USR 3\r | |
250 | \r | |
251 | /* I/O access modes */\r | |
252 | \r | |
253 | #define READ 0\r | |
254 | #define READC 1 /* read console */\r | |
255 | #define WRITE 2\r | |
256 | #define WRITEC 3 /* write console */\r | |
257 | #define WRITEB 4\r | |
258 | \r | |
259 | /* PSW */\r | |
260 | \r | |
261 | #define PSW_V_C 0 /* condition codes */\r | |
262 | #define PSW_V_V 1\r | |
263 | #define PSW_V_Z 2\r | |
264 | #define PSW_V_N 3\r | |
265 | #define PSW_V_TBIT 4 /* trace trap */\r | |
266 | #define PSW_V_IPL 5 /* int priority */\r | |
267 | #define PSW_V_FPD 8 /* first part done */\r | |
268 | #define PSW_V_RS 11 /* register set */\r | |
269 | #define PSW_V_PM 12 /* previous mode */\r | |
270 | #define PSW_V_CM 14 /* current mode */\r | |
271 | #define PSW_CC 017\r | |
272 | #define PSW_TBIT (1 << PSW_V_TBIT)\r | |
273 | #define PSW_PM (3 << PSW_V_PM)\r | |
274 | \r | |
275 | /* FPS */\r | |
276 | \r | |
277 | #define FPS_V_C 0 /* condition codes */\r | |
278 | #define FPS_V_V 1\r | |
279 | #define FPS_V_Z 2\r | |
280 | #define FPS_V_N 3\r | |
281 | #define FPS_V_T 5 /* truncate */\r | |
282 | #define FPS_V_L 6 /* long */\r | |
283 | #define FPS_V_D 7 /* double */\r | |
284 | #define FPS_V_IC 8 /* ic err int */\r | |
285 | #define FPS_V_IV 9 /* overflo err int */\r | |
286 | #define FPS_V_IU 10 /* underflo err int */\r | |
287 | #define FPS_V_IUV 11 /* undef var err int */\r | |
288 | #define FPS_V_ID 14 /* int disable */\r | |
289 | #define FPS_V_ER 15 /* error */\r | |
290 | \r | |
291 | /* PIRQ */\r | |
292 | \r | |
293 | #define PIRQ_PIR1 0001000\r | |
294 | #define PIRQ_PIR2 0002000\r | |
295 | #define PIRQ_PIR3 0004000\r | |
296 | #define PIRQ_PIR4 0010000\r | |
297 | #define PIRQ_PIR5 0020000\r | |
298 | #define PIRQ_PIR6 0040000\r | |
299 | #define PIRQ_PIR7 0100000\r | |
300 | #define PIRQ_IMP 0177356 /* implemented bits */\r | |
301 | #define PIRQ_RW 0177000 /* read/write bits */\r | |
302 | \r | |
303 | /* STKLIM */\r | |
304 | \r | |
305 | #define STKLIM_RW 0177400\r | |
306 | \r | |
307 | /* MMR0 */\r | |
308 | \r | |
309 | #define MMR0_MME 0000001 /* mem mgt enable */\r | |
310 | #define MMR0_V_PAGE 1 /* offset to pageno */\r | |
311 | #define MMR0_M_PAGE 077 /* mask for pageno */\r | |
312 | #define MMR0_PAGE (MMR0_M_PAGE << MMR0_V_PAGE)\r | |
313 | #define MMR0_IC 0000200 /* instr complete */\r | |
314 | #define MMR0_MAINT 0000400 /* maintenance */\r | |
315 | #define MMR0_TENB 0001000 /* trap enable */\r | |
316 | #define MMR0_TRAP 0010000 /* mem mgt trap */\r | |
317 | #define MMR0_RO 0020000 /* read only error */\r | |
318 | #define MMR0_PL 0040000 /* page lnt error */\r | |
319 | #define MMR0_NR 0100000 /* no access error */\r | |
320 | #define MMR0_FREEZE 0160000 /* if set, no update */\r | |
321 | #define MMR0_WR 0171401 /* writeable bits */\r | |
322 | \r | |
323 | /* MMR3 */\r | |
324 | \r | |
325 | #define MMR3_UDS 001 /* user dspace enbl */\r | |
326 | #define MMR3_SDS 002 /* super dspace enbl */\r | |
327 | #define MMR3_KDS 004 /* krnl dspace enbl */\r | |
328 | #define MMR3_CSM 010 /* CSM enable */\r | |
329 | #define MMR3_M22E 020 /* 22b mem mgt enbl */\r | |
330 | #define MMR3_BME 040 /* DMA bus map enbl */\r | |
331 | \r | |
332 | /* PAR */\r | |
333 | \r | |
334 | #define PAR_18B 0007777 /* 18b addressing */\r | |
335 | #define PAR_22B 0177777 /* 22b addressing */\r | |
336 | \r | |
337 | /* PDR */\r | |
338 | \r | |
339 | #define PDR_ACF 0000007 /* access control */\r | |
340 | #define PDR_ACS 0000006 /* 2b access control */\r | |
341 | #define PDR_ED 0000010 /* expansion dir */\r | |
342 | #define PDR_W 0000100 /* written flag */\r | |
343 | #define PDR_A 0000200 /* access flag */\r | |
344 | #define PDR_PLF 0077400 /* page lnt field */\r | |
345 | #define PDR_NOC 0100000 /* don't cache */\r | |
346 | \r | |
347 | #define PDR_PRD 0000003 /* page readable if 2 */\r | |
348 | \r | |
349 | /* Virtual address */\r | |
350 | \r | |
351 | #define VA_DF 0017777 /* displacement */\r | |
352 | #define VA_BN 0017700 /* block number */\r | |
353 | #define VA_V_APF 13 /* offset to APF */\r | |
354 | #define VA_V_DS 16 /* offset to space */\r | |
355 | #define VA_V_MODE 17 /* offset to mode */\r | |
356 | #define VA_DS (1u << VA_V_DS) /* data space flag */\r | |
357 | \r | |
358 | /* Unibus map (if present) */\r | |
359 | \r | |
360 | #define UBM_LNT_LW 32 /* size in LW */\r | |
361 | #define UBM_V_PN 13 /* page number */\r | |
362 | #define UBM_M_PN 037\r | |
363 | #define UBM_V_OFF 0 /* offset */\r | |
364 | #define UBM_M_OFF 017777\r | |
365 | #define UBM_PAGSIZE (UBM_M_OFF + 1) /* page size */\r | |
366 | #define UBM_GETPN(x) (((x) >> UBM_V_PN) & UBM_M_PN)\r | |
367 | #define UBM_GETOFF(x) ((x) & UBM_M_OFF)\r | |
368 | \r | |
369 | /* CPUERR */\r | |
370 | \r | |
371 | #define CPUE_RED 0004 /* red stack */\r | |
372 | #define CPUE_YEL 0010 /* yellow stack */\r | |
373 | #define CPUE_TMO 0020 /* IO page nxm */\r | |
374 | #define CPUE_NXM 0040 /* memory nxm */\r | |
375 | #define CPUE_ODD 0100 /* odd address */\r | |
376 | #define CPUE_HALT 0200 /* HALT not kernel */\r | |
377 | #define CPUE_IMP 0374 /* implemented bits */\r | |
378 | \r | |
379 | /* Floating point accumulators */\r | |
380 | \r | |
381 | typedef struct {\r | |
382 | uint32 l; /* low 32b */\r | |
383 | uint32 h; /* high 32b */\r | |
384 | } fpac_t;\r | |
385 | \r | |
386 | /* Device CSRs */\r | |
387 | \r | |
388 | #define CSR_V_GO 0 /* go */\r | |
389 | #define CSR_V_IE 6 /* interrupt enable */\r | |
390 | #define CSR_V_DONE 7 /* done */\r | |
391 | #define CSR_V_BUSY 11 /* busy */\r | |
392 | #define CSR_V_ERR 15 /* error */\r | |
393 | #define CSR_GO (1u << CSR_V_GO)\r | |
394 | #define CSR_IE (1u << CSR_V_IE)\r | |
395 | #define CSR_DONE (1u << CSR_V_DONE)\r | |
396 | #define CSR_BUSY (1u << CSR_V_BUSY)\r | |
397 | #define CSR_ERR (1u << CSR_V_ERR)\r | |
398 | \r | |
399 | /* Trap masks, descending priority order, following J-11\r | |
400 | An interrupt summary bit is kept with traps, to minimize overhead\r | |
401 | */\r | |
402 | \r | |
403 | #define TRAP_V_RED 0 /* red stk abort 4 */\r | |
404 | #define TRAP_V_ODD 1 /* odd address 4 */\r | |
405 | #define TRAP_V_MME 2 /* mem mgt 250 */\r | |
406 | #define TRAP_V_NXM 3 /* nx memory 4 */\r | |
407 | #define TRAP_V_PAR 4 /* parity err 114 */\r | |
408 | #define TRAP_V_PRV 5 /* priv inst 4 */\r | |
409 | #define TRAP_V_ILL 6 /* illegal inst 10 */\r | |
410 | #define TRAP_V_BPT 7 /* BPT 14 */\r | |
411 | #define TRAP_V_IOT 8 /* IOT 20 */\r | |
412 | #define TRAP_V_EMT 9 /* EMT 30 */\r | |
413 | #define TRAP_V_TRAP 10 /* TRAP 34 */\r | |
414 | #define TRAP_V_TRC 11 /* T bit 14 */\r | |
415 | #define TRAP_V_YEL 12 /* stack 4 */\r | |
416 | #define TRAP_V_PWRFL 13 /* power fail 24 */\r | |
417 | #define TRAP_V_FPE 14 /* fpe 244 */\r | |
418 | #define TRAP_V_MAX 15 /* intr = max trp # */\r | |
419 | #define TRAP_RED (1u << TRAP_V_RED)\r | |
420 | #define TRAP_ODD (1u << TRAP_V_ODD)\r | |
421 | #define TRAP_MME (1u << TRAP_V_MME)\r | |
422 | #define TRAP_NXM (1u << TRAP_V_NXM)\r | |
423 | #define TRAP_PAR (1u << TRAP_V_PAR)\r | |
424 | #define TRAP_PRV (1u << TRAP_V_PRV)\r | |
425 | #define TRAP_ILL (1u << TRAP_V_ILL)\r | |
426 | #define TRAP_BPT (1u << TRAP_V_BPT)\r | |
427 | #define TRAP_IOT (1u << TRAP_V_IOT)\r | |
428 | #define TRAP_EMT (1u << TRAP_V_EMT)\r | |
429 | #define TRAP_TRAP (1u << TRAP_V_TRAP)\r | |
430 | #define TRAP_TRC (1u << TRAP_V_TRC)\r | |
431 | #define TRAP_YEL (1u << TRAP_V_YEL)\r | |
432 | #define TRAP_PWRFL (1u << TRAP_V_PWRFL)\r | |
433 | #define TRAP_FPE (1u << TRAP_V_FPE)\r | |
434 | #define TRAP_INT (1u << TRAP_V_MAX)\r | |
435 | #define TRAP_ALL ((1u << TRAP_V_MAX) - 1) /* all traps */\r | |
436 | \r | |
437 | #define VEC_RED 0004 /* trap vectors */\r | |
438 | #define VEC_ODD 0004\r | |
439 | #define VEC_MME 0250\r | |
440 | #define VEC_NXM 0004\r | |
441 | #define VEC_PAR 0114\r | |
442 | #define VEC_PRV 0004\r | |
443 | #define VEC_ILL 0010\r | |
444 | #define VEC_BPT 0014\r | |
445 | #define VEC_IOT 0020\r | |
446 | #define VEC_EMT 0030\r | |
447 | #define VEC_TRAP 0034\r | |
448 | #define VEC_TRC 0014\r | |
449 | #define VEC_YEL 0004\r | |
450 | #define VEC_PWRFL 0024\r | |
451 | #define VEC_FPE 0244\r | |
452 | \r | |
453 | /* Simulator stop codes; codes 1:TRAP_V_MAX correspond to traps 0:TRAPMAX-1 */\r | |
454 | \r | |
455 | #define STOP_HALT (TRAP_V_MAX + 1) /* HALT instruction */\r | |
456 | #define STOP_IBKPT (TRAP_V_MAX + 2) /* instruction bkpt */\r | |
457 | #define STOP_WAIT (TRAP_V_MAX + 3) /* wait, no events */\r | |
458 | #define STOP_VECABORT (TRAP_V_MAX + 4) /* abort vector read */\r | |
459 | #define STOP_SPABORT (TRAP_V_MAX + 5) /* abort trap push */\r | |
460 | #define STOP_RQ (TRAP_V_MAX + 6) /* RQDX3 panic */\r | |
461 | #define STOP_SANITY (TRAP_V_MAX + 7) /* sanity timer exp */\r | |
462 | #define STOP_DTOFF (TRAP_V_MAX + 8) /* DECtape off reel */\r | |
463 | #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */\r | |
464 | \r | |
465 | /* Timers */\r | |
466 | \r | |
467 | #define TMR_CLK 0 /* line clock */\r | |
468 | #define TMR_PCLK 1 /* KW11P */\r | |
469 | \r | |
470 | /* IO parameters */\r | |
471 | \r | |
472 | #define DZ_MUXES 4 /* max # of DZ muxes */\r | |
473 | #define DZ_LINES 8 /* lines per DZ mux */\r | |
474 | #define VH_MUXES 4 /* max # of VH muxes */\r | |
475 | #define DLX_LINES 16 /* max # of KL11/DL11's */\r | |
476 | #define DCX_LINES 16 /* max # of DC11's */\r | |
477 | #define MT_MAXFR (1 << 16) /* magtape max rec */\r | |
478 | #define AUTO_LNT 34 /* autoconfig ranks */\r | |
479 | #define DIB_MAX 100 /* max DIBs */\r | |
480 | \r | |
481 | #define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */\r | |
482 | #define DEV_V_QBUS (DEV_V_UF + 1) /* Qbus */\r | |
483 | #define DEV_V_Q18 (DEV_V_UF + 2) /* Qbus with <= 256KB */\r | |
484 | #define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */\r | |
485 | #define DEV_V_MBUS (DEV_V_UF + 4) /* Massbus */\r | |
486 | #define DEV_V_FFUF (DEV_V_UF + 5) /* first free flag */\r | |
487 | #define DEV_UBUS (1u << DEV_V_UBUS)\r | |
488 | #define DEV_QBUS (1u << DEV_V_QBUS)\r | |
489 | #define DEV_Q18 (1u << DEV_V_Q18)\r | |
490 | #define DEV_FLTA (1u << DEV_V_FLTA)\r | |
491 | #define DEV_MBUS (1u << DEV_V_MBUS)\r | |
492 | \r | |
493 | #define DEV_RDX 8 /* default device radix */\r | |
494 | \r | |
495 | /* Device information block */\r | |
496 | \r | |
497 | #define VEC_DEVMAX 4 /* max device vec */\r | |
498 | \r | |
499 | struct pdp_dib {\r | |
500 | uint32 ba; /* base addr */\r | |
501 | uint32 lnt; /* length */\r | |
502 | t_stat (*rd)(int32 *dat, int32 ad, int32 md);\r | |
503 | t_stat (*wr)(int32 dat, int32 ad, int32 md);\r | |
504 | int32 vnum; /* vectors: number */\r | |
505 | int32 vloc; /* locator */\r | |
506 | int32 vec; /* value */\r | |
507 | int32 (*ack[VEC_DEVMAX])(void); /* ack routines */\r | |
508 | };\r | |
509 | \r | |
510 | typedef struct pdp_dib DIB;\r | |
511 | \r | |
512 | /* I/O page layout - XUB, RQB,RQC,RQD float based on number of DZ's */\r | |
513 | \r | |
514 | #define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */\r | |
515 | #define IOLN_DZ 010\r | |
516 | #define IOBA_XUB (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2)))\r | |
517 | #define IOLN_XUB 010\r | |
518 | #define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2)))\r | |
519 | #define IOLN_RQB 004\r | |
520 | #define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB)\r | |
521 | #define IOLN_RQC 004\r | |
522 | #define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC)\r | |
523 | #define IOLN_RQD 004\r | |
524 | #define IOBA_VH (IOPAGEBASE + 000440) /* DHQ11 */\r | |
525 | #define IOLN_VH 020\r | |
526 | #define IOBA_UBM (IOPAGEBASE + 010200) /* Unibus map */\r | |
527 | #define IOLN_UBM (UBM_LNT_LW * sizeof (int32))\r | |
528 | #define IOBA_KG (IOPAGEBASE + 010700) /* KG11-A */\r | |
529 | #define IOLN_KG 006\r | |
530 | #define IOBA_RQ (IOPAGEBASE + 012150) /* RQDX3 */\r | |
531 | #define IOLN_RQ 004\r | |
532 | #define IOBA_SUP (IOPAGEBASE + 012200) /* supervisor APR's */\r | |
533 | #define IOLN_SUP 0100\r | |
534 | #define IOBA_KIPDR (IOPAGEBASE + 012300) /* kernel APR's */\r | |
535 | #define IOLN_KIPDR 020\r | |
536 | #define IOBA_KDPDR (IOPAGEBASE + 012320)\r | |
537 | #define IOLN_KDPDR 020\r | |
538 | #define IOBA_KIPAR (IOPAGEBASE + 012340)\r | |
539 | #define IOLN_KIPAR 020\r | |
540 | #define IOBA_KDPAR (IOPAGEBASE + 012360)\r | |
541 | #define IOLN_KDPAR 020\r | |
542 | #define IOBA_TU (IOPAGEBASE + 012440) /* TU */\r | |
543 | #define IOLN_TU 040\r | |
544 | #define IOBA_MMR3 (IOPAGEBASE + 012516) /* MMR3 */\r | |
545 | #define IOLN_MMR3 002\r | |
546 | #define IOBA_TM (IOPAGEBASE + 012520) /* TM11 */\r | |
547 | #define IOLN_TM 014\r | |
548 | #define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */\r | |
549 | #define IOLN_TS 004\r | |
550 | #define IOBA_PCLK (IOPAGEBASE + 012540) /* KW11P */\r | |
551 | #define IOLN_PCLK 006\r | |
552 | #define IOBA_DC (IOPAGEBASE + 014000) /* DC11 */\r | |
553 | #define IOLN_DC (DCX_LINES * 010)\r | |
554 | #define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */\r | |
555 | #define IOLN_RL 012\r | |
556 | #define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */\r | |
557 | #define IOLN_XQ 020\r | |
558 | #define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */\r | |
559 | #define IOLN_XQB 020\r | |
560 | #define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */\r | |
561 | #define IOLN_TQ 004\r | |
562 | #define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */\r | |
563 | #define IOLN_XU 010\r | |
564 | #define IOBA_DL (IOPAGEBASE + 016500) /* extra KL11/DL11 */\r | |
565 | #define IOLN_DL (DLX_LINES * 010)\r | |
566 | #define IOBA_RP (IOPAGEBASE + 016700) /* RP/RM */\r | |
567 | #define IOLN_RP 054\r | |
568 | #define IOBA_CR (IOPAGEBASE + 017160) /* CD/CR/CM */\r | |
569 | #define IOLN_CR 010\r | |
570 | #define IOBA_RX (IOPAGEBASE + 017170) /* RX11 */\r | |
571 | #define IOLN_RX 004\r | |
572 | #define IOBA_RY (IOPAGEBASE + 017170) /* RY11 */\r | |
573 | #define IOLN_RY 004\r | |
574 | #define IOBA_KE (IOPAGEBASE + 017300) /* KE11-A */\r | |
575 | #define IOLN_KE 020\r | |
576 | #define IOBA_TC (IOPAGEBASE + 017340) /* TC11 */\r | |
577 | #define IOLN_TC 012\r | |
578 | #define IOBA_RK (IOPAGEBASE + 017400) /* RK11 */\r | |
579 | #define IOLN_RK 020\r | |
580 | #define IOBA_RC (IOPAGEBASE + 017440) /* RC11/RS64 */\r | |
581 | #define IOLN_RC 020\r | |
582 | #define IOBA_HK (IOPAGEBASE + 017440) /* RK611 */\r | |
583 | #define IOLN_HK 040\r | |
584 | #define IOBA_RF (IOPAGEBASE + 017460) /* RF11 */\r | |
585 | #define IOLN_RF 020\r | |
586 | #define IOBA_TA (IOPAGEBASE + 017500) /* TA11 */\r | |
587 | #define IOLN_TA 004\r | |
588 | #define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */\r | |
589 | #define IOLN_LPT 004\r | |
590 | #define IOBA_CTL (IOPAGEBASE + 017520) /* board ctrl */\r | |
591 | #define IOLN_CTL 010\r | |
592 | #define IOBA_CLK (IOPAGEBASE + 017546) /* KW11L */\r | |
593 | #define IOLN_CLK 002\r | |
594 | #define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */\r | |
595 | #define IOLN_PTR 004\r | |
596 | #define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */\r | |
597 | #define IOLN_PTP 004\r | |
598 | #define IOBA_TTI (IOPAGEBASE + 017560) /* DL11 rcv */\r | |
599 | #define IOLN_TTI 004\r | |
600 | #define IOBA_TTO (IOPAGEBASE + 017564) /* DL11 xmt */\r | |
601 | #define IOLN_TTO 004\r | |
602 | #define IOBA_SR (IOPAGEBASE + 017570) /* SR */\r | |
603 | #define IOLN_SR 002\r | |
604 | #define IOBA_MMR012 (IOPAGEBASE + 017572) /* MMR0-2 */\r | |
605 | #define IOLN_MMR012 006\r | |
606 | #define IOBA_UIPDR (IOPAGEBASE + 017600) /* user APR's */\r | |
607 | #define IOLN_UIPDR 020\r | |
608 | #define IOBA_UDPDR (IOPAGEBASE + 017620)\r | |
609 | #define IOLN_UDPDR 020\r | |
610 | #define IOBA_UIPAR (IOPAGEBASE + 017640)\r | |
611 | #define IOLN_UIPAR 020\r | |
612 | #define IOBA_UDPAR (IOPAGEBASE + 017660)\r | |
613 | #define IOLN_UDPAR 020\r | |
614 | #define IOBA_GPR (IOPAGEBASE + 017700) /* GPR's */\r | |
615 | #define IOLN_GPR 010\r | |
616 | #define IOBA_UCTL (IOPAGEBASE + 017730) /* UBA ctrl */\r | |
617 | #define IOLN_UCTL 010\r | |
618 | #define IOBA_CPU (IOPAGEBASE + 017740) /* CPU reg */\r | |
619 | #define IOLN_CPU 036\r | |
620 | #define IOBA_PSW (IOPAGEBASE + 017776) /* PSW */\r | |
621 | #define IOLN_PSW 002\r | |
622 | \r | |
623 | /* Interrupt assignments; within each level, priority is right to left */\r | |
624 | \r | |
625 | #define IPL_HLVL 8 /* # int levels */\r | |
626 | \r | |
627 | #define INT_V_PIR7 0 /* BR7 */\r | |
628 | \r | |
629 | #define INT_V_CLK 0 /* BR6 */\r | |
630 | #define INT_V_PCLK 1\r | |
631 | #define INT_V_DTA 2\r | |
632 | #define INT_V_TA 3\r | |
633 | #define INT_V_PIR6 4\r | |
634 | \r | |
635 | #define INT_V_RK 0 /* BR5 */\r | |
636 | #define INT_V_RL 1\r | |
637 | #define INT_V_RX 2\r | |
638 | #define INT_V_TM 3\r | |
639 | #define INT_V_RP 4\r | |
640 | #define INT_V_TS 5\r | |
641 | #define INT_V_HK 6\r | |
642 | #define INT_V_RQ 7\r | |
643 | #define INT_V_DZRX 8\r | |
644 | #define INT_V_DZTX 9\r | |
645 | #define INT_V_TQ 10\r | |
646 | #define INT_V_RY 11\r | |
647 | #define INT_V_XQ 12\r | |
648 | #define INT_V_XU 13\r | |
649 | #define INT_V_TU 14\r | |
650 | #define INT_V_RF 15\r | |
651 | #define INT_V_RC 16\r | |
652 | #define INT_V_PIR5 17\r | |
653 | \r | |
654 | #define INT_V_TTI 0 /* BR4 */\r | |
655 | #define INT_V_TTO 1\r | |
656 | #define INT_V_PTR 2\r | |
657 | #define INT_V_PTP 3\r | |
658 | #define INT_V_LPT 4\r | |
659 | #define INT_V_VHRX 5\r | |
660 | #define INT_V_VHTX 6 \r | |
661 | #define INT_V_CR 7\r | |
662 | #define INT_V_DLI 8\r | |
663 | #define INT_V_DLO 9\r | |
664 | #define INT_V_DCI 10\r | |
665 | #define INT_V_DCO 11\r | |
666 | #define INT_V_PIR4 12\r | |
667 | \r | |
668 | #define INT_V_PIR3 0 /* BR3 */\r | |
669 | #define INT_V_PIR2 0 /* BR2 */\r | |
670 | #define INT_V_PIR1 0 /* BR1 */\r | |
671 | \r | |
672 | #define INT_PIR7 (1u << INT_V_PIR7)\r | |
673 | #define INT_CLK (1u << INT_V_CLK)\r | |
674 | #define INT_PCLK (1u << INT_V_PCLK)\r | |
675 | #define INT_DTA (1u << INT_V_DTA)\r | |
676 | #define INT_TA (1u << INT_V_TA)\r | |
677 | #define INT_PIR6 (1u << INT_V_PIR6)\r | |
678 | #define INT_RK (1u << INT_V_RK)\r | |
679 | #define INT_RL (1u << INT_V_RL)\r | |
680 | #define INT_RX (1u << INT_V_RX)\r | |
681 | #define INT_TM (1u << INT_V_TM)\r | |
682 | #define INT_RP (1u << INT_V_RP)\r | |
683 | #define INT_TS (1u << INT_V_TS)\r | |
684 | #define INT_HK (1u << INT_V_HK)\r | |
685 | #define INT_RQ (1u << INT_V_RQ)\r | |
686 | #define INT_DZRX (1u << INT_V_DZRX)\r | |
687 | #define INT_DZTX (1u << INT_V_DZTX)\r | |
688 | #define INT_TQ (1u << INT_V_TQ)\r | |
689 | #define INT_RY (1u << INT_V_RY)\r | |
690 | #define INT_XQ (1u << INT_V_XQ)\r | |
691 | #define INT_XU (1u << INT_V_XU)\r | |
692 | #define INT_TU (1u << INT_V_TU)\r | |
693 | #define INT_RF (1u << INT_V_RF)\r | |
694 | #define INT_RC (1u << INT_V_RC)\r | |
695 | #define INT_PIR5 (1u << INT_V_PIR5)\r | |
696 | #define INT_PTR (1u << INT_V_PTR)\r | |
697 | #define INT_PTP (1u << INT_V_PTP)\r | |
698 | #define INT_TTI (1u << INT_V_TTI)\r | |
699 | #define INT_TTO (1u << INT_V_TTO)\r | |
700 | #define INT_LPT (1u << INT_V_LPT)\r | |
701 | #define INT_VHRX (1u << INT_V_VHRX)\r | |
702 | #define INT_VHTX (1u << INT_V_VHTX)\r | |
703 | #define INT_CR (1u << INT_V_CR)\r | |
704 | #define INT_DLI (1u << INT_V_DLI)\r | |
705 | #define INT_DLO (1u << INT_V_DLO)\r | |
706 | #define INT_DCI (1u << INT_V_DCI)\r | |
707 | #define INT_DCO (1u << INT_V_DCO)\r | |
708 | #define INT_PIR4 (1u << INT_V_PIR4)\r | |
709 | #define INT_PIR3 (1u << INT_V_PIR3)\r | |
710 | #define INT_PIR2 (1u << INT_V_PIR2)\r | |
711 | #define INT_PIR1 (1u << INT_V_PIR1)\r | |
712 | \r | |
713 | #define IPL_CLK 6 /* int pri levels */\r | |
714 | #define IPL_PCLK 6\r | |
715 | #define IPL_DTA 6\r | |
716 | #define IPL_TA 6\r | |
717 | #define IPL_RK 5\r | |
718 | #define IPL_RL 5\r | |
719 | #define IPL_RX 5\r | |
720 | #define IPL_TM 5\r | |
721 | #define IPL_RP 5\r | |
722 | #define IPL_TS 5\r | |
723 | #define IPL_HK 5\r | |
724 | #define IPL_RQ 5\r | |
725 | #define IPL_DZRX 5\r | |
726 | #define IPL_DZTX 5\r | |
727 | #define IPL_TQ 5\r | |
728 | #define IPL_RY 5\r | |
729 | #define IPL_XQ 5\r | |
730 | #define IPL_XU 5\r | |
731 | #define IPL_TU 5\r | |
732 | #define IPL_RF 5\r | |
733 | #define IPL_RC 5\r | |
734 | #define IPL_PTR 4\r | |
735 | #define IPL_PTP 4\r | |
736 | #define IPL_TTI 4\r | |
737 | #define IPL_TTO 4\r | |
738 | #define IPL_LPT 4\r | |
739 | #define IPL_VHRX 4\r | |
740 | #define IPL_VHTX 4\r | |
741 | #define IPL_CR 4\r | |
742 | #define IPL_DLI 4\r | |
743 | #define IPL_DLO 4\r | |
744 | #define IPL_DCI 4\r | |
745 | #define IPL_DCO 4\r | |
746 | \r | |
747 | #define IPL_PIR7 7\r | |
748 | #define IPL_PIR6 6\r | |
749 | #define IPL_PIR5 5\r | |
750 | #define IPL_PIR4 4\r | |
751 | #define IPL_PIR3 3\r | |
752 | #define IPL_PIR2 2\r | |
753 | #define IPL_PIR1 1\r | |
754 | \r | |
755 | /* Device vectors */\r | |
756 | \r | |
757 | #define VEC_Q 0000 /* vector base */\r | |
758 | #define VEC_PIRQ 0240\r | |
759 | #define VEC_TTI 0060\r | |
760 | #define VEC_TTO 0064\r | |
761 | #define VEC_PTR 0070\r | |
762 | #define VEC_PTP 0074\r | |
763 | #define VEC_CLK 0100\r | |
764 | #define VEC_PCLK 0104\r | |
765 | #define VEC_XQ 0120\r | |
766 | #define VEC_XU 0120\r | |
767 | #define VEC_RQ 0154\r | |
768 | #define VEC_RL 0160\r | |
769 | #define VEC_LPT 0200\r | |
770 | #define VEC_RF 0204\r | |
771 | #define VEC_HK 0210\r | |
772 | #define VEC_RC 0210\r | |
773 | #define VEC_RK 0220\r | |
774 | #define VEC_DTA 0214\r | |
775 | #define VEC_TM 0224\r | |
776 | #define VEC_TS 0224\r | |
777 | #define VEC_TU 0224\r | |
778 | #define VEC_CR 0230\r | |
779 | #define VEC_RP 0254\r | |
780 | #define VEC_TQ 0260\r | |
781 | #define VEC_TA 0260\r | |
782 | #define VEC_RX 0264\r | |
783 | #define VEC_RY 0264\r | |
784 | #define VEC_DLI 0300\r | |
785 | #define VEC_DLO 0304\r | |
786 | #define VEC_DCI 0300\r | |
787 | #define VEC_DCO 0304\r | |
788 | #define VEC_DZRX 0300\r | |
789 | #define VEC_DZTX 0304\r | |
790 | #define VEC_VHRX 0310\r | |
791 | #define VEC_VHTX 0314\r | |
792 | \r | |
793 | /* Interrupt macros */\r | |
794 | \r | |
795 | #define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv)\r | |
796 | #define IREQ(dv) int_req[IPL_##dv]\r | |
797 | #define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv)\r | |
798 | #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv)\r | |
799 | \r | |
800 | /* Massbus definitions */\r | |
801 | \r | |
802 | #define MBA_NUM 2 /* number of MBA's */\r | |
803 | #define MBA_RP 0 /* MBA for RP */\r | |
804 | #define MBA_TU 1 /* MBA for TU */\r | |
805 | #define MBA_RMASK 037 /* max 32 reg */\r | |
806 | #define MBE_NXD 1 /* nx drive */\r | |
807 | #define MBE_NXR 2 /* nx reg */\r | |
808 | #define MBE_GOE 3 /* err on GO */\r | |
809 | \r | |
810 | /* CPU and FPU macros */\r | |
811 | \r | |
812 | #define update_MM ((MMR0 & MMR0_FREEZE) == 0)\r | |
813 | #define setTRAP(name) trap_req = trap_req | (name)\r | |
814 | #define setCPUERR(name) CPUERR = CPUERR | (name)\r | |
815 | #define ABORT(val) longjmp (save_env, (val))\r | |
816 | #define SP R[6]\r | |
817 | #define PC R[7]\r | |
818 | \r | |
819 | /* Function prototypes */\r | |
820 | \r | |
821 | int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf);\r | |
822 | int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf);\r | |
823 | int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf);\r | |
824 | int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf);\r | |
825 | \r | |
826 | t_stat set_addr (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
827 | t_stat show_addr (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
828 | t_stat set_addr_flt (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
829 | t_stat set_vec (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
830 | t_stat show_vec (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
831 | t_stat auto_config (char *name, int32 nctrl);\r | |
832 | t_stat build_ubus_tab (DEVICE *dptr, DIB *dibp);\r | |
833 | \r | |
834 | int32 mba_rdbufW (uint32 mbus, int32 bc, uint16 *buf);\r | |
835 | int32 mba_wrbufW (uint32 mbus, int32 bc, uint16 *buf);\r | |
836 | int32 mba_chbufW (uint32 mbus, int32 bc, uint16 *buf);\r | |
837 | int32 mba_get_bc (uint32 mbus);\r | |
838 | int32 mba_get_csr (uint32 mbus);\r | |
839 | void mba_upd_ata (uint32 mbus, uint32 val);\r | |
840 | void mba_set_exc (uint32 mbus);\r | |
841 | void mba_set_don (uint32 mbus);\r | |
842 | void mba_set_enbdis (uint32 mb, t_bool dis);\r | |
843 | t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
844 | \r | |
845 | int32 clk_cosched (int32 wait);\r | |
846 | \r | |
847 | #endif\r |