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1 | /* pdp11_xu.h: DEUNA/DELUA ethernet controller information\r |
2 | ------------------------------------------------------------------------------\r | |
3 | \r | |
4 | Copyright (c) 2003-2005, David T. Hittner\r | |
5 | \r | |
6 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
7 | copy of this software and associated documentation files (the "Software"),\r | |
8 | to deal in the Software without restriction, including without limitation\r | |
9 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
10 | and/or sell copies of the Software, and to permit persons to whom the\r | |
11 | Software is furnished to do so, subject to the following conditions:\r | |
12 | \r | |
13 | The above copyright notice and this permission notice shall be included in\r | |
14 | all copies or substantial portions of the Software.\r | |
15 | \r | |
16 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
17 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
18 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
19 | THE AUTHOR BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
20 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
21 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
22 | \r | |
23 | Except as contained in this notice, the name of the author shall not be\r | |
24 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
25 | in this Software without prior written authorization from the author.\r | |
26 | \r | |
27 | ------------------------------------------------------------------------------\r | |
28 | \r | |
29 | Modification history:\r | |
30 | \r | |
31 | 08-Dec-05 DTH Added load_server, increased UDBSIZE for system ID parameters\r | |
32 | 07-Jul-05 RMS Removed extraneous externs\r | |
33 | 05-Jan-04 DTH Added network statistics\r | |
34 | 31-Dec-03 DTH Added reserved states\r | |
35 | 28-Dec-03 DTH Corrected MODE bitmasks\r | |
36 | 23-Dec-03 DTH Corrected TXR and RXR bitmasks\r | |
37 | 03-Dec-03 DTH Refitted to SIMH v3.0 platform\r | |
38 | 05-May-03 DTH Started XU simulation\r | |
39 | \r | |
40 | ------------------------------------------------------------------------------\r | |
41 | */\r | |
42 | \r | |
43 | #ifndef _PDP11_XU_H\r | |
44 | #define _PDP11_XU_H\r | |
45 | \r | |
46 | \r | |
47 | #if defined (VM_PDP10) /* PDP10 version */\r | |
48 | #include "pdp10_defs.h"\r | |
49 | #define XU_RDX 8\r | |
50 | #define XU_WID 16\r | |
51 | extern int32 int_req;\r | |
52 | \r | |
53 | #elif defined (VM_VAX) /* VAX version */\r | |
54 | #include "vax_defs.h"\r | |
55 | #define XU_RDX 8\r | |
56 | #define XU_WID 16\r | |
57 | extern int32 int_req[IPL_HLVL];\r | |
58 | \r | |
59 | #else /* PDP-11 version */\r | |
60 | #include "pdp11_defs.h"\r | |
61 | #define XU_RDX 8\r | |
62 | #define XU_WID 16\r | |
63 | extern int32 int_req[IPL_HLVL];\r | |
64 | #endif /* VM_PDP10 */\r | |
65 | \r | |
66 | #include "sim_ether.h"\r | |
67 | \r | |
68 | #define XU_QUE_MAX 500 /* message queue array */\r | |
69 | #define XU_FILTER_MAX 11 /* mac + 10 multicast addrs */\r | |
70 | #define XU_SERVICE_INTERVAL 100 /* times per second */\r | |
71 | #define XU_ID_TIMER_VAL 540 /* 9 min * 60 sec */\r | |
72 | #define UDBSIZE 200 /* max size of UDB (in words) */\r | |
73 | \r | |
74 | enum xu_type {XU_T_DEUNA, XU_T_DELUA};\r | |
75 | \r | |
76 | struct xu_setup {\r | |
77 | int promiscuous; /* promiscuous mode enabled */\r | |
78 | int multicast; /* enable all multicast addresses */\r | |
79 | int mac_count; /* number of multicast mac addresses */\r | |
80 | ETH_MAC macs[XU_FILTER_MAX]; /* MAC addresses to respond to */\r | |
81 | };\r | |
82 | \r | |
83 | /* Network Statistics -\r | |
84 | some of these will always be zero in the simulated environment,\r | |
85 | since there is no ability for the sim_ether network driver to see\r | |
86 | things like incoming runts, collision tests, babbling, etc.\r | |
87 | */\r | |
88 | struct xu_stats {\r | |
89 | uint16 secs; /* seconds since last clear */\r | |
90 | uint32 frecv; /* frames received */\r | |
91 | uint32 mfrecv; /* multicast frames received */\r | |
92 | uint16 rxerf; /* receive error flags */\r | |
93 | uint32 frecve; /* frames received with errors */\r | |
94 | uint32 rbytes; /* data bytes received */\r | |
95 | uint32 mrbytes; /* multicast data bytes received */\r | |
96 | uint16 rlossi; /* received frames lost - internal err */\r | |
97 | uint16 rlossl; /* received frames lost - local buffers */\r | |
98 | uint32 ftrans; /* frames transmitted */\r | |
99 | uint32 mftrans; /* multicast frames transmitted */\r | |
100 | uint32 ftrans3; /* frames transmitted with 3+ tries */\r | |
101 | uint32 ftrans2; /* frames transmitted - two tries */\r | |
102 | uint32 ftransd; /* frames transmitted - deferred */\r | |
103 | uint32 tbytes; /* data bytes transmitted */\r | |
104 | uint32 mtbytes; /* multicast data bytes transmitted */\r | |
105 | uint16 txerf; /* transmit error flags summary */\r | |
106 | uint16 ftransa; /* transmit frames aborted */\r | |
107 | uint16 txccf; /* transmit collision test failure */\r | |
108 | uint16 porterr; /* port driver errors */\r | |
109 | uint16 bablcnt; /* babble counter */\r | |
110 | };\r | |
111 | \r | |
112 | struct xu_device {\r | |
113 | /*+ initialized values - DO NOT MOVE */\r | |
114 | ETH_PCALLBACK rcallback; /* read callback routine */\r | |
115 | ETH_PCALLBACK wcallback; /* write callback routine */\r | |
116 | ETH_MAC mac; /* MAC address */\r | |
117 | enum xu_type type; /* controller type */\r | |
118 | /*- initialized values - DO NOT MOVE */\r | |
119 | \r | |
120 | /* I/O register storage */\r | |
121 | uint32 irq; /* interrupt request flag */\r | |
122 | \r | |
123 | /* buffers, etc. */\r | |
124 | ETH_DEV* etherface;\r | |
125 | ETH_PACK read_buffer;\r | |
126 | ETH_PACK write_buffer;\r | |
127 | ETH_QUE ReadQ;\r | |
128 | ETH_MAC load_server; /* load server address */\r | |
129 | int idtmr; /* countdown for ID Timer */\r | |
130 | int sectmr; /* countup for one second timer */\r | |
131 | struct xu_setup setup;\r | |
132 | struct xu_stats stats; /* reportable network statistics */\r | |
133 | \r | |
134 | /* copied from dec_deuna.h */\r | |
135 | uint16 pcsr0; /* primary DEUNA registers */\r | |
136 | uint16 pcsr1;\r | |
137 | uint16 pcsr2;\r | |
138 | uint16 pcsr3;\r | |
139 | uint32 mode; /* mode register */\r | |
140 | uint32 pcbb; /* port command block base */\r | |
141 | uint32 stat; /* extended port status */\r | |
142 | \r | |
143 | uint32 tdrb; /* transmit desc ring base */\r | |
144 | uint32 telen; /* transmit desc ring entry len */\r | |
145 | uint32 trlen; /* transmit desc ring length */\r | |
146 | uint32 txnext; /* transmit buffer pointer */\r | |
147 | uint32 rdrb; /* receive desc ring base */\r | |
148 | uint32 relen; /* receive desc ring entry len */\r | |
149 | uint32 rrlen; /* receive desc ring length */\r | |
150 | uint32 rxnext; /* receive buffer pointer */\r | |
151 | \r | |
152 | uint16 pcb[4]; /* copy of Port Command Block */\r | |
153 | uint16 udb[UDBSIZE]; /* copy of Unibus Data Block */\r | |
154 | uint16 rxhdr[4]; /* content of RX ring entry, during wait */\r | |
155 | uint16 txhdr[4]; /* content of TX ring entry, during xmit */\r | |
156 | };\r | |
157 | \r | |
158 | struct xu_controller {\r | |
159 | DEVICE* dev; /* device block */\r | |
160 | UNIT* unit; /* unit block */\r | |
161 | DIB* dib; /* device interface block */\r | |
162 | struct xu_device* var; /* controller-specific variables */\r | |
163 | };\r | |
164 | \r | |
165 | typedef struct xu_controller CTLR;\r | |
166 | \r | |
167 | /* PCSR0 register definitions */\r | |
168 | #define PCSR0_SERI 0100000 /* <15> Status Error Intr */\r | |
169 | #define PCSR0_PCEI 0040000 /* <14> Port Command Error Intr */\r | |
170 | #define PCSR0_RXI 0020000 /* <13> Receive Interrupt */\r | |
171 | #define PCSR0_TXI 0010000 /* <12> Transmit Interrupt */\r | |
172 | #define PCSR0_DNI 0004000 /* <11> Done Interrupt */\r | |
173 | #define PCSR0_RCBI 0002000 /* <10> Recv Buffer Unavail Intr */\r | |
174 | #define PCSR0_USCI 0000400 /* <08> Unsolicited State Chg Inter */\r | |
175 | #define PCSR0_INTR 0000200 /* <07> Interrupt Summary */\r | |
176 | #define PCSR0_INTE 0000100 /* <06> Interrupt Enable */\r | |
177 | #define PCSR0_RSET 0000040 /* <05> Reset */\r | |
178 | #define PCSR0_PCMD 0000017 /* <03:00> Port Command field */\r | |
179 | \r | |
180 | /* PCSR0 Port Commands */\r | |
181 | #define CMD_NOOP 000 /* No-op */\r | |
182 | #define CMD_GETPCBB 001 /* Get PCB base */\r | |
183 | #define CMD_GETCMD 002 /* Get Command */\r | |
184 | #define CMD_SELFTEST 003 /* Self-test init */\r | |
185 | #define CMD_START 004 /* Start xmit/recv */\r | |
186 | #define CMD_BOOT 005 /* Boot */\r | |
187 | #define CMD_RSV06 006 /* Reserved */\r | |
188 | #define CMD_RSV07 007 /* Reserved */\r | |
189 | #define CMD_PDMD 010 /* Polling Demand */\r | |
190 | #define CMD_RSV11 011 /* Reserved */\r | |
191 | #define CMD_RSV12 012 /* Reserved */\r | |
192 | #define CMD_RSV13 013 /* Reserved */\r | |
193 | #define CMD_RSV14 014 /* Reserved */\r | |
194 | #define CMD_RSV15 015 /* Reserved */\r | |
195 | #define CMD_HALT 016 /* Halt */\r | |
196 | #define CMD_STOP 017 /* Stop */\r | |
197 | \r | |
198 | /* PCSR1 register definitions */\r | |
199 | #define PCSR1_XPWR 0100000 /* <15> Tranceiver power failure */\r | |
200 | #define PCSR1_ICAB 0040000 /* <14> Port/Link cable failure */\r | |
201 | #define PCSR1_ECOD 0037400 /* <13:08> Self-test error code */\r | |
202 | #define PCSR1_PCTO 0000200 /* <07> Port Command Timeout */\r | |
203 | #define PCSR1_TYPE 0000160 /* <06:04> Interface type */\r | |
204 | #define PCSR1_STATE 0000017 /* <03:00> State: */\r | |
205 | \r | |
206 | /* PCSR1 Types */\r | |
207 | #define TYPE_DEUNA (0 << 4) /* Controller is a DEUNA */\r | |
208 | #define TYPE_DELUA (1 << 4) /* Controller is a DELUA */\r | |
209 | \r | |
210 | /* PCSR1 States */\r | |
211 | #define STATE_RESET 000 /* Reset */\r | |
212 | #define STATE_PLOAD 001 /* Primary Load */\r | |
213 | #define STATE_READY 002 /* Ready */\r | |
214 | #define STATE_RUNNING 003 /* Running */\r | |
215 | #define STATE_UHALT 005 /* UNIBUS Halted */\r | |
216 | #define STATE_NHALT 006 /* NI Halted */\r | |
217 | #define STATE_NUHALT 007 /* NI and UNIBUS Halted */\r | |
218 | #define STATE_HALT 010 /* Halted */\r | |
219 | #define STATE_SLOAD 017 /* Secondary Load */\r | |
220 | \r | |
221 | /* Status register definitions */\r | |
222 | #define STAT_ERRS 0100000 /* <15> error summary */\r | |
223 | #define STAT_MERR 0040000 /* <14> multiple errors */\r | |
224 | #define STAT_BABL 0020000 /* <13> Transmitter on too long [DELUA only] */\r | |
225 | #define STAT_CERR 0010000 /* <12> collision test error */\r | |
226 | #define STAT_TMOT 0004000 /* <11> UNIBUS timeout */\r | |
227 | #define STAT_RRNG 0001000 /* <09> receive ring error */\r | |
228 | #define STAT_TRNG 0000400 /* <08> transmit ring error */\r | |
229 | #define STAT_PTCH 0000200 /* <07> ROM patch */\r | |
230 | #define STAT_RRAM 0000100 /* <06> running from RAM */\r | |
231 | #define STAT_RREV 0000077 /* <05:00> ROM version */\r | |
232 | \r | |
233 | /* Mode definitions */\r | |
234 | #define MODE_PROM 0100000 /* <15> Promiscuous Mode */\r | |
235 | #define MODE_ENAL 0040000 /* <14> Enable All Multicasts */\r | |
236 | #define MODE_DRDC 0020000 /* <13> Disable Data Chaining */\r | |
237 | #define MODE_TPAD 0010000 /* <12> Transmit Msg Pad Enable */\r | |
238 | #define MODE_ECT 0004000 /* <11> Enable Collision Test */\r | |
239 | #define MODE_DMNT 0001000 /* <09> Disable Maint Message */\r | |
240 | #define MODE_INTL 0000200 /* <07> Internal Loopback [DELUA only] */\r | |
241 | #define MODE_DTCR 0000010 /* <03> Disable Transmit CRC */\r | |
242 | #define MODE_LOOP 0000004 /* <02> Internal Loopback Mode */\r | |
243 | #define MODE_HDPX 0000001 /* <00> Half-Duplex Mode */\r | |
244 | \r | |
245 | /* Function Code definitions */\r | |
246 | #define FC_NOOP 0000000 /* no-op */\r | |
247 | #define FC_LSM 0000001 /* Load and Start Microaddress */\r | |
248 | #define FC_RDPA 0000002 /* Read Default Physical Address */\r | |
249 | #define FC_RPA 0000004 /* Read Physical Address */\r | |
250 | #define FC_WPA 0000005 /* Write Physical Address */\r | |
251 | #define FC_RMAL 0000006 /* Read Multicast Address List */\r | |
252 | #define FC_WMAL 0000007 /* Write Multicast Address List */\r | |
253 | #define FC_RRF 0000010 /* Read Ring Format */\r | |
254 | #define FC_WRF 0000011 /* Write Ring Format */\r | |
255 | #define FC_RDCTR 0000012 /* Read Counters */\r | |
256 | #define FC_RDCLCTR 0000013 /* Read and Clear Counters */\r | |
257 | #define FC_RMODE 0000014 /* Read Mode */\r | |
258 | #define FC_WMODE 0000015 /* Write Mode */\r | |
259 | #define FC_RSTAT 0000016 /* Read Status */\r | |
260 | #define FC_RCSTAT 0000017 /* Read and Clear Status */\r | |
261 | #define FC_DIM 0000020 /* Dump Internal Memory */\r | |
262 | #define FC_LIM 0000021 /* Load Internal Memory */\r | |
263 | #define FC_RSID 0000022 /* Read System ID parameters */\r | |
264 | #define FC_WSID 0000023 /* Write System ID parameters */\r | |
265 | #define FC_RLSA 0000024 /* Read Load Server Address */\r | |
266 | #define FC_WLSA 0000025 /* Write Load Server Address */\r | |
267 | \r | |
268 | /* Transmitter Ring definitions */\r | |
269 | #define TXR_OWN 0100000 /* <15> we own it (1) */\r | |
270 | #define TXR_ERRS 0040000 /* <14> error summary */\r | |
271 | #define TXR_MTCH 0020000 /* <13> Station Match */\r | |
272 | #define TXR_MORE 0010000 /* <12> Mult Retries Needed */\r | |
273 | #define TXR_ONE 0004000 /* <11> One Collision */\r | |
274 | #define TXR_DEF 0002000 /* <10> Deferred */\r | |
275 | #define TXR_STF 0001000 /* <09> Start Of Frame */\r | |
276 | #define TXR_ENF 0000400 /* <08> End Of Frame */\r | |
277 | #define TXR_BUFL 0100000 /* <15> Buffer Length Error */\r | |
278 | #define TXR_UBTO 0040000 /* <14> UNIBUS TimeOut */\r | |
279 | #define TXR_UFLO 0020000 /* <13> Underflow Error */\r | |
280 | #define TXR_LCOL 0010000 /* <12> Late Collision */\r | |
281 | #define TXR_LCAR 0004000 /* <11> Lost Carrier */\r | |
282 | #define TXR_RTRY 0002000 /* <10> Retry Failure (16x) */\r | |
283 | #define TXR_TDR 0001777 /* <9:0> TDR value if RTRY=1 */\r | |
284 | \r | |
285 | /* Receiver Ring definitions */\r | |
286 | #define RXR_OWN 0100000 /* <15> we own it (1) */\r | |
287 | #define RXR_ERRS 0040000 /* <14> Error Summary */\r | |
288 | #define RXR_FRAM 0020000 /* <13> Frame Error */\r | |
289 | #define RXR_OFLO 0010000 /* <12> Message Overflow */\r | |
290 | #define RXR_CRC 0004000 /* <11> CRC Check Error */\r | |
291 | #define RXR_STF 0001000 /* <09> Start Of Frame */\r | |
292 | #define RXR_ENF 0000400 /* <08> End Of Frame */\r | |
293 | #define RXR_BUFL 0100000 /* <15> Buffer Length error */\r | |
294 | #define RXR_UBTO 0040000 /* <14> UNIBUS TimeOut */\r | |
295 | #define RXR_NCHN 0020000 /* <13> No Data Chaining */\r | |
296 | #define RXR_OVRN 0010000 /* <12> Overrun Error [DELUA only] */\r | |
297 | #define RXR_MLEN 0007777 /* <11:0> Message Length */\r | |
298 | \r | |
299 | /* debugging bitmaps */\r | |
300 | #define DBG_TRC 0x0001 /* trace routine calls */\r | |
301 | #define DBG_REG 0x0002 /* trace read/write registers */\r | |
302 | #define DBG_WRN 0x0004 /* display warnings */\r | |
303 | #define DBG_PCK 0x0080 /* display packets */\r | |
304 | #define DBG_ETH 0x8000 /* debug ethernet device */\r | |
305 | \r | |
306 | #endif /* _PDP11_XU_H */\r |