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1 | /* pdp18b_sys.c: 18b PDP's simulator interface\r |
2 | \r | |
3 | Copyright (c) 1993-2006, Robert M Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | 30-Oct-06 RMS Added infinite loop stop\r | |
27 | 18-Oct-06 RMS Re-ordered device list\r | |
28 | 02-Oct-06 RMS Added RDCLK instruction\r | |
29 | 12-Jun-06 RMS Added Fiodec, Baudot display\r | |
30 | RMS Generalized LOAD to handle HRI, RIM, or BIN files\r | |
31 | 22-Jul-05 RMS Removed AAS, error in V1 reference manual\r | |
32 | 09-Jan-04 RMS Fixed instruction table errors\r | |
33 | 18-Oct-03 RMS Added DECtape off reel message\r | |
34 | 30-Jul-03 RMS Fixed FPM class mask\r | |
35 | 18-Jul-03 RMS Added FP15 support\r | |
36 | 02-Mar-03 RMS Split loaders apart for greater flexibility\r | |
37 | 09-Feb-03 RMS Fixed bug in FMTASC (found by Hans Pufal)\r | |
38 | 31-Jan-03 RMS Added support for RB09\r | |
39 | 05-Oct-02 RMS Added variable device number support\r | |
40 | 25-Jul-02 RMS Added PDP-4 DECtape support\r | |
41 | 10-Feb-02 RMS Added PDP-7 DECtape IOT's\r | |
42 | 03-Feb-02 RMS Fixed typo (found by Robert Alan Byer)\r | |
43 | 17-Sep-01 RMS Removed multiconsole support\r | |
44 | 27-May-01 RMS Added second Teletype support\r | |
45 | 18-May-01 RMS Added PDP-9,-15 API IOT's\r | |
46 | 12-May-01 RMS Fixed bug in RIM loaders\r | |
47 | 14-Mar-01 RMS Added extension detection of RIM format tapes\r | |
48 | 21-Jan-01 RMS Added DECtape support\r | |
49 | 30-Nov-00 RMS Added PDP-9,-15 RIM/BIN loader format\r | |
50 | 30-Oct-00 RMS Added support for examine to file\r | |
51 | 27-Oct-98 RMS V2.4 load interface\r | |
52 | 20-Oct-97 RMS Fixed endian dependence in RIM loader\r | |
53 | (found by Michael Somos)\r | |
54 | */\r | |
55 | \r | |
56 | #include "pdp18b_defs.h"\r | |
57 | #include <ctype.h>\r | |
58 | \r | |
59 | extern DEVICE cpu_dev;\r | |
60 | #if defined (PDP15)\r | |
61 | extern DEVICE fpp_dev;\r | |
62 | #endif\r | |
63 | extern DEVICE ptr_dev, ptp_dev;\r | |
64 | extern DEVICE tti_dev, tto_dev;\r | |
65 | extern UNIT tti_unit, tto_unit;\r | |
66 | extern DEVICE clk_dev;\r | |
67 | #if defined (TYPE62)\r | |
68 | extern DEVICE lp62_dev;\r | |
69 | #endif\r | |
70 | #if defined (TYPE647)\r | |
71 | extern DEVICE lp647_dev;\r | |
72 | #endif\r | |
73 | #if defined (LP09)\r | |
74 | extern DEVICE lp09_dev;\r | |
75 | #endif\r | |
76 | #if defined (LP15)\r | |
77 | extern DEVICE lp15_dev;\r | |
78 | #endif\r | |
79 | extern DEVICE dt_dev;\r | |
80 | #if defined (DRM)\r | |
81 | extern DEVICE drm_dev;\r | |
82 | #endif\r | |
83 | #if defined (RB)\r | |
84 | extern DEVICE rb_dev;\r | |
85 | #endif\r | |
86 | #if defined (RF)\r | |
87 | extern DEVICE rf_dev;\r | |
88 | #endif\r | |
89 | #if defined (RP)\r | |
90 | extern DEVICE rp_dev;\r | |
91 | #endif\r | |
92 | #if defined (MTA)\r | |
93 | extern DEVICE mt_dev;\r | |
94 | #endif\r | |
95 | #if defined (TTY1)\r | |
96 | extern DEVICE tti1_dev, tto1_dev;\r | |
97 | extern UNIT tti1_unit, tto1_unit;\r | |
98 | #endif\r | |
99 | extern UNIT cpu_unit;\r | |
100 | extern REG cpu_reg[];\r | |
101 | extern int32 M[];\r | |
102 | extern int32 memm;\r | |
103 | extern int32 PC;\r | |
104 | extern const char asc_to_baud[128];\r | |
105 | extern const char baud_to_asc[64];\r | |
106 | extern const char fio_to_asc[64];\r | |
107 | \r | |
108 | /* SCP data structures and interface routines\r | |
109 | \r | |
110 | sim_name simulator name string\r | |
111 | sim_PC pointer to saved PC register descriptor\r | |
112 | sim_emax number of words for examine\r | |
113 | sim_devices array of pointers to simulated devices\r | |
114 | sim_stop_messages array of pointers to stop messages\r | |
115 | sim_load binary loader\r | |
116 | */\r | |
117 | \r | |
118 | #if defined (PDP4)\r | |
119 | char sim_name[] = "PDP-4";\r | |
120 | #elif defined (PDP7)\r | |
121 | char sim_name[] = "PDP-7";\r | |
122 | #elif defined (PDP9)\r | |
123 | char sim_name[] = "PDP-9";\r | |
124 | #elif defined (PDP15)\r | |
125 | char sim_name[] = "PDP-15";\r | |
126 | #endif\r | |
127 | \r | |
128 | REG *sim_PC = &cpu_reg[0];\r | |
129 | \r | |
130 | int32 sim_emax = 2;\r | |
131 | \r | |
132 | DEVICE *sim_devices[] = {\r | |
133 | &cpu_dev,\r | |
134 | &clk_dev,\r | |
135 | #if defined (PDP15)\r | |
136 | &fpp_dev,\r | |
137 | #endif\r | |
138 | &ptr_dev,\r | |
139 | &ptp_dev,\r | |
140 | &tti_dev,\r | |
141 | &tto_dev,\r | |
142 | #if defined (TYPE62)\r | |
143 | &lp62_dev,\r | |
144 | #endif\r | |
145 | #if defined (TYPE647)\r | |
146 | &lp647_dev,\r | |
147 | #endif\r | |
148 | #if defined (LP09)\r | |
149 | &lp09_dev,\r | |
150 | #endif\r | |
151 | #if defined (LP15)\r | |
152 | &lp15_dev,\r | |
153 | #endif\r | |
154 | #if defined (DRM)\r | |
155 | &drm_dev,\r | |
156 | #endif\r | |
157 | #if defined (RB)\r | |
158 | &rb_dev,\r | |
159 | #endif\r | |
160 | #if defined (RF)\r | |
161 | &rf_dev,\r | |
162 | #endif\r | |
163 | #if defined (RP)\r | |
164 | &rp_dev,\r | |
165 | #endif\r | |
166 | &dt_dev,\r | |
167 | #if defined (MTA)\r | |
168 | &mt_dev,\r | |
169 | #endif\r | |
170 | #if defined (TTY1)\r | |
171 | &tti1_dev, &tto1_dev,\r | |
172 | #endif\r | |
173 | NULL\r | |
174 | };\r | |
175 | \r | |
176 | const char *sim_stop_messages[] = {\r | |
177 | "Unknown error",\r | |
178 | "Undefined instruction",\r | |
179 | "HALT instruction",\r | |
180 | "Breakpoint",\r | |
181 | "Nested XCT's",\r | |
182 | "Invalid API interrupt",\r | |
183 | "Non-standard device number",\r | |
184 | "Memory management error",\r | |
185 | "FP15 instruction disabled",\r | |
186 | "DECtape off reel",\r | |
187 | "Infinite loop"\r | |
188 | };\r | |
189 | \r | |
190 | /* Binary loaders */\r | |
191 | \r | |
192 | int32 getword (FILE *fileref, int32 *hi)\r | |
193 | {\r | |
194 | int32 word, bits, st, ch;\r | |
195 | \r | |
196 | word = st = bits = 0;\r | |
197 | do {\r | |
198 | if ((ch = getc (fileref)) == EOF) return -1;\r | |
199 | if (ch & 0200) {\r | |
200 | word = (word << 6) | (ch & 077);\r | |
201 | bits = (bits << 1) | ((ch >> 6) & 1);\r | |
202 | st++;\r | |
203 | }\r | |
204 | } while (st < 3);\r | |
205 | if (hi != NULL) *hi = bits;\r | |
206 | return word;\r | |
207 | }\r | |
208 | \r | |
209 | /* PDP-4/PDP-7 RIM format loader\r | |
210 | \r | |
211 | Tape format\r | |
212 | dac addr\r | |
213 | data\r | |
214 | :\r | |
215 | dac addr\r | |
216 | data\r | |
217 | jmp addr or hlt\r | |
218 | */\r | |
219 | \r | |
220 | t_stat rim_load_47 (FILE *fileref, char *cptr)\r | |
221 | {\r | |
222 | int32 origin, val;\r | |
223 | \r | |
224 | if (*cptr != 0) return SCPE_2MARG;\r | |
225 | origin = 0200;\r | |
226 | for (;;) {\r | |
227 | if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;\r | |
228 | if ((val & 0760000) == 0040000) { /* DAC? */\r | |
229 | origin = val & 017777;\r | |
230 | if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;\r | |
231 | if (MEM_ADDR_OK (origin)) M[origin++] = val;\r | |
232 | }\r | |
233 | else if ((val & 0760000) == OP_JMP) { /* JMP? */\r | |
234 | PC = ((origin - 1) & 060000) | (val & 017777);\r | |
235 | return SCPE_OK;\r | |
236 | }\r | |
237 | else if (val == OP_HLT) break; /* HLT? */\r | |
238 | else return SCPE_FMT; /* error */\r | |
239 | }\r | |
240 | return SCPE_OK; /* done */\r | |
241 | }\r | |
242 | \r | |
243 | /* PDP-7/9/15 hardware read-in format loader\r | |
244 | \r | |
245 | Tape format (read in address specified externally)\r | |
246 | data\r | |
247 | :\r | |
248 | data\r | |
249 | word to execute (bit 1 of last character set)\r | |
250 | */\r | |
251 | \r | |
252 | t_stat hri_load_7915 (FILE *fileref, char *cptr)\r | |
253 | {\r | |
254 | int32 bits, origin, val;\r | |
255 | char gbuf[CBUFSIZE];\r | |
256 | t_stat r;\r | |
257 | \r | |
258 | if (*cptr != 0) { /* more input? */\r | |
259 | cptr = get_glyph (cptr, gbuf, 0); /* get origin */\r | |
260 | origin = get_uint (gbuf, 8, AMASK, &r);\r | |
261 | if (r != SCPE_OK) return r;\r | |
262 | if (*cptr != 0) return SCPE_ARG; /* no more */\r | |
263 | }\r | |
264 | else origin = 0200; /* default 200 */\r | |
265 | \r | |
266 | for (;;) { /* word loop */\r | |
267 | if ((val = getword (fileref, &bits)) < 0) return SCPE_FMT;\r | |
268 | if (bits & 1) { /* end of tape? */\r | |
269 | if ((val & 0760000) == OP_JMP) PC = \r | |
270 | ((origin - 1) & 060000) | (val & 017777);\r | |
271 | else if (val != OP_HLT) return SCPE_FMT;\r | |
272 | break;\r | |
273 | }\r | |
274 | else if (MEM_ADDR_OK (origin)) M[origin++] = val;\r | |
275 | }\r | |
276 | return SCPE_OK;\r | |
277 | }\r | |
278 | \r | |
279 | /* PDP-9/15 BIN format loader\r | |
280 | \r | |
281 | BIN format (starts after RIM bootstrap)\r | |
282 | block/ origin (>= 0)\r | |
283 | count\r | |
284 | checksum\r | |
285 | data\r | |
286 | :\r | |
287 | data\r | |
288 | block/\r | |
289 | :\r | |
290 | endblock/ origin (< 0)\r | |
291 | */\r | |
292 | \r | |
293 | t_stat bin_load_915 (FILE *fileref, char *cptr)\r | |
294 | {\r | |
295 | int32 i, val, bits, origin, count, cksum;\r | |
296 | \r | |
297 | if (*cptr != 0) return SCPE_2MARG; /* no arguments */\r | |
298 | do {\r | |
299 | val = getword (fileref, & bits); /* find end RIM */\r | |
300 | } while ((val >= 0) && ((bits & 1) == 0));\r | |
301 | if (val < 0) rewind (fileref); /* no RIM? rewind */ \r | |
302 | for (;;) { /* block loop */\r | |
303 | if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;\r | |
304 | if (val & SIGN) {\r | |
305 | if (val != DMASK) PC = val & 077777;\r | |
306 | break;\r | |
307 | }\r | |
308 | cksum = origin = val; /* save origin */\r | |
309 | if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;\r | |
310 | cksum = cksum + val; /* add to cksum */\r | |
311 | count = (-val) & DMASK; /* save count */\r | |
312 | if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;\r | |
313 | cksum = cksum + val; /* add to cksum */\r | |
314 | for (i = 0; i < count; i++) {\r | |
315 | if ((val = getword (fileref, NULL)) < 0) return SCPE_FMT;\r | |
316 | cksum = cksum + val;\r | |
317 | if (MEM_ADDR_OK (origin)) M[origin++] = val;\r | |
318 | }\r | |
319 | if ((cksum & DMASK) != 0) return SCPE_CSUM;\r | |
320 | }\r | |
321 | return SCPE_OK;\r | |
322 | }\r | |
323 | \r | |
324 | /* Binary loader, all formats */\r | |
325 | \r | |
326 | t_stat sim_load (FILE *fileref, char *cptr, char *fnam, int flag)\r | |
327 | {\r | |
328 | extern int32 sim_switches;\r | |
329 | \r | |
330 | if (flag != 0) return SCPE_NOFNC;\r | |
331 | if (sim_switches & SWMASK ('S')) /* RIM format? */\r | |
332 | return rim_load_47 (fileref, cptr);\r | |
333 | if (sim_switches & SWMASK ('R')) /* HRI format? */\r | |
334 | return hri_load_7915 (fileref, cptr);\r | |
335 | if (!(sim_switches & SWMASK ('B')) && /* .rim extension? */\r | |
336 | match_ext (fnam, "RIM")) {\r | |
337 | int32 val, bits;\r | |
338 | do { /* look for HRI flag */\r | |
339 | val = getword (fileref, &bits);\r | |
340 | } while ((val >= 0) && ((bits & 1) == 0));\r | |
341 | rewind (fileref); /* rewind file */\r | |
342 | if (val < 0) return rim_load_47 (fileref, cptr); /* eof reached? */\r | |
343 | return hri_load_7915 (fileref, cptr); /* no, HRI */\r | |
344 | }\r | |
345 | return bin_load_915 (fileref, cptr); /* must be BIN */\r | |
346 | }\r | |
347 | \r | |
348 | /* Symbol tables */\r | |
349 | \r | |
350 | #define I_V_FL 18 /* inst class */\r | |
351 | #define I_M_FL 017 /* class mask */\r | |
352 | #define I_V_DC 22 /* default count */\r | |
353 | #define I_V_NPN 0 /* no operand */\r | |
354 | #define I_V_NPI 1 /* no operand IOT */\r | |
355 | #define I_V_IOT 2 /* IOT */\r | |
356 | #define I_V_MRF 3 /* memory reference */\r | |
357 | #define I_V_OPR 4 /* OPR */\r | |
358 | #define I_V_LAW 5 /* LAW */\r | |
359 | #define I_V_XR 6 /* index */\r | |
360 | #define I_V_XR9 7 /* index literal */\r | |
361 | #define I_V_EST 8 /* EAE setup */\r | |
362 | #define I_V_ESH 9 /* EAE shift */\r | |
363 | #define I_V_EMD 10 /* EAE mul-div */\r | |
364 | #define I_V_FPM 11 /* FP15 mem ref */\r | |
365 | #define I_V_FPI 12 /* FP15 indirect */\r | |
366 | #define I_V_FPN 13 /* FP15 no operand */\r | |
367 | #define I_NPN (I_V_NPN << I_V_FL)\r | |
368 | #define I_NPI (I_V_NPI << I_V_FL)\r | |
369 | #define I_IOT (I_V_IOT << I_V_FL)\r | |
370 | #define I_MRF (I_V_MRF << I_V_FL)\r | |
371 | #define I_OPR (I_V_OPR << I_V_FL)\r | |
372 | #define I_LAW (I_V_LAW << I_V_FL)\r | |
373 | #define I_XR (I_V_XR << I_V_FL)\r | |
374 | #define I_XR9 (I_V_XR9 << I_V_FL)\r | |
375 | #define I_EST (I_V_EST << I_V_FL)\r | |
376 | #define I_ESH (I_V_ESH << I_V_FL)\r | |
377 | #define I_EMD (I_V_EMD << I_V_FL)\r | |
378 | #define I_FPM (I_V_FPM << I_V_FL)\r | |
379 | #define I_FPI (I_V_FPI << I_V_FL)\r | |
380 | #define I_FPN (I_V_FPN << I_V_FL)\r | |
381 | #define MD(x) ((I_EMD) + ((x) << I_V_DC))\r | |
382 | \r | |
383 | static const int32 masks[] = {\r | |
384 | 0777777, 0777767, 0770000, 0760000,\r | |
385 | 0763730, 0760000, 0777000, 0777000,\r | |
386 | 0740700, 0760700, 0777700, 0777777,\r | |
387 | 0777777, 0777777\r | |
388 | };\r | |
389 | \r | |
390 | /* If both NPN (clear AC) and NPI versions of an IOT are defined,\r | |
391 | the NPN version must come first */\r | |
392 | \r | |
393 | static const char *opcode[] = {\r | |
394 | "CAL", "DAC", "JMS", "DZM", /* mem refs */\r | |
395 | "LAC", "XOR", "ADD", "TAD",\r | |
396 | "XCT", "ISZ", "AND", "SAD",\r | |
397 | "JMP",\r | |
398 | \r | |
399 | #if defined (PDP9) || defined (PDP15) /* mem ref ind */\r | |
400 | "CAL*", "DAC*", "JMS*", "DZM*", /* normal */\r | |
401 | "LAC*", "XOR*", "ADD*", "TAD*",\r | |
402 | "XCT*", "ISZ*", "AND*", "SAD*",\r | |
403 | "JMP*",\r | |
404 | #else\r | |
405 | "CAL I", "DAC I", "JMS I", "DZM I", /* decode only */\r | |
406 | "LAC I", "XOR I", "ADD I", "TAD I",\r | |
407 | "XCT I", "ISZ I", "AND I", "SAD I",\r | |
408 | "JMP I",\r | |
409 | #endif\r | |
410 | \r | |
411 | "LAW", /* LAW */\r | |
412 | \r | |
413 | "LACQ", "LACS", "ABS", "GSM", "LMQ", /* EAE */\r | |
414 | "MUL", "MULS", "DIV", "DIVS",\r | |
415 | "IDIV", "IDIVS", "FRDIV", "FRDIVS",\r | |
416 | "NORM", "NORMS",\r | |
417 | "MUY", "LLK MUY", "DVI", "LLK DVI",\r | |
418 | "NMI", "NMIS", "LRS", "LRSS",\r | |
419 | "LLS", "LLSS", "ALS", "ALSS",\r | |
420 | "EAE-setup", "EAE", /* setup, general */\r | |
421 | \r | |
422 | "CLSF", "IOF", "ION", "CLOF", "CLON", /* standard IO devs */\r | |
423 | "RSF", "RRB", "RCF", "RSA", "RSB",\r | |
424 | "PSF", "PCF", "PSA", "PSB", "PLS",\r | |
425 | "KSF", "KRB", "KCF", "IORS", "IOOS",\r | |
426 | "TSF", "TCF", "TPC", "TLS",\r | |
427 | #if defined (TYPE62) /* Type 62 */\r | |
428 | "LPSF", "LPCF", "LPLD", "LPSE",\r | |
429 | "LSSF", "LSCF", "LSPR",\r | |
430 | #endif\r | |
431 | #if defined (TYPE647) /* Type 647 */\r | |
432 | "LPSF", "LPCB", "LPCD", "LPCD", "LPCD",\r | |
433 | "LPL2", "LPLD", "LPL1",\r | |
434 | "LPEF", "LPCF", "LPCF", "LPCF", "LPCF",\r | |
435 | "LPPB", "LPLS", "LPPS",\r | |
436 | #endif\r | |
437 | #if defined (LP09)\r | |
438 | "LSDF", "LSEF", "LSCF", "LPLD",\r | |
439 | "LIOF", "LION",\r | |
440 | #endif\r | |
441 | #if defined (LP15) /* LP15 */\r | |
442 | "LPSF", "LPPM", "LPP1", "LPDI",\r | |
443 | "LPRS", "LPOS", "LPEI", "LPCD", "LPCF",\r | |
444 | #endif\r | |
445 | #if defined (DRM) /* drum */\r | |
446 | "DRLR", "DRLW", "DRSS", "DRCS",\r | |
447 | "DRSF", "DRSN", "DRCF",\r | |
448 | "DRLCRD", "DRLCWR", "DRLBLK", "DRCONT",\r | |
449 | "DRSF", "DRSOK", "DRCF",\r | |
450 | #endif\r | |
451 | #if defined (RB) /* RB09 */\r | |
452 | "DBCF", "DBRD", "DBLD",\r | |
453 | "DBSF", "DBRS", "DBLW",\r | |
454 | "DBCS", "DBLM", "DBLS",\r | |
455 | #endif\r | |
456 | #if defined (RF) /* RF09 */\r | |
457 | "DSSF", "DSCC", "DSCF",\r | |
458 | "DRBR", "DRAL", "DSFX", "DRAH",\r | |
459 | "DLBR", "DLAL", "DSCN", "DLAH",\r | |
460 | "DLOK", "DSCD", "DSRS",\r | |
461 | "DGHS", "DGSS",\r | |
462 | #endif\r | |
463 | #if defined (RP)\r | |
464 | "DPSF", "DPSA", "DPSJ", "DPSE",\r | |
465 | "DPRSA", "DPOSA", "DPRSB", "DPOSB",\r | |
466 | "DPRM", "DPOM",\r | |
467 | "DPLA", "DPCS", "DPCA", "DPWC",\r | |
468 | "DPLM", "DPEM", "DPSN",\r | |
469 | "DPRU", "DPOU", "DPRA", "DPOA",\r | |
470 | "DPRC", "DPOC", "DPRW", "DPOW",\r | |
471 | "DPCF", "DPLZ", "DPCN", "DPLO", "DPLF",\r | |
472 | #endif\r | |
473 | #if defined (MTA) /* TC59 */\r | |
474 | "MTTR", "MTCR", "MTSF", "MTRC", "MTAF",\r | |
475 | "MTRS", "MTGO", "MTCM", "MTLC",\r | |
476 | #endif\r | |
477 | #if defined (TYPE550) /* Type 550 */\r | |
478 | "MMDF", "MMEF", "MMRD", "MMWR",\r | |
479 | "MMBF", "MMRS", "MMLC", "MMSE",\r | |
480 | #elif defined (TC02) /* TC02/TC15 */\r | |
481 | "DTCA", "DTRA", "DTXA", "DTLA",\r | |
482 | "DTEF", "DTRB", "DTDF",\r | |
483 | #endif\r | |
484 | #if defined (TTY1)\r | |
485 | "KSF1", "KRB1",\r | |
486 | "TSF1", "TCF1", "TLS1", "TCF1!TLS1",\r | |
487 | #endif\r | |
488 | #if defined (PDP7)\r | |
489 | "ITON", "TTS", "SKP7", "CAF",\r | |
490 | "SEM", "EEM", "EMIR", "LEM",\r | |
491 | #endif\r | |
492 | #if defined (PDP9)\r | |
493 | "SKP7", "SEM", "EEM", "LEM",\r | |
494 | "LPDI", "LPEI",\r | |
495 | #endif\r | |
496 | #if defined (PDP15)\r | |
497 | "SPCO", "SKP15", "RES",\r | |
498 | "SBA", "DBA", "EBA",\r | |
499 | "RDMM", "ORMM", "LDMM", "MPLR",\r | |
500 | "ENB", "INH",\r | |
501 | "RDCLK","MPRC", "IPFH",\r | |
502 | "PAX", "PAL", "AAC", "PXA",\r | |
503 | "AXS", "PXL", "PLA", "PLX",\r | |
504 | "CLAC","CLX", "CLLR", "AXR",\r | |
505 | \r | |
506 | "FPT", /* FP15 */\r | |
507 | "ISB", "ESB", /* mem ref */\r | |
508 | "FSB", "URFSB", "UNFSB", "UUFSB",\r | |
509 | "DSB", "URDSB", "UNDSB", "UUDSB",\r | |
510 | "IRS", "ERS",\r | |
511 | "FRS", "URFRS", "UNFRS", "UUFRS",\r | |
512 | "DRS", "URDRS", "UNDRS", "UUDRS",\r | |
513 | "IMP", "EMP",\r | |
514 | "FMP", "URFMP", "UNFMP", "UUFMP",\r | |
515 | "DMP", "URDMP", "UNDMP", "UUDMP",\r | |
516 | "IDV", "EDV",\r | |
517 | "FDV", "URFDV", "UNFDV", "UUFDV",\r | |
518 | "DDV", "URDDV", "UNDDV", "UUDDV",\r | |
519 | "IRD", "ERD",\r | |
520 | "FRD", "URFRD", "UNFRD", "UUFRD",\r | |
521 | "DRD", "URDRD", "UNDRD", "UUDRD",\r | |
522 | "ILD", "ELD",\r | |
523 | "FLD", "UNFLD", "DLD", "UNDLD",\r | |
524 | "IST", "EST",\r | |
525 | "FST", "URFST", "UNFST", "UUFST",\r | |
526 | "DST", "UNDST",\r | |
527 | "ILF", "UNILF", "ELF", "UNELF",\r | |
528 | "FLX", "URFLX", "DLX", "URDLX",\r | |
529 | "ILQ", "ELQ",\r | |
530 | "FLQ", "UNFLQ", "DLQ", "UNDLQ",\r | |
531 | "LJE", "SJE",\r | |
532 | "IAD", "EAD",\r | |
533 | "FAD", "URFAD", "UNFAD", "UUFAD",\r | |
534 | "DAD", "URDAD", "UNDAD", "UUDAD",\r | |
535 | "BZA", "BMA", "BLE", "BPA",\r | |
536 | "BRU", "BNA", "BAC",\r | |
537 | "ISB*", "ESB*", /* indirect */\r | |
538 | "FSB*", "URFSB*", "UNFSB*", "UUFSB*",\r | |
539 | "DSB*", "URDSB*", "UNDSB*", "UUDSB*",\r | |
540 | "IRS*", "ERS*",\r | |
541 | "FRS*", "URFRS*", "UNFRS*", "UUFRS*",\r | |
542 | "DRS*", "URDRS*", "UNDRS*", "UUDRS*",\r | |
543 | "IMP*", "EMP*",\r | |
544 | "FMP*", "URFMP*", "UNFMP*", "UUFMP*",\r | |
545 | "DMP*", "URDMP*", "UNDMP*", "UUDMP*",\r | |
546 | "IDV*", "EDV*",\r | |
547 | "FDV*", "URFDV*", "UNFDV*", "UUFDV*",\r | |
548 | "DDV*", "URDDV*", "UNDDV*", "UUDDV*",\r | |
549 | "IRD*", "ERD",\r | |
550 | "FRD*", "URFRD*", "UNFRD*", "UUFRD*",\r | |
551 | "DRD*", "URDRD*", "UNDRD*", "UUDRD*",\r | |
552 | "ILD*", "ELD",\r | |
553 | "FLD*", "UNFLD*", "DLD*", "UNDLD*",\r | |
554 | "IST*", "EST",\r | |
555 | "FST*", "URFST*", "UNFST*", "UUFST*",\r | |
556 | "DST*", "UNDST*",\r | |
557 | "ILF*", "UNILF*", "ELF*", "UNELF*",\r | |
558 | "FLX*", "URFLX*", "DLX*", "URDLX*",\r | |
559 | "ILQ*", "ELQ*",\r | |
560 | "FLQ*", "UNFLQ*", "DLQ*", "UNDLQ*",\r | |
561 | "LJE*", "SJE*",\r | |
562 | "IAD*", "EAD*",\r | |
563 | "FAD*", "URFAD*", "UNFAD*", "UUFAD*",\r | |
564 | "DAD*", "URDAD*", "UNDAD*", "UUDAD*",\r | |
565 | \r | |
566 | "FLA", "UNFLA", "FXA", "URFXA", /* no operand */\r | |
567 | "SWQ", "UNSWQ", "FZR",\r | |
568 | "FAB", "FNG", "FCM", "FNM",\r | |
569 | #endif\r | |
570 | #if defined (PDP9) || defined (PDP15)\r | |
571 | "MPSK", "MPSNE", "MPCV", "MPEU",\r | |
572 | "MPLD", "MPCNE", "PFSF",\r | |
573 | "TTS", "CAF", "DBK", "DBR",\r | |
574 | "SPI", "RPL", "ISA",\r | |
575 | #endif\r | |
576 | "IOT", /* general */\r | |
577 | \r | |
578 | "NOP", "STL", "RCL", "RCR",\r | |
579 | "CLC", "LAS", "GLK",\r | |
580 | "OPR", "SMA", "SZA", "SZA SMA",\r | |
581 | "SNL", "SNL SMA", "SNL SZA", "SNL SZA SMA",\r | |
582 | "SKP", "SPA", "SNA", "SNA SPA",\r | |
583 | "SZL", "SZL SPA", "SZL SNA", "SZL SZA SPA",\r | |
584 | "RAL", "SMA RAL", "SZA RAL", "SZA SMA RAL",\r | |
585 | "SNL RAL", "SNL SMA RAL", "SNL SZA RAL", "SNL SZA SMA RAL",\r | |
586 | "SKP RAL", "SPA RAL", "SNA RAL", "SNA SPA RAL",\r | |
587 | "SZL RAL", "SZL SPA RAL", "SZL SNA RAL", "SZL SZA SPA RAL",\r | |
588 | "RAR", "SMA RAR", "SZA RAR", "SZA SMA RAR",\r | |
589 | "SNL RAR", "SNL SMA RAR", "SNL SZA RAR", "SNL SZA SMA RAR",\r | |
590 | "SKP RAR", "SPA RAR", "SNA RAR", "SNA SPA RAR",\r | |
591 | "SZL RAR", "SZL SPA RAR", "SZL SNA RAR", "SZL SZA SPA RAR",\r | |
592 | #if defined (PDP15)\r | |
593 | "IAC", "SMA IAC", "SZA IAC", "SZA SMA IAC",\r | |
594 | "SNL IAC", "SNL SMA IAC", "SNL SZA IAC", "SNL SZA SMA IAC",\r | |
595 | "SKP IAC", "SPA IAC", "SNA IAC", "SNA SPA IAC",\r | |
596 | "SZL IAC", "SZL SPA IAC", "SZL SNA IAC", "SZL SZA SPA IAC",\r | |
597 | #else\r | |
598 | "RAL RAR", "SMA RAL RAR", "SZA RAL RAR", "SZA SMA RAL RAR",\r | |
599 | "SNL RAL RAR", "SNL SMA RAL RAR", "SNL SZA RAL RAR", "SNL SZA SMA RAL RAR",\r | |
600 | "SKP RAL RAR", "SPA RAL RAR", "SNA RAL RAR", "SNA SPA RAL RAR",\r | |
601 | "SZL RAL RAR", "SZL SPA RAL RAR", "SZL SNA RAL RAR", "SZL SZA SPA RAL RAR",\r | |
602 | #endif\r | |
603 | "RTWO", "SMA RTWO", "SZA RTWO", "SZA SMA RTWO",\r | |
604 | "SNL RTWO", "SNL SMA RTWO", "SNL SZA RTWO", "SNL SZA SMA RTWO",\r | |
605 | "SKP RTWO", "SPA RTWO", "SNA RTWO", "SNA SPA RTWO",\r | |
606 | "SZL RTWO", "SZL SPA RTWO", "SZL SNA RTWO", "SZL SZA SPA RTWO",\r | |
607 | "RTL", "SMA RTL", "SZA RTL", "SZA SMA RTL",\r | |
608 | "SNL RTL", "SNL SMA RTL", "SNL SZA RTL", "SNL SZA SMA RTL",\r | |
609 | "SKP RTL", "SPA RTL", "SNA RTL", "SNA SPA RTL",\r | |
610 | "SZL RTL", "SZL SPA RTL", "SZL SNA RTL", "SZL SZA SPA RTL",\r | |
611 | "RTR", "SMA RTR", "SZA RTR", "SZA SMA RTR",\r | |
612 | "SNL RTR", "SNL SMA RTR", "SNL SZA RTR", "SNL SZA SMA RTR",\r | |
613 | "SKP RTR", "SPA RTR", "SNA RTR", "SNA SPA RTR",\r | |
614 | "SZL RTR", "SZL SPA RTR", "SZL SNA RTR", "SZL SZA SPA RTR",\r | |
615 | #if defined (PDP15)\r | |
616 | "BSW", "SMA BSW", "SZA BSW", "SZA SMA BSW",\r | |
617 | "SNL BSW", "SNL SMA BSW", "SNL SZA BSW", "SNL SZA SMA BSW",\r | |
618 | "SKP BSW", "SPA BSW", "SNA BSW", "SNA SPA BSW",\r | |
619 | "SZL BSW", "SZL SPA BSW", "SZL SNA BSW", "SZL SZA SPA BSW",\r | |
620 | #else\r | |
621 | "RTL RTR", "SMA RTL RTR", "SZA RTL RTR", "SZA SMA RTL RTR",\r | |
622 | "SNL RTL RTR", "SNL SMA RTL RTR", "SNL SZA RTL RTR", "SNL SZA SMA RTL RTR",\r | |
623 | "SKP RTL RTR", "SPA RTL RTR", "SNA RTL RTR", "SNA SPA RTL RTR",\r | |
624 | "SZL RTL RTR", "SZL SPA RTL RTR", "SZL SNA RTL RTR", "SZL SZA SPA RTL RTR",\r | |
625 | #endif\r | |
626 | \r | |
627 | "LLK", "CLQ", "LSN", "OACQ", "ECLA", /* encode only masks */\r | |
628 | "CMQ", "OMQ", "OSC", \r | |
629 | "CLA", "CLL", "CML", "CMA",\r | |
630 | "OAS", "HLT",\r | |
631 | NULL\r | |
632 | };\r | |
633 | \r | |
634 | static const int32 opc_val[] = {\r | |
635 | 0000000+I_MRF, 0040000+I_MRF, 0100000+I_MRF, 0140000+I_MRF,\r | |
636 | 0200000+I_MRF, 0240000+I_MRF, 0300000+I_MRF, 0340000+I_MRF,\r | |
637 | 0400000+I_MRF, 0440000+I_MRF, 0500000+I_MRF, 0540000+I_MRF,\r | |
638 | 0600000+I_MRF,\r | |
639 | 0020000+I_MRF, 0060000+I_MRF, 0120000+I_MRF, 0160000+I_MRF,\r | |
640 | 0220000+I_MRF, 0260000+I_MRF, 0320000+I_MRF, 0360000+I_MRF,\r | |
641 | 0420000+I_MRF, 0460000+I_MRF, 0520000+I_MRF, 0560000+I_MRF,\r | |
642 | 0620000+I_MRF,\r | |
643 | \r | |
644 | 0760000+I_LAW,\r | |
645 | \r | |
646 | 0641002+I_NPN, 0641001+I_NPN, 0644000+I_NPN, 0664000+I_NPN, 0652000+I_NPN,\r | |
647 | 0653100+MD(022), 0657100+MD(022), 0640300+MD(023), 0644300+MD(023),\r | |
648 | 0653300+MD(023), 0657300+MD(023), 0650300+MD(023), 0654300+MD(023),\r | |
649 | 0640400+MD(044), 0660400+MD(044),\r | |
650 | 0640100+I_ESH, 0660100+I_ESH, 0640300+I_ESH, 0660300+I_ESH,\r | |
651 | 0640400+I_ESH, 0660400+I_ESH, 0640500+I_ESH, 0660500+I_ESH,\r | |
652 | 0640600+I_ESH, 0660600+I_ESH, 0640700+I_ESH, 0660700+I_ESH,\r | |
653 | 0640000+I_EST, 0640000+I_IOT, \r | |
654 | \r | |
655 | 0700001+I_NPI, 0700002+I_NPI, 0700042+I_NPI, 0700004+I_NPI, 0700044+I_NPI,\r | |
656 | 0700101+I_NPI, 0700112+I_NPN, 0700102+I_NPI, 0700104+I_NPI, 0700144+I_NPI,\r | |
657 | 0700201+I_NPI, 0700202+I_NPI, 0700204+I_NPI, 0700244+I_NPI, 0700206+I_NPI,\r | |
658 | 0700301+I_NPI, 0700312+I_NPN, 0700302+I_NPI, 0700314+I_NPN, 0700304+I_NPI,\r | |
659 | 0700401+I_NPI, 0700402+I_NPI, 0700404+I_NPI, 0700406+I_NPI,\r | |
660 | #if defined (TYPE62)\r | |
661 | 0706501+I_NPI, 0706502+I_NPI, 0706542+I_NPI, 0706506+I_NPI,\r | |
662 | 0706601+I_NPI, 0706602+I_NPI, 0706606+I_NPI,\r | |
663 | #endif\r | |
664 | #if defined (TYPE647)\r | |
665 | 0706501+I_NPI, 0706502+I_NPI, 0706522+I_NPI, 0706542+I_NPI, 0706562+I_NPI,\r | |
666 | 0706526+I_NPI, 0706546+I_NPI, 0706566+I_NPI,\r | |
667 | 0706601+I_NPI, 0706602+I_NPI, 0706622+I_NPI, 0706642+I_NPI, 0706662+I_NPI, \r | |
668 | 0706606+I_NPI, 0706626+I_NPI, 0706646+I_NPI,\r | |
669 | #endif\r | |
670 | #if defined (LP09)\r | |
671 | 0706601+I_NPI, 0706621+I_NPI, 0706602+I_NPI, 0706622+I_NPI,\r | |
672 | 0706604+I_NPI, 0706644+I_NPI,\r | |
673 | #endif\r | |
674 | #if defined (LP15)\r | |
675 | 0706501+I_NPI, 0706521+I_NPI, 0706541+I_NPI, 0706561+I_NPI,\r | |
676 | 0706552+I_NPN, 0706542+I_NPI, 0706544+I_NPI, 0706621+I_NPI, 0706641+I_NPI,\r | |
677 | #endif\r | |
678 | #if defined (DRM)\r | |
679 | 0706006+I_NPI, 0706046+I_NPI, 0706106+I_NPI, 0706204+I_NPI,\r | |
680 | 0706101+I_NPI, 0706201+I_NPI, 0706102+I_NPI,\r | |
681 | 0706006+I_NPI, 0706046+I_NPI, 0706106+I_NPI, 0706204+I_NPI,\r | |
682 | 0706101+I_NPI, 0706201+I_NPI, 0706102+I_NPI,\r | |
683 | #endif\r | |
684 | #if defined (RB)\r | |
685 | 0707101+I_NPI, 0707112+I_NPN, 0707104+I_NPI,\r | |
686 | 0707121+I_NPI, 0707132+I_NPN, 0707124+I_NPI,\r | |
687 | 0707141+I_NPI, 0707142+I_NPI, 0707144+I_NPI,\r | |
688 | #endif\r | |
689 | #if defined (RF)\r | |
690 | 0707001+I_NPI, 0707021+I_NPI, 0707041+I_NPI,\r | |
691 | 0707002+I_NPI, 0707022+I_NPI, 0707042+I_NPI, 0707062+I_NPI,\r | |
692 | 0707004+I_NPI, 0707024+I_NPI, 0707044+I_NPI, 0707064+I_NPI,\r | |
693 | 0707202+I_NPI, 0707242+I_NPI, 0707262+I_NPI,\r | |
694 | 0707204+I_NPI, 0707224+I_NPI,\r | |
695 | #endif\r | |
696 | #if defined (RP)\r | |
697 | 0706301+I_NPI, 0706321+I_NPI, 0706341+I_NPI, 0706361+I_NPI,\r | |
698 | 0706312+I_NPN, 0706302+I_NPI, 0706332+I_NPN, 0706322+I_NPI, \r | |
699 | 0706352+I_NPN, 0706342+I_NPI,\r | |
700 | 0706304+I_NPI, 0706324+I_NPI, 0706344+I_NPI, 0706364+I_NPI,\r | |
701 | 0706411+I_NPN, 0706401+I_NPI, 0706421+I_NPI,\r | |
702 | 0706412+I_NPN, 0706402+I_NPI, 0706432+I_NPN, 0706422+I_NPI, \r | |
703 | 0706452+I_NPN, 0706442+I_NPI, 0706472+I_NPN, 0706462+I_NPI, \r | |
704 | 0706404+I_NPI, 0706424+I_NPI, 0706454+I_NPN, 0706444+I_NPI, 0706464+I_NPI,\r | |
705 | #endif \r | |
706 | #if defined (MTA)\r | |
707 | 0707301+I_NPI, 0707321+I_NPI, 0707341+I_NPI, 0707312+I_NPN, 0707322+I_NPI,\r | |
708 | 0707352+I_NPN, 0707304+I_NPI, 0707324+I_NPI, 0707326+I_NPI, \r | |
709 | #endif\r | |
710 | #if defined (TYPE550) /* Type 550 */\r | |
711 | 0707501+I_NPI, 0707541+I_NPI, 0707512+I_NPN, 0707504+I_NPI,\r | |
712 | 0707601+I_NPI, 0707612+I_NPN, 0707604+I_NPI, 0707644+I_NPI,\r | |
713 | #elif defined (TC02) /* TC02/TC15 */\r | |
714 | 0707541+I_NPI, 0707552+I_NPN, 0707544+I_NPI, 0707545+I_NPI,\r | |
715 | 0707561+I_NPI, 0707572+I_NPN, 0707601+I_NPI,\r | |
716 | #endif\r | |
717 | #if defined (TTY1)\r | |
718 | 0704101+I_NPI, 0704112+I_NPN,\r | |
719 | 0704001+I_NPI, 0704002+I_NPI, 0704004+I_NPI, 0704006+I_NPI,\r | |
720 | #endif\r | |
721 | #if defined (PDP7)\r | |
722 | 0703201+I_NPI, 0703301+I_NPI, 0703341+I_NPI, 0703302+I_NPI,\r | |
723 | 0707701+I_NPI, 0707702+I_NPI, 0707742+I_NPI, 0707704+I_NPI,\r | |
724 | #endif\r | |
725 | #if defined (PDP9)\r | |
726 | 0703341+I_NPI, 0707701+I_NPI, 0707702+I_NPI, 0707704+I_NPI,\r | |
727 | 0706504+I_NPI, 0706604+I_NPI,\r | |
728 | #endif\r | |
729 | #if defined (PDP15)\r | |
730 | 0703341+I_NPI, 0707741+I_NPI, 0707742+I_NPI,\r | |
731 | 0707761+I_NPI, 0707762+I_NPI, 0707764+I_NPI,\r | |
732 | 0700032+I_NPN, 0700022+I_NPI, 0700024+I_NPI, 0701724+I_NPI,\r | |
733 | 0705521+I_NPI, 0705522+I_NPI,\r | |
734 | 0701772+I_NPN, 0701762+I_NPI, 0701764+I_NPI,\r | |
735 | 0721000+I_XR, 0722000+I_XR, 0723000+I_XR9, 0724000+I_XR,\r | |
736 | 0725000+I_XR9, 0726000+I_XR, 0730000+I_XR, 0731000+I_XR,\r | |
737 | 0734000+I_XR, 0735000+I_XR, 0736000+I_XR, 0737000+I_XR9,\r | |
738 | \r | |
739 | 0710314+I_FPN,\r | |
740 | 0710400+I_FPM, 0710500+I_FPM,\r | |
741 | 0710440+I_FPM, 0710450+I_FPM, 0710460+I_FPM, 0710470+I_FPM,\r | |
742 | 0710540+I_FPM, 0710550+I_FPM, 0710560+I_FPM, 0710570+I_FPM,\r | |
743 | 0711000+I_FPM, 0711100+I_FPM,\r | |
744 | 0711040+I_FPM, 0711050+I_FPM, 0711060+I_FPM, 0711070+I_FPM,\r | |
745 | 0711140+I_FPM, 0711150+I_FPM, 0711160+I_FPM, 0711170+I_FPM,\r | |
746 | 0711400+I_FPM, 0711500+I_FPM,\r | |
747 | 0711440+I_FPM, 0711450+I_FPM, 0711460+I_FPM, 0711470+I_FPM,\r | |
748 | 0711540+I_FPM, 0711550+I_FPM, 0711560+I_FPM, 0711570+I_FPM,\r | |
749 | 0712000+I_FPM, 0712100+I_FPM,\r | |
750 | 0712040+I_FPM, 0712050+I_FPM, 0712060+I_FPM, 0712070+I_FPM,\r | |
751 | 0712140+I_FPM, 0712150+I_FPM, 0712160+I_FPM, 0712170+I_FPM,\r | |
752 | 0712400+I_FPM, 0712500+I_FPM,\r | |
753 | 0712440+I_FPM, 0712450+I_FPM, 0712460+I_FPM, 0712470+I_FPM,\r | |
754 | 0712540+I_FPM, 0712550+I_FPM, 0712560+I_FPM, 0712570+I_FPM,\r | |
755 | 0713000+I_FPM, 0713100+I_FPM,\r | |
756 | 0713050+I_FPM, 0713070+I_FPM, 0713150+I_FPM, 0713170+I_FPM,\r | |
757 | 0713600+I_FPM, 0713700+I_FPM,\r | |
758 | 0713640+I_FPM, 0713650+I_FPM, 0713660+I_FPM, 0713670+I_FPM,\r | |
759 | 0713750+I_FPM, 0713770+I_FPM,\r | |
760 | 0714010+I_FPM, 0714030+I_FPM, 0714110+I_FPM, 0714130+I_FPM,\r | |
761 | 0714460+I_FPM, 0714470+I_FPM, 0714560+I_FPM, 0714570+I_FPM,\r | |
762 | 0715000+I_FPM, 0715100+I_FPM,\r | |
763 | 0715050+I_FPM, 0715070+I_FPM, 0715150+I_FPM, 0715170+I_FPM,\r | |
764 | 0715400+I_FPM, 0715600+I_FPM,\r | |
765 | 0716000+I_FPM, 0716100+I_FPM,\r | |
766 | 0716040+I_FPM, 0716050+I_FPM, 0716060+I_FPM, 0716070+I_FPM,\r | |
767 | 0716140+I_FPM, 0716150+I_FPM, 0716160+I_FPM, 0716170+I_FPM,\r | |
768 | 0716601+I_FPM, 0716602+I_FPM, 0716603+I_FPM,\r | |
769 | 0716604+I_FPM, 0716606+I_FPM, 0716610+I_FPM, 0716620+I_FPM,\r | |
770 | 0710400+I_FPI, 0710500+I_FPI, /* indirect */\r | |
771 | 0710440+I_FPI, 0710450+I_FPI, 0710460+I_FPI, 0710470+I_FPI,\r | |
772 | 0710540+I_FPI, 0710550+I_FPI, 0710560+I_FPI, 0710570+I_FPI,\r | |
773 | 0711000+I_FPI, 0711100+I_FPI,\r | |
774 | 0711040+I_FPI, 0711050+I_FPI, 0711060+I_FPI, 0711070+I_FPI,\r | |
775 | 0711140+I_FPI, 0711150+I_FPI, 0711160+I_FPI, 0711170+I_FPI,\r | |
776 | 0711400+I_FPI, 0711500+I_FPI,\r | |
777 | 0711440+I_FPI, 0711450+I_FPI, 0711460+I_FPI, 0711470+I_FPI,\r | |
778 | 0711540+I_FPI, 0711550+I_FPI, 0711560+I_FPI, 0711570+I_FPI,\r | |
779 | 0712000+I_FPI, 0712100+I_FPI,\r | |
780 | 0712040+I_FPI, 0712050+I_FPI, 0712060+I_FPI, 0712070+I_FPI,\r | |
781 | 0712140+I_FPI, 0712150+I_FPI, 0712160+I_FPI, 0712170+I_FPI,\r | |
782 | 0712400+I_FPI, 0712500+I_FPI,\r | |
783 | 0712440+I_FPI, 0712450+I_FPI, 0712460+I_FPI, 0712470+I_FPI,\r | |
784 | 0712540+I_FPI, 0712550+I_FPI, 0712560+I_FPI, 0712570+I_FPI,\r | |
785 | 0713000+I_FPI, 0713100+I_FPI,\r | |
786 | 0713050+I_FPI, 0713070+I_FPI, 0713150+I_FPI, 0713170+I_FPI,\r | |
787 | 0713600+I_FPI, 0713700+I_FPI,\r | |
788 | 0713640+I_FPI, 0713650+I_FPI, 0713660+I_FPI, 0713670+I_FPI,\r | |
789 | 0713750+I_FPI, 0713770+I_FPI,\r | |
790 | 0714010+I_FPI, 0714030+I_FPI, 0714110+I_FPI, 0714130+I_FPI,\r | |
791 | 0714460+I_FPI, 0714470+I_FPI, 0714560+I_FPI, 0714570+I_FPI,\r | |
792 | 0715000+I_FPI, 0715100+I_FPI,\r | |
793 | 0715050+I_FPI, 0715070+I_FPI, 0715150+I_FPI, 0715170+I_FPI,\r | |
794 | 0715400+I_FPI, 0715600+I_FPI,\r | |
795 | 0716000+I_FPI, 0716100+I_FPI,\r | |
796 | 0716040+I_FPI, 0716050+I_FPI, 0716060+I_FPI, 0716070+I_FPI,\r | |
797 | 0716140+I_FPI, 0716150+I_FPI, 0716160+I_FPI, 0716170+I_FPI,\r | |
798 | 0714210+I_FPN, 0714230+I_FPN, 0714660+I_FPN, 0714670+I_FPN,\r | |
799 | 0715250+I_FPN, 0715270+I_FPN, 0711200+I_FPN,\r | |
800 | 0713271+I_FPN, 0713272+I_FPN, 0713273+I_FPN, 0713250+I_FPN,\r | |
801 | #endif\r | |
802 | #if defined (PDP9) || defined (PDP15)\r | |
803 | 0701701+I_NPI, 0701741+I_NPI, 0701702+I_NPI, 0701742+I_NPI,\r | |
804 | 0701704+I_NPI, 0701744+I_NPI, 0703201+I_NPI,\r | |
805 | 0703301+I_NPI, 0703302+I_NPI, 0703304+I_NPI, 0703344+I_NPI,\r | |
806 | 0705501+I_NPI, 0705512+I_NPN, 0705504+I_NPI,\r | |
807 | #endif\r | |
808 | 0700000+I_IOT,\r | |
809 | \r | |
810 | 0740000+I_NPN, 0744002+I_NPN, 0744010+I_NPN, 0744020+I_NPN,\r | |
811 | 0750001+I_NPN, 0750004+I_NPN, 0750010+I_NPN,\r | |
812 | 0740000+I_OPR, 0740100+I_OPR, 0740200+I_OPR, 0740300+I_OPR,\r | |
813 | 0740400+I_OPR, 0740500+I_OPR, 0740600+I_OPR, 0740700+I_OPR,\r | |
814 | 0741000+I_OPR, 0741100+I_OPR, 0741200+I_OPR, 0741300+I_OPR,\r | |
815 | 0741400+I_OPR, 0741500+I_OPR, 0741600+I_OPR, 0741700+I_OPR,\r | |
816 | 0740010+I_OPR, 0740110+I_OPR, 0740210+I_OPR, 0740310+I_OPR,\r | |
817 | 0740410+I_OPR, 0740510+I_OPR, 0740610+I_OPR, 0740710+I_OPR,\r | |
818 | 0741010+I_OPR, 0741110+I_OPR, 0741210+I_OPR, 0741310+I_OPR,\r | |
819 | 0741410+I_OPR, 0741510+I_OPR, 0741610+I_OPR, 0741710+I_OPR,\r | |
820 | 0740020+I_OPR, 0740120+I_OPR, 0740220+I_OPR, 0740320+I_OPR,\r | |
821 | 0740420+I_OPR, 0740520+I_OPR, 0740620+I_OPR, 0740720+I_OPR,\r | |
822 | 0741020+I_OPR, 0741120+I_OPR, 0741220+I_OPR, 0741320+I_OPR,\r | |
823 | 0741420+I_OPR, 0741520+I_OPR, 0741620+I_OPR, 0741720+I_OPR,\r | |
824 | 0740030+I_OPR, 0740130+I_OPR, 0740230+I_OPR, 0740330+I_OPR,\r | |
825 | 0740430+I_OPR, 0740530+I_OPR, 0740630+I_OPR, 0740730+I_OPR,\r | |
826 | 0741030+I_OPR, 0741130+I_OPR, 0741230+I_OPR, 0741330+I_OPR,\r | |
827 | 0741430+I_OPR, 0741530+I_OPR, 0741630+I_OPR, 0741730+I_OPR,\r | |
828 | 0742000+I_OPR, 0742100+I_OPR, 0742200+I_OPR, 0742300+I_OPR,\r | |
829 | 0742400+I_OPR, 0742500+I_OPR, 0742600+I_OPR, 0742700+I_OPR,\r | |
830 | 0743000+I_OPR, 0743100+I_OPR, 0743200+I_OPR, 0743300+I_OPR,\r | |
831 | 0743400+I_OPR, 0743500+I_OPR, 0743600+I_OPR, 0743700+I_OPR,\r | |
832 | 0742010+I_OPR, 0742110+I_OPR, 0742210+I_OPR, 0742310+I_OPR,\r | |
833 | 0742410+I_OPR, 0742510+I_OPR, 0742610+I_OPR, 0742710+I_OPR,\r | |
834 | 0743010+I_OPR, 0743110+I_OPR, 0743210+I_OPR, 0743310+I_OPR,\r | |
835 | 0743410+I_OPR, 0743510+I_OPR, 0743610+I_OPR, 0743710+I_OPR,\r | |
836 | 0742020+I_OPR, 0742120+I_OPR, 0742220+I_OPR, 0742320+I_OPR,\r | |
837 | 0742420+I_OPR, 0742520+I_OPR, 0742620+I_OPR, 0742720+I_OPR,\r | |
838 | 0743020+I_OPR, 0743120+I_OPR, 0743220+I_OPR, 0743320+I_OPR,\r | |
839 | 0743420+I_OPR, 0743520+I_OPR, 0743620+I_OPR, 0743720+I_OPR,\r | |
840 | 0742030+I_OPR, 0742130+I_OPR, 0742230+I_OPR, 0742330+I_OPR,\r | |
841 | 0742430+I_OPR, 0742530+I_OPR, 0742630+I_OPR, 0742730+I_OPR,\r | |
842 | 0743030+I_OPR, 0743130+I_OPR, 0743230+I_OPR, 0743330+I_OPR,\r | |
843 | 0743430+I_OPR, 0743530+I_OPR, 0743630+I_OPR, 0743730+I_OPR,\r | |
844 | \r | |
845 | 0660000+I_EST, 0650000+I_EST, 0644000+I_EST, 0642000+I_EST, 0641000+I_EST,\r | |
846 | 0640004+I_EST, 0640002+I_EST, 0640001+I_EST,\r | |
847 | 0750000+I_OPR, 0744000+I_OPR, 0740002+I_OPR, 0740001+I_OPR,\r | |
848 | 0740004+I_OPR, 0740040+I_OPR,\r | |
849 | -1\r | |
850 | };\r | |
851 | \r | |
852 | /* Operate or EAE decode\r | |
853 | \r | |
854 | Inputs:\r | |
855 | *of = output stream\r | |
856 | inst = mask bits\r | |
857 | class = instruction class code\r | |
858 | sp = space needed?\r | |
859 | Outputs:\r | |
860 | status = space needed?\r | |
861 | */\r | |
862 | \r | |
863 | int32 fprint_opr (FILE *of, int32 inst, int32 class, int32 sp)\r | |
864 | {\r | |
865 | int32 i, j;\r | |
866 | \r | |
867 | for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */\r | |
868 | j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */\r | |
869 | if ((j == class) && (opc_val[i] & inst)) { /* same class? */\r | |
870 | inst = inst & ~opc_val[i]; /* mask bit set? */\r | |
871 | fprintf (of, (sp? " %s": "%s"), opcode[i]);\r | |
872 | sp = 1;\r | |
873 | }\r | |
874 | }\r | |
875 | return sp;\r | |
876 | }\r | |
877 | \r | |
878 | static int32 rar (int32 c)\r | |
879 | {\r | |
880 | c = c & 077;\r | |
881 | return (c >> 1) | (c << 5);\r | |
882 | }\r | |
883 | \r | |
884 | /* Symbolic decode\r | |
885 | \r | |
886 | Inputs:\r | |
887 | *of = output stream\r | |
888 | addr = current PC\r | |
889 | *val = pointer to values\r | |
890 | *uptr = pointer to unit\r | |
891 | sw = switches\r | |
892 | Outputs:\r | |
893 | return = status code\r | |
894 | */\r | |
895 | \r | |
896 | #define FMTASC(x) (((x) < 040)? "<%03o>": "%c"), (x)\r | |
897 | #define SIXTOASC(x) (((x) >= 040)? (x): ((x) + 0100))\r | |
898 | \r | |
899 | t_stat fprint_sym (FILE *of, t_addr addr, t_value *val,\r | |
900 | UNIT *uptr, int32 sw)\r | |
901 | {\r | |
902 | int32 cflag, i, j, k, sp, inst, disp, ma;\r | |
903 | \r | |
904 | inst = val[0];\r | |
905 | cflag = (uptr == NULL) || (uptr == &cpu_unit);\r | |
906 | if (sw & SWMASK ('A')) { /* ASCII? */\r | |
907 | if (inst > 0377) return SCPE_ARG;\r | |
908 | fprintf (of, FMTASC (inst & 0177));\r | |
909 | return SCPE_OK;\r | |
910 | }\r | |
911 | if (sw & SWMASK ('C')) { /* character? */\r | |
912 | fprintf (of, "%c", SIXTOASC ((inst >> 12) & 077));\r | |
913 | fprintf (of, "%c", SIXTOASC ((inst >> 6) & 077));\r | |
914 | fprintf (of, "%c", SIXTOASC (inst & 077));\r | |
915 | return SCPE_OK;\r | |
916 | }\r | |
917 | #if defined (PDP4) || defined (PDP7)\r | |
918 | if (sw & SWMASK ('F')) { /* FIODEC? */\r | |
919 | fprintf (of, "%c", fio_to_asc[(inst >> 12) & 077]);\r | |
920 | fprintf (of, "%c", fio_to_asc[(inst >> 6) & 077]);\r | |
921 | fprintf (of, "%c", fio_to_asc[inst & 077]);\r | |
922 | return SCPE_OK;\r | |
923 | }\r | |
924 | if (sw & SWMASK ('B')) { /* Baudot? */\r | |
925 | fprintf (of, "%c", baud_to_asc[rar (inst >> 12) & 077]);\r | |
926 | fprintf (of, "%c", baud_to_asc[rar (inst >> 6) & 077]);\r | |
927 | fprintf (of, "%c", baud_to_asc[rar (inst) & 077]);\r | |
928 | return SCPE_OK;\r | |
929 | }\r | |
930 | #endif\r | |
931 | #if defined (PDP15)\r | |
932 | if (sw & SWMASK ('P')) { /* packed ASCII? */\r | |
933 | i = val[1];\r | |
934 | fprintf (of, FMTASC ((inst >> 11) & 0177));\r | |
935 | fprintf (of, FMTASC ((inst >> 4) & 0177));\r | |
936 | fprintf (of, FMTASC (((inst << 3) | (i >> 15)) & 0177));\r | |
937 | fprintf (of, FMTASC ((i >> 8) & 0177));\r | |
938 | fprintf (of, FMTASC ((i >> 1) & 0177));\r | |
939 | return -1;\r | |
940 | }\r | |
941 | #endif\r | |
942 | if (!(sw & SWMASK ('M'))) return SCPE_ARG;\r | |
943 | \r | |
944 | /* Instruction decode */\r | |
945 | \r | |
946 | for (i = 0; opc_val[i] >= 0; i++) { /* loop thru ops */\r | |
947 | j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */\r | |
948 | if ((opc_val[i] & DMASK) == (inst & masks[j])) { /* match? */\r | |
949 | \r | |
950 | switch (j) { /* case on class */\r | |
951 | \r | |
952 | case I_V_NPN: /* no operands */\r | |
953 | case I_V_XR: /* index no opers */\r | |
954 | fprintf (of, "%s", opcode[i]); /* opcode */\r | |
955 | break;\r | |
956 | \r | |
957 | case I_V_NPI: /* IOT no operand */\r | |
958 | fprintf (of, "%s", opcode[i]); /* opcode */\r | |
959 | if (inst & 010) fprintf (of, " +10");\r | |
960 | break;\r | |
961 | \r | |
962 | case I_V_IOT: /* IOT or EAE */\r | |
963 | fprintf (of, "%s %-o", opcode[i], inst & 037777);\r | |
964 | break;\r | |
965 | \r | |
966 | case I_V_MRF: /* mem ref */\r | |
967 | #if defined (PDP15)\r | |
968 | if (memm) {\r | |
969 | disp = inst & B_DAMASK; \r | |
970 | ma = (addr & (AMASK & ~B_DAMASK)) | disp;\r | |
971 | }\r | |
972 | else {\r | |
973 | disp = inst & P_DAMASK;\r | |
974 | ma = (addr & (AMASK & ~P_DAMASK)) | disp;\r | |
975 | }\r | |
976 | fprintf (of, "%s %-o", opcode[i], (cflag? ma & AMASK: disp));\r | |
977 | if (!memm && (inst & I_IDX)) fprintf (of, ",X");\r | |
978 | #else\r | |
979 | disp = inst & B_DAMASK;\r | |
980 | ma = (addr & (AMASK & ~B_DAMASK)) | disp;\r | |
981 | fprintf (of, "%s %-o", opcode[i], (cflag? ma & AMASK: disp));\r | |
982 | #endif\r | |
983 | break;\r | |
984 | \r | |
985 | case I_V_OPR: /* operate */\r | |
986 | if (sp = (inst & 03730)) fprintf (of, "%s", opcode[i]);\r | |
987 | fprint_opr (of, inst & 014047, I_V_OPR, sp);\r | |
988 | break;\r | |
989 | \r | |
990 | case I_V_LAW: /* LAW */\r | |
991 | fprintf (of, "%s %-o", opcode[i], inst & 017777);\r | |
992 | break;\r | |
993 | \r | |
994 | case I_V_XR9: /* index with lit */\r | |
995 | disp = inst & 0777;\r | |
996 | if (disp & 0400) fprintf (of, "%s -%-o", opcode[i], 01000 - disp);\r | |
997 | else fprintf (of, "%s %-o", opcode[i], disp);\r | |
998 | break;\r | |
999 | \r | |
1000 | case I_V_EST: /* EAE setup */\r | |
1001 | fprint_opr (of, inst & 037007, I_V_EST, 0);\r | |
1002 | break;\r | |
1003 | \r | |
1004 | case I_V_ESH: /* EAE shift */\r | |
1005 | sp = fprint_opr (of, inst & 017000, I_V_EST, 0);\r | |
1006 | fprintf (of, (sp? " %s %-o": "%s %-o"), opcode[i], inst & 077);\r | |
1007 | break;\r | |
1008 | \r | |
1009 | case I_V_EMD: /* EAE mul-div */\r | |
1010 | disp = inst & 077; /* get actual val */\r | |
1011 | k = (opc_val[i] >> I_V_DC) & 077; /* get default val */\r | |
1012 | if (disp == k) fprintf (of, "%s", opcode[i]);\r | |
1013 | else if (disp < k) fprintf (of, "%s -%-o", opcode[i], k - disp);\r | |
1014 | else fprintf (of, "%s +%-o", opcode[i], disp - k);\r | |
1015 | break;\r | |
1016 | \r | |
1017 | case I_V_FPM: case I_V_FPI: /* FP15 mem ref */\r | |
1018 | fprintf (of, "%s", opcode[i]);\r | |
1019 | if (val[1] & SIGN) fputc ('*', of);\r | |
1020 | fprintf (of, " %-o", val[1] & ~SIGN);\r | |
1021 | return -1;\r | |
1022 | \r | |
1023 | case I_V_FPN: /* FP15 no operand */\r | |
1024 | fprintf (of, "%s", opcode[i]);\r | |
1025 | return -1;\r | |
1026 | } /* end case */\r | |
1027 | return SCPE_OK;\r | |
1028 | } /* end if */\r | |
1029 | } /* end for */\r | |
1030 | return SCPE_ARG;\r | |
1031 | }\r | |
1032 | \r | |
1033 | /* Get 18b signed number\r | |
1034 | \r | |
1035 | Inputs:\r | |
1036 | *cptr = pointer to input string\r | |
1037 | *sign = pointer to sign\r | |
1038 | *status = pointer to error status\r | |
1039 | Outputs:\r | |
1040 | val = output value\r | |
1041 | */\r | |
1042 | \r | |
1043 | t_value get_sint (char *cptr, int32 *sign, t_stat *status)\r | |
1044 | {\r | |
1045 | *sign = 0;\r | |
1046 | if (*cptr == '+') {\r | |
1047 | *sign = 1;\r | |
1048 | cptr++;\r | |
1049 | }\r | |
1050 | else if (*cptr == '-') {\r | |
1051 | *sign = -1;\r | |
1052 | cptr++;\r | |
1053 | }\r | |
1054 | return get_uint (cptr, 8, 0777777, status);\r | |
1055 | }\r | |
1056 | \r | |
1057 | /* Symbolic input\r | |
1058 | \r | |
1059 | Inputs:\r | |
1060 | *cptr = pointer to input string\r | |
1061 | addr = current PC\r | |
1062 | uptr = pointer to unit\r | |
1063 | *val = pointer to output values\r | |
1064 | sw = switches\r | |
1065 | Outputs:\r | |
1066 | status = error status\r | |
1067 | */\r | |
1068 | \r | |
1069 | t_stat parse_sym (char *cptr, t_addr addr, UNIT *uptr, t_value *val, int32 sw)\r | |
1070 | {\r | |
1071 | int32 cflag, d, i, j, k, sign, damask, epcmask;\r | |
1072 | t_stat r, sta = SCPE_OK;\r | |
1073 | char gbuf[CBUFSIZE];\r | |
1074 | \r | |
1075 | cflag = (uptr == NULL) || (uptr == &cpu_unit);\r | |
1076 | while (isspace (*cptr)) cptr++;\r | |
1077 | for (i = 1; (i < 5) && (cptr[i] != 0); i++)\r | |
1078 | if (cptr[i] == 0) for (j = i + 1; j <= 5; j++) cptr[j] = 0;\r | |
1079 | if ((sw & SWMASK ('A')) || ((*cptr == '\'') && cptr++)) { /* ASCII char? */\r | |
1080 | if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */\r | |
1081 | val[0] = (t_value) cptr[0] | 0200;\r | |
1082 | return SCPE_OK;\r | |
1083 | }\r | |
1084 | if ((sw & SWMASK ('C')) || ((*cptr == '"') && cptr++)) { /* sixbit string? */\r | |
1085 | if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */\r | |
1086 | val[0] = (((t_value) cptr[0] & 077) << 12) |\r | |
1087 | (((t_value) cptr[1] & 077) << 6) |\r | |
1088 | ((t_value) cptr[2] & 077);\r | |
1089 | return SCPE_OK;\r | |
1090 | }\r | |
1091 | #if defined (PDP15)\r | |
1092 | if ((sw & SWMASK ('P')) || ((*cptr == '#') && cptr++)) { /* packed string? */\r | |
1093 | if (cptr[0] == 0) return SCPE_ARG; /* must have 1 char */\r | |
1094 | val[0] = (((t_value) cptr[0] & 0177) << 11) |\r | |
1095 | (((t_value) cptr[1] & 0177) << 4) |\r | |
1096 | (((t_value) cptr[2] & 0170) >> 3);\r | |
1097 | val[1] = (((t_value) cptr[2] & 0007) << 15) |\r | |
1098 | (((t_value) cptr[3] & 0177) << 8) |\r | |
1099 | (((t_value) cptr[4] & 0177) << 1);\r | |
1100 | return -1;\r | |
1101 | }\r | |
1102 | #endif\r | |
1103 | \r | |
1104 | cptr = get_glyph (cptr, gbuf, 0); /* get opcode */\r | |
1105 | for (i = 0; (opcode[i] != NULL) && (strcmp (opcode[i], gbuf) != 0) ; i++) ;\r | |
1106 | if (opcode[i] == NULL) return SCPE_ARG;\r | |
1107 | val[0] = opc_val[i] & DMASK; /* get value */\r | |
1108 | j = (opc_val[i] >> I_V_FL) & I_M_FL; /* get class */\r | |
1109 | \r | |
1110 | switch (j) { /* case on class */\r | |
1111 | \r | |
1112 | case I_V_XR: /* index */\r | |
1113 | break;\r | |
1114 | \r | |
1115 | case I_V_XR9: /* index literal */\r | |
1116 | cptr = get_glyph (cptr, gbuf, 0); /* get next field */\r | |
1117 | d = get_sint (gbuf, &sign, &r);\r | |
1118 | if (r != SCPE_OK) return SCPE_ARG;\r | |
1119 | if (((sign >= 0) && (d > 0377)) || ((sign < 0) && (d > 0400)))\r | |
1120 | return SCPE_ARG;\r | |
1121 | val[0] = val[0] | ((sign >= 0)? d: (01000 - d));\r | |
1122 | break;\r | |
1123 | \r | |
1124 | case I_V_LAW: /* law */\r | |
1125 | cptr = get_glyph (cptr, gbuf, 0); /* get next field */\r | |
1126 | d = get_uint (gbuf, 8, 017777, &r);\r | |
1127 | if (r != SCPE_OK) return SCPE_ARG;\r | |
1128 | val[0] = val[0] | d;\r | |
1129 | break;\r | |
1130 | \r | |
1131 | case I_V_MRF: /* mem ref */\r | |
1132 | #if defined (PDP15)\r | |
1133 | if (memm) damask = B_DAMASK;\r | |
1134 | else damask = P_DAMASK;\r | |
1135 | cptr = get_glyph (cptr, gbuf, ','); /* get glyph */\r | |
1136 | #else\r | |
1137 | damask = B_DAMASK;\r | |
1138 | cptr = get_glyph (cptr, gbuf, 0); /* get next field */\r | |
1139 | #endif\r | |
1140 | #if defined (PDP4) || defined (PDP7)\r | |
1141 | if (strcmp (gbuf, "I") == 0) { /* indirect? */\r | |
1142 | val[0] = val[0] | I_IND;\r | |
1143 | cptr = get_glyph (cptr, gbuf, 0);\r | |
1144 | }\r | |
1145 | #endif\r | |
1146 | epcmask = AMASK & ~damask; /* get ePC */\r | |
1147 | d = get_uint (gbuf, 8, AMASK, &r); /* get addr */\r | |
1148 | if (r != SCPE_OK) return SCPE_ARG;\r | |
1149 | if (d <= damask) val[0] = val[0] | d; /* fit in 12/13b? */\r | |
1150 | else if (cflag && (((addr ^ d) & epcmask) == 0))\r | |
1151 | val[0] = val[0] | (d & damask); /* hi bits = ePC? */\r | |
1152 | else return SCPE_ARG;\r | |
1153 | #if defined (PDP15)\r | |
1154 | if (!memm) {\r | |
1155 | cptr = get_glyph (cptr, gbuf, 0);\r | |
1156 | if (gbuf[0] != 0) {\r | |
1157 | if (strcmp (gbuf, "X") != 0) return SCPE_ARG;\r | |
1158 | val[0] = val[0] | I_IDX;\r | |
1159 | }\r | |
1160 | }\r | |
1161 | #endif\r | |
1162 | break;\r | |
1163 | \r | |
1164 | case I_V_EMD: /* or'able */\r | |
1165 | val[0] = val[0] | ((opc_val[i] >> I_V_DC) & 077); /* default shift */\r | |
1166 | case I_V_EST: case I_V_ESH: \r | |
1167 | case I_V_NPN: case I_V_NPI:\r | |
1168 | case I_V_IOT: case I_V_OPR:\r | |
1169 | for (cptr = get_glyph (cptr, gbuf, 0); gbuf[0] != 0;\r | |
1170 | cptr = get_glyph (cptr, gbuf, 0)) {\r | |
1171 | for (i = 0; (opcode[i] != NULL) &&\r | |
1172 | (strcmp (opcode[i], gbuf) != 0) ; i++) ;\r | |
1173 | if (opcode[i] != NULL) {\r | |
1174 | k = opc_val[i] & DMASK;\r | |
1175 | if (((k ^ val[0]) & 0740000) != 0) return SCPE_ARG;\r | |
1176 | val[0] = val[0] | k;\r | |
1177 | }\r | |
1178 | else {\r | |
1179 | d = get_sint (gbuf, & sign, &r);\r | |
1180 | if (r != SCPE_OK) return SCPE_ARG;\r | |
1181 | if (sign > 0) val[0] = val[0] + d; \r | |
1182 | else if (sign < 0) val[0] = val[0] - d;\r | |
1183 | else val[0] = val[0] | d;\r | |
1184 | }\r | |
1185 | }\r | |
1186 | break;\r | |
1187 | \r | |
1188 | case I_V_FPM: /* FP15 mem ref */\r | |
1189 | cptr = get_glyph (cptr, gbuf, 0); /* get next field */\r | |
1190 | val[1] = get_uint (gbuf, 8, AMASK, &r); /* get addr */\r | |
1191 | if (r != SCPE_OK) return SCPE_ARG;\r | |
1192 | sta = -1;\r | |
1193 | break;\r | |
1194 | \r | |
1195 | case I_V_FPI: /* FP15 ind mem ref */\r | |
1196 | cptr = get_glyph (cptr, gbuf, 0); /* get next field */\r | |
1197 | val[1] = get_uint (gbuf, 8, AMASK, &r) | SIGN; /* get @addr */\r | |
1198 | if (r != SCPE_OK) return SCPE_ARG;\r | |
1199 | sta = -1;\r | |
1200 | break;\r | |
1201 | \r | |
1202 | case I_V_FPN: /* FP15 no operand */\r | |
1203 | val[1] = 0;\r | |
1204 | sta = -1;\r | |
1205 | break;\r | |
1206 | } /* end case */\r | |
1207 | \r | |
1208 | if (*cptr != 0) return SCPE_ARG; /* junk at end? */\r | |
1209 | return sta;\r | |
1210 | }\r |