Commit | Line | Data |
---|---|---|
196ba1fc PH |
1 | /* vax_defs.h: VAX architecture definitions file\r |
2 | \r | |
3 | Copyright (c) 1998-2006, Robert M Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | The author gratefully acknowledges the help of Stephen Shirron, Antonio\r | |
27 | Carlini, and Kevin Peterson in providing specifications for the Qbus VAX's\r | |
28 | \r | |
29 | 09-May-06 RMS Added system PTE ACV error code\r | |
30 | 03-May-06 RMS Added EDITPC get/put cc's macros\r | |
31 | 03-Nov-05 RMS Added 780 stop codes\r | |
32 | 22-Jul-05 RMS Fixed warning from Solaris C (from Doug Gwyn)\r | |
33 | 02-Sep-04 RMS Added octa specifier definitions\r | |
34 | 30-Aug-04 RMS Added octa, h_floating instruction definitions\r | |
35 | 24-Aug-04 RMS Added compatibility mode definitions\r | |
36 | 18-Apr-04 RMS Added octa, fp, string definitions\r | |
37 | 19-May-03 RMS Revised for new conditional compilation scheme\r | |
38 | 14-Jul-02 RMS Added infinite loop message\r | |
39 | 30-Apr-02 RMS Added CLR_TRAPS macro\r | |
40 | */\r | |
41 | \r | |
42 | #ifndef _VAX_DEFS_H\r | |
43 | #define _VAX_DEFS_H 0\r | |
44 | \r | |
45 | #ifndef VM_VAX\r | |
46 | #define VM_VAX 0\r | |
47 | #endif\r | |
48 | \r | |
49 | #include "sim_defs.h"\r | |
50 | #include <setjmp.h>\r | |
51 | \r | |
52 | /* Stops and aborts */\r | |
53 | \r | |
54 | #define STOP_HALT 1 /* halt */\r | |
55 | #define STOP_IBKPT 2 /* breakpoint */\r | |
56 | #define STOP_CHMFI 3 /* chg mode IS */\r | |
57 | #define STOP_ILLVEC 4 /* illegal vector */\r | |
58 | #define STOP_INIE 5 /* exc in intexc */\r | |
59 | #define STOP_PPTE 6 /* proc pte in Px */\r | |
60 | #define STOP_UIPL 7 /* undefined IPL */\r | |
61 | #define STOP_RQ 8 /* fatal RQ err */\r | |
62 | #define STOP_LOOP 9 /* infinite loop */\r | |
63 | #define STOP_SANITY 10 /* sanity timer exp */\r | |
64 | #define STOP_SWDN 11 /* software done (780) */\r | |
65 | #define STOP_BOOT 12 /* reboot (780) */\r | |
66 | #define STOP_UNKNOWN 13 /* unknown reason */\r | |
67 | #define STOP_UNKABO 14 /* unknown abort */\r | |
68 | #define ABORT_INTR -1 /* interrupt */\r | |
69 | #define ABORT_MCHK (-SCB_MCHK) /* machine check */\r | |
70 | #define ABORT_RESIN (-SCB_RESIN) /* rsvd instruction */\r | |
71 | #define ABORT_RESAD (-SCB_RESAD) /* rsvd addr mode */\r | |
72 | #define ABORT_RESOP (-SCB_RESOP) /* rsvd operand */ \r | |
73 | #define ABORT_CMODE (-SCB_CMODE) /* comp mode fault */\r | |
74 | #define ABORT_ARITH (-SCB_ARITH) /* arithmetic trap */\r | |
75 | #define ABORT_ACV (-SCB_ACV) /* access violation */\r | |
76 | #define ABORT_TNV (-SCB_TNV) /* transl not vaid */\r | |
77 | #define ABORT(x) longjmp (save_env, (x)) /* abort */\r | |
78 | #define RSVD_INST_FAULT ABORT (ABORT_RESIN)\r | |
79 | #define RSVD_ADDR_FAULT ABORT (ABORT_RESAD)\r | |
80 | #define RSVD_OPND_FAULT ABORT (ABORT_RESOP)\r | |
81 | #define FLT_OVFL_FAULT p1 = FLT_OVRFLO, ABORT (ABORT_ARITH)\r | |
82 | #define FLT_DZRO_FAULT p1 = FLT_DIVZRO, ABORT (ABORT_ARITH)\r | |
83 | #define FLT_UNFL_FAULT p1 = FLT_UNDFLO, ABORT (ABORT_ARITH)\r | |
84 | #define CMODE_FAULT(cd) p1 = (cd), ABORT (ABORT_CMODE)\r | |
85 | #define MACH_CHECK(cd) p1 = (cd), ABORT (ABORT_MCHK)\r | |
86 | \r | |
87 | /* Recovery queue */\r | |
88 | \r | |
89 | #define RQ_RN 0xF /* register */\r | |
90 | #define RQ_V_LNT 4 /* length */\r | |
91 | #define RQ_M_LNT 0x7 /* 0,1,2,3,4 */\r | |
92 | #define RQ_DIR 0x800 /* 0 = -, 1 = + */\r | |
93 | #define RQ_REC(d,r) (((d) << RQ_V_LNT) | (r))\r | |
94 | #define RQ_GETRN(x) ((x) & RQ_RN)\r | |
95 | #define RQ_GETLNT(x) (((x) >> RQ_V_LNT) & RQ_M_LNT)\r | |
96 | \r | |
97 | /* Address space */\r | |
98 | \r | |
99 | #define VAMASK 0xFFFFFFFF /* virt addr mask */\r | |
100 | #define PAWIDTH 30 /* phys addr width */\r | |
101 | #define PASIZE (1 << PAWIDTH) /* phys addr size */\r | |
102 | #define PAMASK (PASIZE - 1) /* phys addr mask */\r | |
103 | #define IOPAGE (1 << (PAWIDTH - 1)) /* start of I/O page */\r | |
104 | \r | |
105 | /* Architectural constants */\r | |
106 | \r | |
107 | #define BMASK 0x000000FF /* byte */\r | |
108 | #define BSIGN 0x00000080\r | |
109 | #define WMASK 0x0000FFFF /* word */\r | |
110 | #define WSIGN 0x00008000\r | |
111 | #define LMASK 0xFFFFFFFF /* longword */\r | |
112 | #define LSIGN 0x80000000\r | |
113 | #define FPSIGN 0x00008000 /* floating point */\r | |
114 | #define L_BYTE 1 /* bytes per */\r | |
115 | #define L_WORD 2 /* data type */\r | |
116 | #define L_LONG 4\r | |
117 | #define L_QUAD 8\r | |
118 | #define L_OCTA 16\r | |
119 | #define NUM_INST 512 /* one byte+two byte */\r | |
120 | #define MAX_SPEC 6 /* max spec/instr */\r | |
121 | \r | |
122 | /* Floating point formats */\r | |
123 | \r | |
124 | #define FD_V_EXP 7 /* f/d exponent */\r | |
125 | #define FD_M_EXP 0xFF\r | |
126 | #define FD_BIAS 0x80 /* f/d bias */\r | |
127 | #define FD_EXP (FD_M_EXP << FD_V_EXP)\r | |
128 | #define FD_HB (1 << FD_V_EXP) /* f/d hidden bit */\r | |
129 | #define FD_GUARD (15 - FD_V_EXP) /* # guard bits */\r | |
130 | #define FD_GETEXP(x) (((x) >> FD_V_EXP) & FD_M_EXP)\r | |
131 | \r | |
132 | #define G_V_EXP 4 /* g exponent */\r | |
133 | #define G_M_EXP 0x7FF\r | |
134 | #define G_BIAS 0x400 /* g bias */\r | |
135 | #define G_EXP (G_M_EXP << G_V_EXP)\r | |
136 | #define G_HB (1 << G_V_EXP) /* g hidden bit */\r | |
137 | #define G_GUARD (15 - G_V_EXP) /* # guard bits */\r | |
138 | #define G_GETEXP(x) (((x) >> G_V_EXP) & G_M_EXP)\r | |
139 | \r | |
140 | #define H_V_EXP 0 /* h exponent */\r | |
141 | #define H_M_EXP 0x7FFF\r | |
142 | #define H_BIAS 0x4000 /* h bias */\r | |
143 | #define H_EXP (H_M_EXP << H_V_EXP)\r | |
144 | #define H_HB (1 << H_V_EXP) /* h hidden bit */\r | |
145 | #define H_GUARD (15 - H_V_EXP) /* # guard bits */\r | |
146 | #define H_GETEXP(x) (((x) >> H_V_EXP) & H_M_EXP)\r | |
147 | \r | |
148 | /* Memory management modes */\r | |
149 | \r | |
150 | #define KERN 0\r | |
151 | #define EXEC 1\r | |
152 | #define SUPV 2\r | |
153 | #define USER 3\r | |
154 | \r | |
155 | /* Register and stack aliases */\r | |
156 | \r | |
157 | #define nAP 12\r | |
158 | #define nFP 13\r | |
159 | #define nSP 14\r | |
160 | #define nPC 15\r | |
161 | #define AP R[nAP]\r | |
162 | #define FP R[nFP]\r | |
163 | #define SP R[nSP]\r | |
164 | #define PC R[nPC]\r | |
165 | #define RGMASK 0xF\r | |
166 | #define KSP STK[KERN]\r | |
167 | #define ESP STK[EXEC]\r | |
168 | #define SSP STK[SUPV]\r | |
169 | #define USP STK[USER]\r | |
170 | #define IS STK[4]\r | |
171 | \r | |
172 | /* PSL, PSW, and condition codes */\r | |
173 | \r | |
174 | #define PSL_V_CM 31 /* compatibility mode */\r | |
175 | #define PSL_CM (1u << PSL_V_CM)\r | |
176 | #define PSL_V_TP 30 /* trace pending */\r | |
177 | #define PSL_TP (1 << PSL_V_TP)\r | |
178 | #define PSL_V_FPD 27 /* first part done */\r | |
179 | #define PSL_FPD (1 << PSL_V_FPD)\r | |
180 | #define PSL_V_IS 26 /* interrupt stack */\r | |
181 | #define PSL_IS (1 << PSL_V_IS)\r | |
182 | #define PSL_V_CUR 24 /* current mode */\r | |
183 | #define PSL_V_PRV 22 /* previous mode */\r | |
184 | #define PSL_M_MODE 0x3 /* mode mask */\r | |
185 | #define PSL_CUR (PSL_M_MODE << PSL_V_CUR)\r | |
186 | #define PSL_PRV (PSL_M_MODE << PSL_V_PRV)\r | |
187 | #define PSL_V_IPL 16 /* int priority lvl */\r | |
188 | #define PSL_M_IPL 0x1F\r | |
189 | #define PSL_IPL (PSL_M_IPL << PSL_V_IPL)\r | |
190 | #define PSL_IPL1 (0x01 << PSL_V_IPL)\r | |
191 | #define PSL_IPL1F (0x1F << PSL_V_IPL)\r | |
192 | #define PSL_MBZ (0x30200000 | PSW_MBZ) /* must be zero */\r | |
193 | #define PSW_MBZ 0xFF00 /* must be zero */\r | |
194 | #define PSW_DV 0x80 /* dec ovflo enable */\r | |
195 | #define PSW_FU 0x40 /* flt undflo enable */\r | |
196 | #define PSW_IV 0x20 /* int ovflo enable */\r | |
197 | #define PSW_T 0x10 /* trace enable */\r | |
198 | #define CC_N 0x08 /* negative */\r | |
199 | #define CC_Z 0x04 /* zero */\r | |
200 | #define CC_V 0x02 /* overflow */\r | |
201 | #define CC_C 0x01 /* carry */\r | |
202 | #define CC_MASK (CC_N | CC_Z | CC_V | CC_C)\r | |
203 | #define PSL_GETCUR(x) (((x) >> PSL_V_CUR) & PSL_M_MODE)\r | |
204 | #define PSL_GETPRV(x) (((x) >> PSL_V_PRV) & PSL_M_MODE)\r | |
205 | #define PSL_GETIPL(x) (((x) >> PSL_V_IPL) & PSL_M_IPL)\r | |
206 | \r | |
207 | /* Software interrupt summary register */\r | |
208 | \r | |
209 | #define SISR_MASK 0xFFFE\r | |
210 | #define SISR_2 (1 << 2)\r | |
211 | \r | |
212 | /* AST register */\r | |
213 | \r | |
214 | #define AST_MASK 7\r | |
215 | #define AST_MAX 4\r | |
216 | \r | |
217 | /* Virtual address */\r | |
218 | \r | |
219 | #define VA_N_OFF 9 /* offset size */\r | |
220 | #define VA_PAGSIZE (1u << VA_N_OFF) /* page size */\r | |
221 | #define VA_M_OFF ((1u << VA_N_OFF) - 1) /* offset mask */\r | |
222 | #define VA_V_VPN VA_N_OFF /* vpn start */\r | |
223 | #define VA_N_VPN (31 - VA_N_OFF) /* vpn size */\r | |
224 | #define VA_M_VPN ((1u << VA_N_VPN) - 1) /* vpn mask */\r | |
225 | #define VA_S0 (1u << 31) /* S0 space */\r | |
226 | #define VA_P1 (1u << 30) /* P1 space */\r | |
227 | #define VA_N_TBI 12 /* TB index size */\r | |
228 | #define VA_TBSIZE (1u << VA_N_TBI) /* TB size */\r | |
229 | #define VA_M_TBI ((1u << VA_N_TBI) - 1) /* TB index mask */\r | |
230 | #define VA_GETOFF(x) ((x) & VA_M_OFF)\r | |
231 | #define VA_GETVPN(x) (((x) >> VA_V_VPN) & VA_M_VPN)\r | |
232 | #define VA_GETTBI(x) ((x) & VA_M_TBI)\r | |
233 | \r | |
234 | /* PTE */\r | |
235 | \r | |
236 | #define PTE_V_V 31 /* valid */\r | |
237 | #define PTE_V (1u << PTE_V_V)\r | |
238 | #define PTE_V_ACC 27 /* access */\r | |
239 | #define PTE_M_ACC 0xF\r | |
240 | #define PTE_ACC (PTE_M_ACC << PTE_V_ACC)\r | |
241 | #define PTE_V_M 26 /* modified */\r | |
242 | #define PTE_M (1u << PTE_V_M)\r | |
243 | #define PTE_GETACC(x) (((x) >> PTE_V_ACC) & PTE_M_ACC)\r | |
244 | \r | |
245 | /* TLB entry */\r | |
246 | \r | |
247 | #define TLB_V_RACC 0 /* rd acc field */\r | |
248 | #define TLB_V_WACC 4 /* wr acc field */\r | |
249 | #define TLB_M_ACC 0xF\r | |
250 | #define TLB_RACC (TLB_M_ACC << TLB_V_RACC)\r | |
251 | #define TLB_WACC (TLB_M_ACC << TLB_V_WACC)\r | |
252 | #define TLB_V_M 8 /* m bit */\r | |
253 | #define TLB_M (1u << TLB_V_M)\r | |
254 | #define TLB_N_PFN (PAWIDTH - VA_N_OFF) /* ppfn size */\r | |
255 | #define TLB_M_PFN ((1u << TLB_N_PFN) - 1) /* ppfn mask */\r | |
256 | #define TLB_PFN (TLB_M_PFN << VA_V_VPN)\r | |
257 | \r | |
258 | /* Traps and interrupt requests */\r | |
259 | \r | |
260 | #define TIR_V_IRQL 0 /* int request lvl */\r | |
261 | #define TIR_V_TRAP 5 /* trap requests */\r | |
262 | #define TIR_M_TRAP 07\r | |
263 | #define TIR_TRAP (TIR_M_TRAP << TIR_V_TRAP)\r | |
264 | #define TRAP_INTOV (1 << TIR_V_TRAP) /* integer overflow */\r | |
265 | #define TRAP_DIVZRO (2 << TIR_V_TRAP) /* divide by zero */\r | |
266 | #define TRAP_FLTOVF (3 << TIR_V_TRAP) /* flt overflow */\r | |
267 | #define TRAP_FLTDIV (4 << TIR_V_TRAP) /* flt/dec div by zero */\r | |
268 | #define TRAP_FLTUND (5 << TIR_V_TRAP) /* flt underflow */\r | |
269 | #define TRAP_DECOVF (6 << TIR_V_TRAP) /* decimal overflow */\r | |
270 | #define TRAP_SUBSCR (7 << TIR_V_TRAP) /* subscript range */\r | |
271 | #define SET_TRAP(x) trpirq = (trpirq & PSL_M_IPL) | (x)\r | |
272 | #define CLR_TRAPS trpirq = trpirq & ~TIR_TRAP\r | |
273 | #define SET_IRQL trpirq = (trpirq & TIR_TRAP) | eval_int ()\r | |
274 | #define GET_TRAP(x) (((x) >> TIR_V_TRAP) & TIR_M_TRAP)\r | |
275 | #define GET_IRQL(x) (((x) >> TIR_V_IRQL) & PSL_M_IPL)\r | |
276 | \r | |
277 | /* Floating point fault parameters */\r | |
278 | \r | |
279 | #define FLT_OVRFLO 0x8 /* flt overflow */\r | |
280 | #define FLT_DIVZRO 0x9 /* flt div by zero */\r | |
281 | #define FLT_UNDFLO 0xA /* flt underflow */\r | |
282 | \r | |
283 | /* Compatability mode fault parameters */\r | |
284 | \r | |
285 | #define CMODE_RSVI 0x0 /* reserved instr */\r | |
286 | #define CMODE_BPT 0x1 /* BPT */\r | |
287 | #define CMODE_IOT 0x2 /* IOT */\r | |
288 | #define CMODE_EMT 0x3 /* EMT */\r | |
289 | #define CMODE_TRAP 0x4 /* TRAP */\r | |
290 | #define CMODE_ILLI 0x5 /* illegal instr */\r | |
291 | #define CMODE_ODD 0x6 /* odd address */\r | |
292 | \r | |
293 | /* EDITPC suboperators */\r | |
294 | \r | |
295 | #define EO_END 0x00 /* end */\r | |
296 | #define EO_END_FLOAT 0x01 /* end float */\r | |
297 | #define EO_CLR_SIGNIF 0x02 /* clear signif */\r | |
298 | #define EO_SET_SIGNIF 0x03 /* set signif */\r | |
299 | #define EO_STORE_SIGN 0x04 /* store sign */\r | |
300 | #define EO_LOAD_FILL 0x40 /* load fill */\r | |
301 | #define EO_LOAD_SIGN 0x41 /* load sign */\r | |
302 | #define EO_LOAD_PLUS 0x42 /* load sign if + */\r | |
303 | #define EO_LOAD_MINUS 0x43 /* load sign if - */\r | |
304 | #define EO_INSERT 0x44 /* insert */\r | |
305 | #define EO_BLANK_ZERO 0x45 /* blank zero */\r | |
306 | #define EO_REPL_SIGN 0x46 /* replace sign */\r | |
307 | #define EO_ADJUST_LNT 0x47 /* adjust length */\r | |
308 | #define EO_FILL 0x80 /* fill */\r | |
309 | #define EO_MOVE 0x90 /* move */\r | |
310 | #define EO_FLOAT 0xA0 /* float */\r | |
311 | #define EO_RPT_MASK 0x0F /* rpt mask */\r | |
312 | #define EO_RPT_FLAG 0x80 /* rpt flag */\r | |
313 | \r | |
314 | /* EDITPC R2 packup parameters */\r | |
315 | \r | |
316 | #define ED_V_CC 16 /* condition codes */\r | |
317 | #define ED_M_CC 0xFF\r | |
318 | #define ED_CC (ED_M_CC << ED_V_CC)\r | |
319 | #define ED_V_SIGN 8 /* sign */\r | |
320 | #define ED_M_SIGN 0xFF\r | |
321 | #define ED_SIGN (ED_M_SIGN << ED_V_SIGN)\r | |
322 | #define ED_V_FILL 0 /* fill */\r | |
323 | #define ED_M_FILL 0xFF\r | |
324 | #define ED_FILL (ED_M_FILL << ED_V_FILL)\r | |
325 | #define ED_GETCC(x) (((x) >> ED_V_CC) & CC_MASK)\r | |
326 | #define ED_GETSIGN(x) (((x) >> ED_V_SIGN) & ED_M_SIGN)\r | |
327 | #define ED_GETFILL(x) (((x) >> ED_V_FILL) & ED_M_FILL)\r | |
328 | #define ED_PUTCC(r,x) (((r) & ~ED_CC) | (((x) << ED_V_CC) & ED_CC))\r | |
329 | #define ED_PUTSIGN(r,x) (((r) & ~ED_SIGN) | (((x) << ED_V_SIGN) & ED_SIGN))\r | |
330 | #define ED_PUTFILL(r,x) (((r) & ~ED_FILL) | (((x) << ED_V_FILL) & ED_FILL))\r | |
331 | \r | |
332 | /* SCB offsets */\r | |
333 | \r | |
334 | #define SCB_MCHK 0x04 /* machine chk */\r | |
335 | #define SCB_KSNV 0x08 /* ker stk invalid */\r | |
336 | #define SCB_PWRFL 0x0C /* power fail */\r | |
337 | #define SCB_RESIN 0x10 /* rsvd/priv instr */\r | |
338 | #define SCB_XFC 0x14 /* XFC instr */\r | |
339 | #define SCB_RESOP 0x18 /* rsvd operand */\r | |
340 | #define SCB_RESAD 0x1C /* rsvd addr mode */\r | |
341 | #define SCB_ACV 0x20 /* ACV */\r | |
342 | #define SCB_TNV 0x24 /* TNV */\r | |
343 | #define SCB_TP 0x28 /* trace pending */\r | |
344 | #define SCB_BPT 0x2C /* BPT instr */\r | |
345 | #define SCB_CMODE 0x30 /* comp mode fault */\r | |
346 | #define SCB_ARITH 0x34 /* arith fault */\r | |
347 | #define SCB_CHMK 0x40 /* CHMK */\r | |
348 | #define SCB_CHME 0x44 /* CHME */\r | |
349 | #define SCB_CHMS 0x48 /* CHMS */\r | |
350 | #define SCB_CHMU 0x4C /* CHMU */\r | |
351 | #define SCB_CRDERR 0x54 /* CRD err intr */\r | |
352 | #define SCB_MEMERR 0x60 /* mem err intr */\r | |
353 | #define SCB_IPLSOFT 0x80 /* software intr */\r | |
354 | #define SCB_INTTIM 0xC0 /* timer intr */\r | |
355 | #define SCB_EMULATE 0xC8 /* emulation */\r | |
356 | #define SCB_EMULFPD 0xCC /* emulation, FPD */\r | |
357 | #define SCB_CSI 0xF0 /* constor input */\r | |
358 | #define SCB_CSO 0xF4 /* constor output */\r | |
359 | #define SCB_TTI 0xF8 /* console input */\r | |
360 | #define SCB_TTO 0xFC /* console output */\r | |
361 | #define SCB_INTR 0x100 /* hardware intr */\r | |
362 | \r | |
363 | #define IPL_HLTPIN 0x1F /* halt pin IPL */\r | |
364 | #define IPL_MEMERR 0x1D /* mem err IPL */\r | |
365 | #define IPL_CRDERR 0x1A /* CRD err IPL */\r | |
366 | \r | |
367 | /* Interrupt and exception types */\r | |
368 | \r | |
369 | #define IE_SVE -1 /* severe exception */\r | |
370 | #define IE_EXC 0 /* normal exception */\r | |
371 | #define IE_INT 1 /* interrupt */\r | |
372 | \r | |
373 | /* Decode ROM: opcode entry */\r | |
374 | \r | |
375 | #define DR_F 0x80 /* FPD ok flag */\r | |
376 | #define DR_NSPMASK 0x07 /* #specifiers */\r | |
377 | #define DR_V_USPMASK 4\r | |
378 | #define DR_M_USPMASK 0x70 /* #spec, sym_ */\r | |
379 | #define DR_GETNSP(x) ((x) & DR_NSPMASK)\r | |
380 | #define DR_GETUSP(x) (((x) >> DR_V_USPMASK) & DR_M_USPMASK)\r | |
381 | \r | |
382 | /* Decode ROM: specifier entry */\r | |
383 | \r | |
384 | #define DR_ACMASK 0x300 /* type */\r | |
385 | #define DR_SPFLAG 0x008 /* special decode */\r | |
386 | #define DR_LNMASK 0x007 /* length mask */\r | |
387 | #define DR_LNT(x) (1 << (x & DR_LNMASK)) /* disp to lnt */\r | |
388 | \r | |
389 | /* Decode ROM: length */\r | |
390 | \r | |
391 | #define DR_BYTE 0x000 /* byte */\r | |
392 | #define DR_WORD 0x001 /* word */\r | |
393 | #define DR_LONG 0x002 /* long */\r | |
394 | #define DR_QUAD 0x003 /* quad */\r | |
395 | #define DR_OCTA 0x004 /* octa */\r | |
396 | \r | |
397 | /* Decode ROM: operand type */\r | |
398 | \r | |
399 | #define SH0 0x000 /* short literal */\r | |
400 | #define SH1 0x010\r | |
401 | #define SH2 0x020\r | |
402 | #define SH3 0x030\r | |
403 | #define IDX 0x040 /* indexed */\r | |
404 | #define GRN 0x050 /* register */\r | |
405 | #define RGD 0x060 /* register def */\r | |
406 | #define ADC 0x070 /* autodecrement */\r | |
407 | #define AIN 0x080 /* autoincrement */\r | |
408 | #define AID 0x090 /* autoinc def */\r | |
409 | #define BDP 0x0A0 /* byte disp */\r | |
410 | #define BDD 0x0B0 /* byte disp def */\r | |
411 | #define WDP 0x0C0 /* word disp */\r | |
412 | #define WDD 0x0D0 /* word disp def */\r | |
413 | #define LDP 0x0E0 /* long disp */\r | |
414 | #define LDD 0x0F0 /* long disp def */\r | |
415 | \r | |
416 | /* Decode ROM: access type */\r | |
417 | \r | |
418 | #define DR_R 0x000 /* read */\r | |
419 | #define DR_M 0x100 /* modify */\r | |
420 | #define DR_A 0x200 /* address */\r | |
421 | #define DR_W 0x300 /* write */\r | |
422 | \r | |
423 | /* Decode ROM: access type and length */\r | |
424 | \r | |
425 | #define RB (DR_R|DR_BYTE)\r | |
426 | #define RW (DR_R|DR_WORD)\r | |
427 | #define RL (DR_R|DR_LONG)\r | |
428 | #define RQ (DR_R|DR_QUAD)\r | |
429 | #define RO (DR_R|DR_OCTA)\r | |
430 | #define MB (DR_M|DR_BYTE)\r | |
431 | #define MW (DR_M|DR_WORD)\r | |
432 | #define ML (DR_M|DR_LONG)\r | |
433 | #define MQ (DR_M|DR_QUAD)\r | |
434 | #define MO (DR_M|DR_OCTA)\r | |
435 | #define AB (DR_A|DR_BYTE)\r | |
436 | #define AW (DR_A|DR_WORD)\r | |
437 | #define AL (DR_A|DR_LONG)\r | |
438 | #define AQ (DR_A|DR_QUAD)\r | |
439 | #define AO (DR_A|DR_OCTA)\r | |
440 | #define WB (DR_W|DR_BYTE)\r | |
441 | #define WW (DR_W|DR_WORD)\r | |
442 | #define WL (DR_W|DR_LONG)\r | |
443 | #define WQ (DR_W|DR_QUAD)\r | |
444 | #define WO (DR_W|DR_OCTA)\r | |
445 | \r | |
446 | /* Special dispatches.\r | |
447 | \r | |
448 | vb = variable bit field, treated as wb except for register\r | |
449 | rf = f_floating, treated as rl except for short literal\r | |
450 | rd = d_floating, treated as rq except for short literal\r | |
451 | rg = g_floating, treated as rq except for short literal\r | |
452 | rh = h_floating, treated as ro except for short literal\r | |
453 | bb = branch byte displacement\r | |
454 | bw = branch word displacement\r | |
455 | \r | |
456 | Length field must be correct\r | |
457 | */\r | |
458 | \r | |
459 | #define VB (DR_SPFLAG|WB) /* .vb */\r | |
460 | #define RF (DR_SPFLAG|RL) /* .rf */\r | |
461 | #define RD (DR_SPFLAG|RQ) /* .rd */\r | |
462 | #define RG (DR_SPFLAG|MQ) /* .rg */\r | |
463 | #define RH (DR_SPFLAG|RO) /* .rh */\r | |
464 | #define BB (DR_SPFLAG|WB|6) /* byte branch */\r | |
465 | #define BW (DR_SPFLAG|WB|7) /* word branch */\r | |
466 | \r | |
467 | /* Probe results and memory management fault codes */\r | |
468 | \r | |
469 | #define PR_ACV 0 /* ACV */\r | |
470 | #define PR_LNV 1 /* length viol */\r | |
471 | #define PR_PACV 2 /* pte ACV (780) */\r | |
472 | #define PR_PLNV 3 /* pte len viol */\r | |
473 | #define PR_TNV 4 /* TNV */\r | |
474 | /* #define PR_TB 5 /* impossible */\r | |
475 | #define PR_PTNV 6 /* pte TNV */\r | |
476 | #define PR_OK 7 /* ok */\r | |
477 | #define MM_PARAM(w,p) (((w)? 4: 0) | ((p) & 3)) /* fault param */\r | |
478 | \r | |
479 | /* Memory management errors */\r | |
480 | \r | |
481 | #define MM_WRITE 4 /* write */\r | |
482 | #define MM_EMASK 3 /* against probe */\r | |
483 | \r | |
484 | /* Privileged registers */\r | |
485 | \r | |
486 | #define MT_KSP 0\r | |
487 | #define MT_ESP 1\r | |
488 | #define MT_SSP 2\r | |
489 | #define MT_USP 3\r | |
490 | #define MT_IS 4\r | |
491 | #define MT_P0BR 8\r | |
492 | #define MT_P0LR 9\r | |
493 | #define MT_P1BR 10\r | |
494 | #define MT_P1LR 11\r | |
495 | #define MT_SBR 12\r | |
496 | #define MT_SLR 13\r | |
497 | #define MT_PCBB 16\r | |
498 | #define MT_SCBB 17\r | |
499 | #define MT_IPL 18\r | |
500 | #define MT_ASTLVL 19\r | |
501 | #define MT_SIRR 20\r | |
502 | #define MT_SISR 21\r | |
503 | #define MT_ICCS 24\r | |
504 | #define MT_NICR 25\r | |
505 | #define MT_ICR 26\r | |
506 | #define MT_TODR 27\r | |
507 | #define MT_CSRS 28\r | |
508 | #define MT_CSRD 29\r | |
509 | #define MT_CSTS 30\r | |
510 | #define MT_CSTD 31\r | |
511 | #define MT_RXCS 32\r | |
512 | #define MT_RXDB 33\r | |
513 | #define MT_TXCS 34\r | |
514 | #define MT_TXDB 35\r | |
515 | #define MT_MAPEN 56\r | |
516 | #define MT_TBIA 57\r | |
517 | #define MT_TBIS 58\r | |
518 | #define MT_PME 61\r | |
519 | #define MT_SID 62\r | |
520 | #define MT_TBCHK 63\r | |
521 | \r | |
522 | #define BR_MASK 0xFFFFFFFC\r | |
523 | #define LR_MASK 0x003FFFFF\r | |
524 | \r | |
525 | /* Opcodes */\r | |
526 | \r | |
527 | enum opcodes {\r | |
528 | HALT, NOP, REI, BPT, RET, RSB, LDPCTX, SVPCTX,\r | |
529 | CVTPS, CVTSP, INDEX, CRC, PROBER, PROBEW, INSQUE, REMQUE,\r | |
530 | BSBB, BRB, BNEQ, BEQL, BGTR, BLEQ, JSB, JMP,\r | |
531 | BGEQ, BLSS, BGTRU, BLEQU, BVC, BVS, BGEQU, BLSSU,\r | |
532 | ADDP4, ADDP6, SUBP4, SUBP6, CVTPT, MULP, CVTTP, DIVP,\r | |
533 | MOVC3, CMPC3, SCANC, SPANC, MOVC5, CMPC5, MOVTC, MOVTUC,\r | |
534 | BSBW, BRW, CVTWL, CVTWB, MOVP, CMPP3, CVTPL, CMPP4,\r | |
535 | EDITPC, MATCHC, LOCC, SKPC, MOVZWL, ACBW, MOVAW, PUSHAW,\r | |
536 | ADDF2, ADDF3, SUBF2, SUBF3, MULF2, MULF3, DIVF2, DIVF3,\r | |
537 | CVTFB, CVTFW, CVTFL, CVTRFL, CVTBF, CVTWF, CVTLF, ACBF,\r | |
538 | MOVF, CMPF, MNEGF, TSTF, EMODF, POLYF, CVTFD,\r | |
539 | ADAWI = 0x58, INSQHI = 0x5C, INSQTI, REMQHI, REMQTI,\r | |
540 | ADDD2, ADDD3, SUBD2, SUBD3, MULD2, MULD3, DIVD2, DIVD3,\r | |
541 | CVTDB, CVTDW, CVTDL, CVTRDL, CVTBD, CVTWD, CVTLD, ACBD,\r | |
542 | MOVD, CMPD, MNEGD, TSTD, EMODD, POLYD, CVTDF,\r | |
543 | ASHL = 0x78, ASHQ, EMUL, EDIV, CLRQ, MOVQ, MOVAQ, PUSHAQ,\r | |
544 | ADDB2, ADDB3, SUBB2, SUBB3, MULB2, MULB3, DIVB2, DIVB3,\r | |
545 | BISB2, BISB3, BICB2, BICB3, XORB2, XORB3, MNEGB, CASEB,\r | |
546 | MOVB, CMPB, MCOMB, BITB, CLRB, TSTB, INCB, DECB,\r | |
547 | CVTBL, CVTBW, MOVZBL, MOVZBW, ROTL, ACBB, MOVAB, PUSHAB,\r | |
548 | ADDW2, ADDW3, SUBW2, SUBW3, MULW2, MULW3, DIVW2, DIVW3,\r | |
549 | BISW2, BISW3, BICW2, BICW3, XORW2, XORW3, MNEGW, CASEW,\r | |
550 | MOVW, CMPW, MCOMW, BITW, CLRW, TSTW, INCW, DECW,\r | |
551 | BISPSW, BICPSW, POPR, PUSHR, CHMK, CHME, CHMS, CHMU,\r | |
552 | ADDL2, ADDL3, SUBL2, SUBL3, MULL2, MULL3, DIVL2, DIVL3,\r | |
553 | BISL2, BISL3, BICL2, BICL3, XORL2, XORL3, MNEGL, CASEL,\r | |
554 | MOVL, CMPL, MCOML, BITL, CLRL, TSTL, INCL, DECL,\r | |
555 | ADWC, SBWC, MTPR, MFPR, MOVPSL, PUSHL, MOVAL, PUSHAL,\r | |
556 | BBS, BBC, BBSS, BBCS, BBSC, BBCC, BBSSI, BBCCI,\r | |
557 | BLBS, BLBC, FFS, FFC, CMPV, CMPZV, EXTV, EXTZV,\r | |
558 | INSV, ACBL, AOBLSS, AOBLEQ, SOBGEQ, SOBGTR, CVTLB, CVTLW,\r | |
559 | ASHP, CVTLP, CALLG, CALLS, XFC, CVTDH = 0x132, CVTGF = 0x133,\r | |
560 | ADDG2 = 0x140, ADDG3, SUBG2, SUBG3, MULG2, MULG3, DIVG2, DIVG3,\r | |
561 | CVTGB, CVTGW, CVTGL, CVTRGL, CVTBG, CVTWG, CVTLG, ACBG,\r | |
562 | MOVG, CMPG, MNEGG, TSTG, EMODG, POLYG, CVTGH,\r | |
563 | ADDH2 = 0x160, ADDH3, SUBH2, SUBH3, MULH2, MULH3, DIVH2, DIVH3,\r | |
564 | CVTHB, CVTHW, CVTHL, CVTRHL, CVTBH, CVTWH, CVTLH, ACBH,\r | |
565 | MOVH, CMPH, MNEGH, TSTH, EMODH, POLYH, CVTHG,\r | |
566 | CLRO = 0x17C, MOVO, MOVAO, PUSHAO,\r | |
567 | CVTFH = 0x198, CVTFG = 0x199,\r | |
568 | CVTHF = 0x1F6, CVTHD = 0x1F7 };\r | |
569 | \r | |
570 | /* Repeated operations */\r | |
571 | \r | |
572 | #define SXTB(x) (((x) & BSIGN)? ((x) | ~BMASK): ((x) & BMASK))\r | |
573 | #define SXTW(x) (((x) & WSIGN)? ((x) | ~WMASK): ((x) & WMASK))\r | |
574 | #define SXTBW(x) (((x) & BSIGN)? ((x) | (WMASK - BMASK)): ((x) & BMASK))\r | |
575 | #define SXTL(x) (((x) & LSIGN)? ((x) | ~LMASK): ((x) & LMASK))\r | |
576 | #define INTOV if (PSL & PSW_IV) SET_TRAP (TRAP_INTOV)\r | |
577 | #define V_INTOV cc = cc | CC_V; INTOV\r | |
578 | #define NEG(x) ((~(x) + 1) & LMASK)\r | |
579 | \r | |
580 | /* Istream access */\r | |
581 | \r | |
582 | #define PCQ_SIZE 64 /* must be 2**n */\r | |
583 | #define PCQ_MASK (PCQ_SIZE - 1)\r | |
584 | #define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = fault_PC\r | |
585 | #define GET_ISTR(d,l) d = get_istr (l, acc)\r | |
586 | #define BRANCHB(d) PCQ_ENTRY, PC = PC + SXTB (d), FLUSH_ISTR\r | |
587 | #define BRANCHW(d) PCQ_ENTRY, PC = PC + SXTW (d), FLUSH_ISTR\r | |
588 | #define JUMP(d) PCQ_ENTRY, PC = (d), FLUSH_ISTR\r | |
589 | #define CMODE_JUMP(d) PCQ_ENTRY, PC = (d)\r | |
590 | #define SETPC(d) PC = (d), FLUSH_ISTR\r | |
591 | #define FLUSH_ISTR ibcnt = 0, ppc = -1\r | |
592 | \r | |
593 | /* Character string instructions */\r | |
594 | \r | |
595 | #define STR_V_DPC 24 /* delta PC */\r | |
596 | #define STR_M_DPC 0xFF\r | |
597 | #define STR_V_CHR 16 /* char argument */\r | |
598 | #define STR_M_CHR 0xFF\r | |
599 | #define STR_LNMASK 0xFFFF /* string length */\r | |
600 | #define STR_GETDPC(x) (((x) >> STR_V_DPC) & STR_M_DPC)\r | |
601 | #define STR_GETCHR(x) (((x) >> STR_V_CHR) & STR_M_CHR)\r | |
602 | #define STR_PACK(m,x) ((((PC - fault_PC) & STR_M_DPC) << STR_V_DPC) | \\r | |
603 | (((m) & STR_M_CHR) << STR_V_CHR) | ((x) & STR_LNMASK))\r | |
604 | \r | |
605 | /* Read and write */\r | |
606 | \r | |
607 | #define RA (acc)\r | |
608 | #define WA ((acc) << TLB_V_WACC)\r | |
609 | #define ACC_MASK(x) (1 << (x))\r | |
610 | #define TLB_ACCR(x) (ACC_MASK (x) << TLB_V_RACC)\r | |
611 | #define TLB_ACCW(x) (ACC_MASK (x) << TLB_V_WACC)\r | |
612 | #define REF_V 0\r | |
613 | #define REF_P 1\r | |
614 | \r | |
615 | /* Condition code macros */\r | |
616 | \r | |
617 | #define CC_ZZ1P cc = CC_Z | (cc & CC_C)\r | |
618 | \r | |
619 | #define CC_IIZZ_B(r) \\r | |
620 | if ((r) & BSIGN) cc = CC_N; \\r | |
621 | else if ((r) == 0) cc = CC_Z; \\r | |
622 | else cc = 0\r | |
623 | #define CC_IIZZ_W(r) \\r | |
624 | if ((r) & WSIGN) cc = CC_N; \\r | |
625 | else if ((r) == 0) cc = CC_Z; \\r | |
626 | else cc = 0\r | |
627 | #define CC_IIZZ_L(r) \\r | |
628 | if ((r) & LSIGN) cc = CC_N; \\r | |
629 | else if ((r) == 0) cc = CC_Z; \\r | |
630 | else cc = 0\r | |
631 | #define CC_IIZZ_Q(rl,rh) \\r | |
632 | if ((rh) & LSIGN) cc = CC_N; \\r | |
633 | else if (((rl) | (rh)) == 0) cc = CC_Z; \\r | |
634 | else cc = 0\r | |
635 | #define CC_IIZZ_FP CC_IIZZ_W\r | |
636 | \r | |
637 | #define CC_IIZP_B(r) \\r | |
638 | if ((r) & BSIGN) cc = CC_N | (cc & CC_C); \\r | |
639 | else if ((r) == 0) cc = CC_Z | (cc & CC_C); \\r | |
640 | else cc = cc & CC_C\r | |
641 | #define CC_IIZP_W(r) \\r | |
642 | if ((r) & WSIGN) cc = CC_N | (cc & CC_C); \\r | |
643 | else if ((r) == 0) cc = CC_Z | (cc & CC_C); \\r | |
644 | else cc = cc & CC_C\r | |
645 | #define CC_IIZP_L(r) \\r | |
646 | if ((r) & LSIGN) cc = CC_N | (cc & CC_C); \\r | |
647 | else if ((r) == 0) cc = CC_Z | (cc & CC_C); \\r | |
648 | else cc = cc & CC_C\r | |
649 | #define CC_IIZP_Q(rl,rh) \\r | |
650 | if ((rh) & LSIGN) cc = CC_N | (cc & CC_C); \\r | |
651 | else if (((rl) | (rh)) == 0) cc = CC_Z | (cc & CC_C); \\r | |
652 | else cc = cc & CC_C\r | |
653 | #define CC_IIZP_O(rl,rm2,rm1,rh) \\r | |
654 | if ((rh) & LSIGN) cc = CC_N | (cc & CC_C); \\r | |
655 | else if (((rl) | (rm2) | (rm1) | (rh)) == 0) cc = CC_Z | (cc & CC_C); \\r | |
656 | else cc = cc & CC_C\r | |
657 | #define CC_IIZP_FP CC_IIZP_W\r | |
658 | \r | |
659 | #define V_ADD_B(r,s1,s2) \\r | |
660 | if (((~(s1) ^ (s2)) & ((s1) ^ (r))) & BSIGN) { V_INTOV; }\r | |
661 | #define V_ADD_W(r,s1,s2) \\r | |
662 | if (((~(s1) ^ (s2)) & ((s1) ^ (r))) & WSIGN) { V_INTOV; }\r | |
663 | #define V_ADD_L(r,s1,s2) \\r | |
664 | if (((~(s1) ^ (s2)) & ((s1) ^ (r))) & LSIGN) { V_INTOV; }\r | |
665 | #define C_ADD(r,s1,s2) \\r | |
666 | if (((uint32) r) < ((uint32) s2)) cc = cc | CC_C\r | |
667 | \r | |
668 | #define CC_ADD_B(r,s1,s2) \\r | |
669 | CC_IIZZ_B (r); \\r | |
670 | V_ADD_B (r, s1, s2); \\r | |
671 | C_ADD (r, s1, s2)\r | |
672 | #define CC_ADD_W(r,s1,s2) \\r | |
673 | CC_IIZZ_W (r); \\r | |
674 | V_ADD_W (r, s1, s2); \\r | |
675 | C_ADD (r, s1, s2)\r | |
676 | #define CC_ADD_L(r,s1,s2) \\r | |
677 | CC_IIZZ_L (r); \\r | |
678 | V_ADD_L (r, s1, s2); \\r | |
679 | C_ADD (r, s1, s2)\r | |
680 | \r | |
681 | #define V_SUB_B(r,s1,s2) \\r | |
682 | if ((((s1) ^ (s2)) & (~(s1) ^ (r))) & BSIGN) { V_INTOV; }\r | |
683 | #define V_SUB_W(r,s1,s2) \\r | |
684 | if ((((s1) ^ (s2)) & (~(s1) ^ (r))) & WSIGN) { V_INTOV; }\r | |
685 | #define V_SUB_L(r,s1,s2) \\r | |
686 | if ((((s1) ^ (s2)) & (~(s1) ^ (r))) & LSIGN) { V_INTOV; }\r | |
687 | #define C_SUB(r,s1,s2) \\r | |
688 | if (((uint32) s2) < ((uint32) s1)) cc = cc | CC_C\r | |
689 | \r | |
690 | #define CC_SUB_B(r,s1,s2) \\r | |
691 | CC_IIZZ_B (r); \\r | |
692 | V_SUB_B (r, s1, s2); \\r | |
693 | C_SUB (r, s1, s2)\r | |
694 | #define CC_SUB_W(r,s1,s2) \\r | |
695 | CC_IIZZ_W (r); \\r | |
696 | V_SUB_W (r, s1, s2); \\r | |
697 | C_SUB (r, s1, s2)\r | |
698 | #define CC_SUB_L(r,s1,s2) \\r | |
699 | CC_IIZZ_L (r); \\r | |
700 | V_SUB_L (r, s1, s2); \\r | |
701 | C_SUB (r, s1, s2)\r | |
702 | \r | |
703 | #define CC_CMP_B(s1,s2) \\r | |
704 | if (SXTB (s1) < SXTB (s2)) cc = CC_N; \\r | |
705 | else if ((s1) == (s2)) cc = CC_Z; \\r | |
706 | else cc = 0; \\r | |
707 | if (((uint32) s1) < ((uint32) s2)) cc = cc | CC_C\r | |
708 | #define CC_CMP_W(s1,s2) \\r | |
709 | if (SXTW (s1) < SXTW (s2)) cc = CC_N; \\r | |
710 | else if ((s1) == (s2)) cc = CC_Z; \\r | |
711 | else cc = 0; \\r | |
712 | if (((uint32) s1) < ((uint32) s2)) cc = cc | CC_C\r | |
713 | #define CC_CMP_L(s1,s2) \\r | |
714 | if ((s1) < (s2)) cc = CC_N; \\r | |
715 | else if ((s1) == (s2)) cc = CC_Z; \\r | |
716 | else cc = 0; \\r | |
717 | if (((uint32) s1) < ((uint32) s2)) cc = cc | CC_C\r | |
718 | \r | |
719 | /* Model dependent definitions */\r | |
720 | \r | |
721 | #if defined (VAX_780)\r | |
722 | #include "vax780_defs.h"\r | |
723 | #else\r | |
724 | #include "vaxmod_defs.h"\r | |
725 | #endif\r | |
726 | \r | |
727 | #endif /* _VAX_DEFS_H */\r |