Commit | Line | Data |
---|---|---|
196ba1fc PH |
1 | /*************************************************************************\r |
2 | * *\r | |
3 | * $Id: s100_selchan.c 1771 2008-01-09 07:10:46Z hharte $ *\r | |
4 | * *\r | |
5 | * Copyright (c) 2007-2008 Howard M. Harte. *\r | |
6 | * http://www.hartetec.com *\r | |
7 | * *\r | |
8 | * Permission is hereby granted, free of charge, to any person obtaining *\r | |
9 | * a copy of this software and associated documentation files (the *\r | |
10 | * "Software"), to deal in the Software without restriction, including *\r | |
11 | * without limitation the rights to use, copy, modify, merge, publish, *\r | |
12 | * distribute, sublicense, and/or sell copies of the Software, and to *\r | |
13 | * permit persons to whom the Software is furnished to do so, subject to *\r | |
14 | * the following conditions: *\r | |
15 | * *\r | |
16 | * The above copyright notice and this permission notice shall be *\r | |
17 | * included in all copies or substantial portions of the Software. *\r | |
18 | * *\r | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, *\r | |
20 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF *\r | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND *\r | |
22 | * NONINFRINGEMENT. IN NO EVENT SHALL HOWARD M. HARTE BE LIABLE FOR ANY *\r | |
23 | * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, *\r | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE *\r | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. *\r | |
26 | * *\r | |
27 | * Except as contained in this notice, the name of Howard M. Harte shall *\r | |
28 | * not be used in advertising or otherwise to promote the sale, use or *\r | |
29 | * other dealings in this Software without prior written authorization *\r | |
30 | * Howard M. Harte. *\r | |
31 | * *\r | |
32 | * SIMH Interface based on altairz80_hdsk.c, by Peter Schorn. *\r | |
33 | * *\r | |
34 | * Module Description: *\r | |
35 | * CompuPro Selector Channel module for SIMH. *\r | |
36 | * *\r | |
37 | * Environment: *\r | |
38 | * User mode only *\r | |
39 | * *\r | |
40 | *************************************************************************/\r | |
41 | \r | |
42 | /*#define DBG_MSG */\r | |
43 | \r | |
44 | #include "altairz80_defs.h"\r | |
45 | \r | |
46 | #if defined (_WIN32)\r | |
47 | #include <windows.h>\r | |
48 | #endif\r | |
49 | \r | |
50 | #ifdef DBG_MSG\r | |
51 | #define DBG_PRINT(args) printf args\r | |
52 | #else\r | |
53 | #define DBG_PRINT(args)\r | |
54 | #endif\r | |
55 | \r | |
56 | #define TRACE_MSG 0x01\r | |
57 | #define DMA_MSG 0x02\r | |
58 | \r | |
59 | #define SELCHAN_MAX_DRIVES 1\r | |
60 | \r | |
61 | #define UNIT_V_SELCHAN_VERBOSE (UNIT_V_UF + 1) /* verbose mode, i.e. show error messages */\r | |
62 | #define UNIT_SELCHAN_VERBOSE (1 << UNIT_V_SELCHAN_VERBOSE)\r | |
63 | \r | |
64 | typedef struct {\r | |
65 | PNP_INFO pnp; /* Plug and Play */\r | |
66 | uint32 selchan; /* Selector Channel Register */\r | |
67 | uint32 dma_addr; /* DMA Transfer Address */\r | |
68 | uint32 dma_mode; /* DMA Mode register */\r | |
69 | uint8 reg_cnt; /* Counter for selchan register */\r | |
70 | } SELCHAN_INFO;\r | |
71 | \r | |
72 | static SELCHAN_INFO selchan_info_data = { { 0x0, 0, 0xF0, 1 } };\r | |
73 | static SELCHAN_INFO *selchan_info = &selchan_info_data;\r | |
74 | int32 selchan_dma(uint8 *buf, uint32 len);\r | |
75 | \r | |
76 | extern t_stat set_iobase(UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
77 | extern t_stat show_iobase(FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
78 | extern uint32 sim_map_resource(uint32 baseaddr, uint32 size, uint32 resource_type,\r | |
79 | int32 (*routine)(const int32, const int32, const int32), uint8 unmap);\r | |
80 | extern uint32 PCX;\r | |
81 | extern REG *sim_PC;\r | |
82 | \r | |
83 | /* These are needed for DMA. PIO Mode has not been implemented yet. */\r | |
84 | extern void PutBYTEWrapper(const uint32 Addr, const uint32 Value);\r | |
85 | extern uint8 GetBYTEWrapper(const uint32 Addr);\r | |
86 | \r | |
87 | static t_stat selchan_reset(DEVICE *selchan_dev);\r | |
88 | \r | |
89 | static int32 selchandev(const int32 port, const int32 io, const int32 data);\r | |
90 | \r | |
91 | static int32 trace_level = 0; /* Disable all tracing by default */\r | |
92 | \r | |
93 | static UNIT selchan_unit[] = {\r | |
94 | { UDATA (NULL, UNIT_FIX + UNIT_DISABLE + UNIT_ROABLE, 0) }\r | |
95 | };\r | |
96 | \r | |
97 | static REG selchan_reg[] = {\r | |
98 | { HRDATA (TRACELEVEL, trace_level, 16), },\r | |
99 | { NULL }\r | |
100 | };\r | |
101 | \r | |
102 | static MTAB selchan_mod[] = {\r | |
103 | { MTAB_XTD|MTAB_VDV, 0, "IOBASE", "IOBASE", &set_iobase, &show_iobase, NULL },\r | |
104 | /* quiet, no warning messages */\r | |
105 | { UNIT_SELCHAN_VERBOSE, 0, "QUIET", "QUIET", NULL },\r | |
106 | /* verbose, show warning messages */\r | |
107 | { UNIT_SELCHAN_VERBOSE, UNIT_SELCHAN_VERBOSE, "VERBOSE", "VERBOSE", NULL },\r | |
108 | { 0 }\r | |
109 | };\r | |
110 | \r | |
111 | DEVICE selchan_dev = {\r | |
112 | "SELCHAN", selchan_unit, selchan_reg, selchan_mod,\r | |
113 | SELCHAN_MAX_DRIVES, 10, 31, 1, SELCHAN_MAX_DRIVES, SELCHAN_MAX_DRIVES,\r | |
114 | NULL, NULL, &selchan_reset,\r | |
115 | NULL, NULL, NULL,\r | |
116 | &selchan_info_data, (DEV_DISABLE | DEV_DIS), 0,\r | |
117 | NULL, NULL, NULL\r | |
118 | };\r | |
119 | \r | |
120 | /* Reset routine */\r | |
121 | static t_stat selchan_reset(DEVICE *dptr)\r | |
122 | {\r | |
123 | PNP_INFO *pnp = (PNP_INFO *)dptr->ctxt;\r | |
124 | \r | |
125 | if(dptr->flags & DEV_DIS) { /* Disconnect I/O Ports */\r | |
126 | sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &selchandev, TRUE);\r | |
127 | } else {\r | |
128 | /* Connect SELCHAN at base address */\r | |
129 | if(sim_map_resource(pnp->io_base, pnp->io_size, RESOURCE_TYPE_IO, &selchandev, FALSE) != 0) {\r | |
130 | printf("%s: error mapping I/O resource at 0x%04x\n", __FUNCTION__, pnp->io_base);\r | |
131 | return SCPE_ARG;\r | |
132 | }\r | |
133 | }\r | |
134 | return SCPE_OK;\r | |
135 | }\r | |
136 | \r | |
137 | #define SELCHAN_MODE_WRITE 0x80 /* Selector Channel Memory or I/O Write */\r | |
138 | #define SELCHAN_MODE_IO 0x40 /* Set if I/O Access, otherwise memory */\r | |
139 | #define SELCHAN_MODE_CNT_UP 0x20 /* Set = DMA Address Count Up, otherwise down. (Mem only */\r | |
140 | #define SELCHAN_MODE_WAIT 0x10 /* Insert one wait state. */\r | |
141 | #define SELCHAN_MODE_DMA_MASK 0x0F /* Mask for DMA Priority field */\r | |
142 | \r | |
143 | static int32 selchandev(const int32 port, const int32 io, const int32 data)\r | |
144 | {\r | |
145 | DBG_PRINT(("SELCHAN: IO %s, Port %02x" NLP, io ? "WR" : "RD", port));\r | |
146 | if(io) {\r | |
147 | selchan_info->selchan <<= 8;\r | |
148 | selchan_info->selchan &= 0xFFFFFF00;\r | |
149 | selchan_info->selchan |= data;\r | |
150 | \r | |
151 | selchan_info->dma_addr = (selchan_info->selchan & 0xFFFFF00) >> 8;\r | |
152 | selchan_info->dma_mode = (selchan_info->selchan & 0xFF);\r | |
153 | \r | |
154 | selchan_info->reg_cnt ++;\r | |
155 | \r | |
156 | if(selchan_info->reg_cnt == 4) {\r | |
157 | TRACE_PRINT(TRACE_MSG, ("SELCHAN: " ADDRESS_FORMAT " DMA=0x%06x, Mode=0x%02x (%s, %s, %s)" NLP,\r | |
158 | PCX,\r | |
159 | selchan_info->dma_addr,\r | |
160 | selchan_info->dma_mode,\r | |
161 | selchan_info->dma_mode & SELCHAN_MODE_WRITE ? "WR" : "RD",\r | |
162 | selchan_info->dma_mode & SELCHAN_MODE_IO ? "I/O" : "MEM",\r | |
163 | selchan_info->dma_mode & SELCHAN_MODE_IO ? "FIX" : selchan_info->dma_mode & SELCHAN_MODE_CNT_UP ? "INC" : "DEC"));\r | |
164 | }\r | |
165 | \r | |
166 | return 0;\r | |
167 | } else {\r | |
168 | TRACE_PRINT(TRACE_MSG, ("SELCHAN: " ADDRESS_FORMAT " Reset" NLP, PCX));\r | |
169 | selchan_info->reg_cnt = 0;\r | |
170 | return(0xFF);\r | |
171 | }\r | |
172 | }\r | |
173 | \r | |
174 | int32 selchan_dma(uint8 *buf, uint32 len)\r | |
175 | {\r | |
176 | uint32 i;\r | |
177 | \r | |
178 | if(selchan_info->reg_cnt != 4) {\r | |
179 | printf("SELCHAN: " ADDRESS_FORMAT " Programming error: selector channel disabled." NLP,\r | |
180 | PCX);\r | |
181 | return (-1);\r | |
182 | }\r | |
183 | \r | |
184 | if(selchan_info->dma_mode & SELCHAN_MODE_IO)\r | |
185 | {\r | |
186 | printf("SELCHAN: " ADDRESS_FORMAT " I/O Not supported" NLP, PCX);\r | |
187 | return (-1);\r | |
188 | } else {\r | |
189 | TRACE_PRINT(DMA_MSG, ("SELCHAN: " ADDRESS_FORMAT " DMA %s Transfer, len=%d" NLP,\r | |
190 | PCX,\r | |
191 | (selchan_info->dma_mode & SELCHAN_MODE_WRITE) ? "WR" : "RD", len));\r | |
192 | for(i=0;i<len;i++) {\r | |
193 | if(selchan_info->dma_mode & SELCHAN_MODE_WRITE) {\r | |
194 | PutBYTEWrapper(selchan_info->dma_addr + i, buf[i]);\r | |
195 | } else {\r | |
196 | buf[i] = GetBYTEWrapper(selchan_info->dma_addr + i);\r | |
197 | }\r | |
198 | }\r | |
199 | \r | |
200 | if(selchan_info->dma_mode & SELCHAN_MODE_CNT_UP) {\r | |
201 | selchan_info->dma_addr += i;\r | |
202 | } else {\r | |
203 | selchan_info->dma_addr -= i;\r | |
204 | }\r | |
205 | }\r | |
206 | \r | |
207 | return(0);\r | |
208 | }\r |