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1 | /* pdp11_stddev.c: PDP-11 standard I/O devices simulator\r |
2 | \r | |
3 | Copyright (c) 1993-2008, Robert M Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | tti,tto DL11 terminal input/output\r | |
27 | clk KW11L (and other) line frequency clock\r | |
28 | \r | |
29 | 20-May-08 RMS Standardized clock delay at 1mips\r | |
30 | 18-Jun-07 RMS Added UNIT_IDLE flag to console input, clock\r | |
31 | 29-Oct-06 RMS Synced keyboard and clock\r | |
32 | Added clock coscheduling support\r | |
33 | 05-Jul-06 RMS Added UC only support for early DOS/RSTS\r | |
34 | 22-Nov-05 RMS Revised for new terminal processing routines\r | |
35 | 22-Sep-05 RMS Fixed declarations (from Sterling Garwood)\r | |
36 | 07-Jul-05 RMS Removed extraneous externs\r | |
37 | 11-Oct-04 RMS Added clock model dependencies\r | |
38 | 28-May-04 RMS Removed SET TTI CTRL-C\r | |
39 | 29-Dec-03 RMS Added console backpressure support\r | |
40 | 25-Apr-03 RMS Revised for extended file support\r | |
41 | 01-Mar-03 RMS Added SET/SHOW CLOCK FREQ, SET TTI CTRL-C\r | |
42 | 22-Nov-02 RMS Changed terminal default to 7B for UNIX\r | |
43 | 01-Nov-02 RMS Added 7B/8B support to terminal\r | |
44 | 29-Sep-02 RMS Added vector display support\r | |
45 | Split out paper tape\r | |
46 | Split DL11 dibs\r | |
47 | 30-May-02 RMS Widened POS to 32b\r | |
48 | 26-Jan-02 RMS Revised for multiple timers\r | |
49 | 09-Jan-02 RMS Fixed bugs in KW11L (found by John Dundas)\r | |
50 | 06-Jan-02 RMS Split I/O address routines, revised enable/disable support\r | |
51 | 29-Nov-01 RMS Added read only unit support\r | |
52 | 09-Nov-01 RMS Added RQDX3 support\r | |
53 | 07-Oct-01 RMS Upgraded clock to full KW11L for RSTS/E autoconfigure\r | |
54 | 07-Sep-01 RMS Moved function prototypes, revised interrupt mechanism\r | |
55 | 17-Jul-01 RMS Moved function prototype\r | |
56 | 04-Jul-01 RMS Added DZ11 support\r | |
57 | 05-Mar-01 RMS Added clock calibration support\r | |
58 | 30-Oct-00 RMS Standardized register order\r | |
59 | 25-Jun-98 RMS Fixed bugs in paper tape error handling\r | |
60 | */\r | |
61 | \r | |
62 | #include "pdp11_defs.h"\r | |
63 | \r | |
64 | #define TTICSR_IMP (CSR_DONE + CSR_IE) /* terminal input */\r | |
65 | #define TTICSR_RW (CSR_IE)\r | |
66 | #define TTOCSR_IMP (CSR_DONE + CSR_IE) /* terminal output */\r | |
67 | #define TTOCSR_RW (CSR_IE)\r | |
68 | #define CLKCSR_IMP (CSR_DONE + CSR_IE) /* real-time clock */\r | |
69 | #define CLKCSR_RW (CSR_IE)\r | |
70 | #define CLK_DELAY 16667\r | |
71 | \r | |
72 | extern int32 int_req[IPL_HLVL];\r | |
73 | extern uint32 cpu_type;\r | |
74 | \r | |
75 | int32 tti_csr = 0; /* control/status */\r | |
76 | int32 tto_csr = 0; /* control/status */\r | |
77 | int32 clk_csr = 0; /* control/status */\r | |
78 | int32 clk_tps = 60; /* ticks/second */\r | |
79 | int32 clk_default = 60; /* default ticks/second */\r | |
80 | int32 clk_fie = 0; /* force IE = 1 */\r | |
81 | int32 clk_fnxm = 0; /* force NXM on reg */\r | |
82 | int32 tmxr_poll = CLK_DELAY; /* term mux poll */\r | |
83 | int32 tmr_poll = CLK_DELAY; /* timer poll */\r | |
84 | \r | |
85 | t_stat tti_rd (int32 *data, int32 PA, int32 access);\r | |
86 | t_stat tti_wr (int32 data, int32 PA, int32 access);\r | |
87 | t_stat tti_svc (UNIT *uptr);\r | |
88 | t_stat tti_reset (DEVICE *dptr);\r | |
89 | t_stat tto_rd (int32 *data, int32 PA, int32 access);\r | |
90 | t_stat tto_wr (int32 data, int32 PA, int32 access);\r | |
91 | t_stat tto_svc (UNIT *uptr);\r | |
92 | t_stat tto_reset (DEVICE *dptr);\r | |
93 | t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
94 | t_stat clk_rd (int32 *data, int32 PA, int32 access);\r | |
95 | t_stat clk_wr (int32 data, int32 PA, int32 access);\r | |
96 | t_stat clk_svc (UNIT *uptr);\r | |
97 | int32 clk_inta (void);\r | |
98 | t_stat clk_reset (DEVICE *dptr);\r | |
99 | t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
100 | t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);\r | |
101 | \r | |
102 | /* TTI data structures\r | |
103 | \r | |
104 | tti_dev TTI device descriptor\r | |
105 | tti_unit TTI unit descriptor\r | |
106 | tti_reg TTI register list\r | |
107 | */\r | |
108 | \r | |
109 | DIB tti_dib = {\r | |
110 | IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr,\r | |
111 | 1, IVCL (TTI), VEC_TTI, { NULL }\r | |
112 | };\r | |
113 | \r | |
114 | UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), 0 };\r | |
115 | \r | |
116 | REG tti_reg[] = {\r | |
117 | { ORDATA (BUF, tti_unit.buf, 8) },\r | |
118 | { ORDATA (CSR, tti_csr, 16) },\r | |
119 | { FLDATA (INT, IREQ (TTI), INT_V_TTI) },\r | |
120 | { FLDATA (ERR, tti_csr, CSR_V_ERR) },\r | |
121 | { FLDATA (DONE, tti_csr, CSR_V_DONE) },\r | |
122 | { FLDATA (IE, tti_csr, CSR_V_IE) },\r | |
123 | { DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },\r | |
124 | { DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },\r | |
125 | { NULL }\r | |
126 | };\r | |
127 | \r | |
128 | MTAB tti_mod[] = {\r | |
129 | { TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },\r | |
130 | { TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },\r | |
131 | { TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },\r | |
132 | { TT_MODE, TT_MODE_7P, "7b", NULL, NULL },\r | |
133 | { MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,\r | |
134 | NULL, &show_addr, NULL },\r | |
135 | { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,\r | |
136 | NULL, &show_vec, NULL },\r | |
137 | { 0 }\r | |
138 | };\r | |
139 | \r | |
140 | DEVICE tti_dev = {\r | |
141 | "TTI", &tti_unit, tti_reg, tti_mod,\r | |
142 | 1, 10, 31, 1, 8, 8,\r | |
143 | NULL, NULL, &tti_reset,\r | |
144 | NULL, NULL, NULL,\r | |
145 | &tti_dib, DEV_UBUS | DEV_QBUS\r | |
146 | };\r | |
147 | \r | |
148 | /* TTO data structures\r | |
149 | \r | |
150 | tto_dev TTO device descriptor\r | |
151 | tto_unit TTO unit descriptor\r | |
152 | tto_reg TTO register list\r | |
153 | */\r | |
154 | \r | |
155 | DIB tto_dib = {\r | |
156 | IOBA_TTO, IOLN_TTO, &tto_rd, &tto_wr,\r | |
157 | 1, IVCL (TTO), VEC_TTO, { NULL }\r | |
158 | };\r | |
159 | \r | |
160 | UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_7P, 0), SERIAL_OUT_WAIT };\r | |
161 | \r | |
162 | REG tto_reg[] = {\r | |
163 | { ORDATA (BUF, tto_unit.buf, 8) },\r | |
164 | { ORDATA (CSR, tto_csr, 16) },\r | |
165 | { FLDATA (INT, IREQ (TTO), INT_V_TTO) },\r | |
166 | { FLDATA (ERR, tto_csr, CSR_V_ERR) },\r | |
167 | { FLDATA (DONE, tto_csr, CSR_V_DONE) },\r | |
168 | { FLDATA (IE, tto_csr, CSR_V_IE) },\r | |
169 | { DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },\r | |
170 | { DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },\r | |
171 | { NULL }\r | |
172 | };\r | |
173 | \r | |
174 | MTAB tto_mod[] = {\r | |
175 | { TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },\r | |
176 | { TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },\r | |
177 | { TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },\r | |
178 | { TT_MODE, TT_MODE_7P, "7p", "7P", &tty_set_mode },\r | |
179 | { MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,\r | |
180 | NULL, &show_addr, NULL },\r | |
181 | { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,\r | |
182 | NULL, &show_vec, NULL },\r | |
183 | { 0 }\r | |
184 | };\r | |
185 | \r | |
186 | DEVICE tto_dev = {\r | |
187 | "TTO", &tto_unit, tto_reg, tto_mod,\r | |
188 | 1, 10, 31, 1, 8, 8,\r | |
189 | NULL, NULL, &tto_reset,\r | |
190 | NULL, NULL, NULL,\r | |
191 | &tto_dib, DEV_UBUS | DEV_QBUS\r | |
192 | };\r | |
193 | \r | |
194 | /* CLK data structures\r | |
195 | \r | |
196 | clk_dev CLK device descriptor\r | |
197 | clk_unit CLK unit descriptor\r | |
198 | clk_reg CLK register list\r | |
199 | */\r | |
200 | \r | |
201 | DIB clk_dib = {\r | |
202 | IOBA_CLK, IOLN_CLK, &clk_rd, &clk_wr,\r | |
203 | 1, IVCL (CLK), VEC_CLK, { &clk_inta }\r | |
204 | };\r | |
205 | \r | |
206 | UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY };\r | |
207 | \r | |
208 | REG clk_reg[] = {\r | |
209 | { ORDATA (CSR, clk_csr, 16) },\r | |
210 | { FLDATA (INT, IREQ (CLK), INT_V_CLK) },\r | |
211 | { FLDATA (DONE, clk_csr, CSR_V_DONE) },\r | |
212 | { FLDATA (IE, clk_csr, CSR_V_IE) },\r | |
213 | { DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },\r | |
214 | { DRDATA (TPS, clk_tps, 16), PV_LEFT + REG_HRO },\r | |
215 | { DRDATA (DEFTPS, clk_default, 16), PV_LEFT + REG_HRO },\r | |
216 | { FLDATA (FIE, clk_fie, 0), REG_HIDDEN },\r | |
217 | { FLDATA (FNXM, clk_fnxm, 0), REG_HIDDEN },\r | |
218 | { NULL }\r | |
219 | };\r | |
220 | \r | |
221 | MTAB clk_mod[] = {\r | |
222 | { MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",\r | |
223 | &clk_set_freq, NULL, NULL },\r | |
224 | { MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",\r | |
225 | &clk_set_freq, NULL, NULL },\r | |
226 | { MTAB_XTD|MTAB_VDV, 0, "FREQUENCY", NULL,\r | |
227 | NULL, &clk_show_freq, NULL },\r | |
228 | { MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,\r | |
229 | NULL, &show_addr, NULL },\r | |
230 | { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,\r | |
231 | NULL, &show_vec, NULL },\r | |
232 | { 0 }\r | |
233 | };\r | |
234 | \r | |
235 | DEVICE clk_dev = {\r | |
236 | "CLK", &clk_unit, clk_reg, clk_mod,\r | |
237 | 1, 0, 0, 0, 0, 0,\r | |
238 | NULL, NULL, &clk_reset,\r | |
239 | NULL, NULL, NULL,\r | |
240 | &clk_dib, DEV_UBUS | DEV_QBUS\r | |
241 | };\r | |
242 | \r | |
243 | /* Terminal input address routines */\r | |
244 | \r | |
245 | t_stat tti_rd (int32 *data, int32 PA, int32 access)\r | |
246 | {\r | |
247 | switch ((PA >> 1) & 01) { /* decode PA<1> */\r | |
248 | \r | |
249 | case 00: /* tti csr */\r | |
250 | *data = tti_csr & TTICSR_IMP;\r | |
251 | return SCPE_OK;\r | |
252 | \r | |
253 | case 01: /* tti buf */\r | |
254 | tti_csr = tti_csr & ~CSR_DONE;\r | |
255 | CLR_INT (TTI);\r | |
256 | *data = tti_unit.buf & 0377;\r | |
257 | return SCPE_OK;\r | |
258 | } /* end switch PA */\r | |
259 | \r | |
260 | return SCPE_NXM;\r | |
261 | }\r | |
262 | \r | |
263 | t_stat tti_wr (int32 data, int32 PA, int32 access)\r | |
264 | {\r | |
265 | switch ((PA >> 1) & 01) { /* decode PA<1> */\r | |
266 | \r | |
267 | case 00: /* tti csr */\r | |
268 | if (PA & 1) return SCPE_OK;\r | |
269 | if ((data & CSR_IE) == 0) CLR_INT (TTI);\r | |
270 | else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)\r | |
271 | SET_INT (TTI);\r | |
272 | tti_csr = (tti_csr & ~TTICSR_RW) | (data & TTICSR_RW);\r | |
273 | return SCPE_OK;\r | |
274 | \r | |
275 | case 01: /* tti buf */\r | |
276 | return SCPE_OK;\r | |
277 | } /* end switch PA */\r | |
278 | \r | |
279 | return SCPE_NXM;\r | |
280 | }\r | |
281 | \r | |
282 | /* Terminal input service */\r | |
283 | \r | |
284 | t_stat tti_svc (UNIT *uptr)\r | |
285 | {\r | |
286 | int32 c;\r | |
287 | \r | |
288 | sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll)); /* continue poll */\r | |
289 | if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c; /* no char or error? */\r | |
290 | if (c & SCPE_BREAK) uptr->buf = 0; /* break? */\r | |
291 | else uptr->buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags));\r | |
292 | uptr->pos = uptr->pos + 1;\r | |
293 | tti_csr = tti_csr | CSR_DONE;\r | |
294 | if (tti_csr & CSR_IE) SET_INT (TTI);\r | |
295 | return SCPE_OK;\r | |
296 | }\r | |
297 | \r | |
298 | /* Terminal input reset */\r | |
299 | \r | |
300 | t_stat tti_reset (DEVICE *dptr)\r | |
301 | {\r | |
302 | tti_unit.buf = 0;\r | |
303 | tti_csr = 0;\r | |
304 | CLR_INT (TTI);\r | |
305 | sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));\r | |
306 | return SCPE_OK;\r | |
307 | }\r | |
308 | \r | |
309 | /* Terminal output address routines */\r | |
310 | \r | |
311 | t_stat tto_rd (int32 *data, int32 PA, int32 access)\r | |
312 | {\r | |
313 | switch ((PA >> 1) & 01) { /* decode PA<1> */\r | |
314 | \r | |
315 | case 00: /* tto csr */\r | |
316 | *data = tto_csr & TTOCSR_IMP;\r | |
317 | return SCPE_OK;\r | |
318 | \r | |
319 | case 01: /* tto buf */\r | |
320 | *data = tto_unit.buf;\r | |
321 | return SCPE_OK;\r | |
322 | } /* end switch PA */\r | |
323 | \r | |
324 | return SCPE_NXM;\r | |
325 | }\r | |
326 | \r | |
327 | t_stat tto_wr (int32 data, int32 PA, int32 access)\r | |
328 | {\r | |
329 | switch ((PA >> 1) & 01) { /* decode PA<1> */\r | |
330 | \r | |
331 | case 00: /* tto csr */\r | |
332 | if (PA & 1) return SCPE_OK;\r | |
333 | if ((data & CSR_IE) == 0) CLR_INT (TTO);\r | |
334 | else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)\r | |
335 | SET_INT (TTO);\r | |
336 | tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW);\r | |
337 | return SCPE_OK;\r | |
338 | \r | |
339 | case 01: /* tto buf */\r | |
340 | if ((PA & 1) == 0) tto_unit.buf = data & 0377;\r | |
341 | tto_csr = tto_csr & ~CSR_DONE;\r | |
342 | CLR_INT (TTO);\r | |
343 | sim_activate (&tto_unit, tto_unit.wait);\r | |
344 | return SCPE_OK;\r | |
345 | } /* end switch PA */\r | |
346 | \r | |
347 | return SCPE_NXM;\r | |
348 | }\r | |
349 | \r | |
350 | /* Terminal output service */\r | |
351 | \r | |
352 | t_stat tto_svc (UNIT *uptr)\r | |
353 | {\r | |
354 | int32 c;\r | |
355 | t_stat r;\r | |
356 | \r | |
357 | c = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags));\r | |
358 | if (c >= 0) {\r | |
359 | if ((r = sim_putchar_s (c)) != SCPE_OK) { /* output; error? */\r | |
360 | sim_activate (uptr, uptr->wait); /* try again */\r | |
361 | return ((r == SCPE_STALL)? SCPE_OK: r); /* !stall? report */\r | |
362 | }\r | |
363 | }\r | |
364 | tto_csr = tto_csr | CSR_DONE;\r | |
365 | if (tto_csr & CSR_IE) SET_INT (TTO);\r | |
366 | uptr->pos = uptr->pos + 1;\r | |
367 | return SCPE_OK;\r | |
368 | }\r | |
369 | \r | |
370 | /* Terminal output reset */\r | |
371 | \r | |
372 | t_stat tto_reset (DEVICE *dptr)\r | |
373 | {\r | |
374 | tto_unit.buf = 0;\r | |
375 | tto_csr = CSR_DONE;\r | |
376 | CLR_INT (TTO);\r | |
377 | sim_cancel (&tto_unit); /* deactivate unit */\r | |
378 | return SCPE_OK;\r | |
379 | }\r | |
380 | \r | |
381 | t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc)\r | |
382 | {\r | |
383 | tti_unit.flags = (tti_unit.flags & ~TT_MODE) | val;\r | |
384 | tto_unit.flags = (tto_unit.flags & ~TT_MODE) | val;\r | |
385 | return SCPE_OK;\r | |
386 | }\r | |
387 | \r | |
388 | /* The line time clock has a few twists and turns through the history of 11's\r | |
389 | \r | |
390 | LSI-11 no CSR\r | |
391 | LSI-11/23 (KDF11A) no CSR\r | |
392 | PDP-11/23+ (KDF11B) no monitor bit\r | |
393 | PDP-11/24 (KDF11U) monitor bit clears on IAK\r | |
394 | */\r | |
395 | \r | |
396 | /* Clock I/O address routines */\r | |
397 | \r | |
398 | t_stat clk_rd (int32 *data, int32 PA, int32 access)\r | |
399 | {\r | |
400 | if (clk_fnxm) return SCPE_NXM; /* not there??? */\r | |
401 | if (CPUT (HAS_LTCM)) *data = clk_csr & CLKCSR_IMP; /* monitor bit? */\r | |
402 | else *data = clk_csr & (CLKCSR_IMP & ~CSR_DONE); /* no, just IE */\r | |
403 | return SCPE_OK;\r | |
404 | }\r | |
405 | \r | |
406 | t_stat clk_wr (int32 data, int32 PA, int32 access)\r | |
407 | {\r | |
408 | if (clk_fnxm) return SCPE_NXM; /* not there??? */\r | |
409 | if (PA & 1) return SCPE_OK;\r | |
410 | clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW);\r | |
411 | if (CPUT (HAS_LTCM) && ((data & CSR_DONE) == 0)) /* monitor bit? */\r | |
412 | clk_csr = clk_csr & ~CSR_DONE; /* clr if zero */\r | |
413 | if ((((clk_csr & CSR_IE) == 0) && !clk_fie) || /* unless IE+DONE */\r | |
414 | ((clk_csr & CSR_DONE) == 0)) CLR_INT (CLK); /* clr intr */\r | |
415 | return SCPE_OK;\r | |
416 | }\r | |
417 | \r | |
418 | /* Clock service */\r | |
419 | \r | |
420 | t_stat clk_svc (UNIT *uptr)\r | |
421 | {\r | |
422 | int32 t;\r | |
423 | \r | |
424 | clk_csr = clk_csr | CSR_DONE; /* set done */\r | |
425 | if ((clk_csr & CSR_IE) || clk_fie) SET_INT (CLK);\r | |
426 | t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */\r | |
427 | sim_activate (&clk_unit, t); /* reactivate unit */\r | |
428 | tmr_poll = t; /* set timer poll */\r | |
429 | tmxr_poll = t; /* set mux poll */\r | |
430 | return SCPE_OK;\r | |
431 | }\r | |
432 | \r | |
433 | /* Clock interrupt acknowledge */\r | |
434 | \r | |
435 | int32 clk_inta (void)\r | |
436 | {\r | |
437 | if (CPUT (CPUT_24)) clk_csr = clk_csr & ~CSR_DONE;\r | |
438 | return clk_dib.vec;\r | |
439 | }\r | |
440 | \r | |
441 | /* Clock coscheduling routine */\r | |
442 | \r | |
443 | int32 clk_cosched (int32 wait)\r | |
444 | {\r | |
445 | int32 t;\r | |
446 | \r | |
447 | t = sim_is_active (&clk_unit);\r | |
448 | return (t? t - 1: wait);\r | |
449 | }\r | |
450 | \r | |
451 | /* Clock reset */\r | |
452 | \r | |
453 | t_stat clk_reset (DEVICE *dptr)\r | |
454 | {\r | |
455 | if (CPUT (HAS_LTCR)) clk_fie = clk_fnxm = 0; /* reg there? */\r | |
456 | else clk_fie = clk_fnxm = 1; /* no, BEVENT */\r | |
457 | clk_tps = clk_default; /* set default tps */\r | |
458 | clk_csr = CSR_DONE; /* set done */\r | |
459 | CLR_INT (CLK);\r | |
460 | sim_rtcn_init (clk_unit.wait, TMR_CLK); /* init line clock */\r | |
461 | sim_activate_abs (&clk_unit, clk_unit.wait); /* activate unit */\r | |
462 | tmr_poll = clk_unit.wait; /* set timer poll */\r | |
463 | tmxr_poll = clk_unit.wait; /* set mux poll */\r | |
464 | return SCPE_OK;\r | |
465 | }\r | |
466 | \r | |
467 | /* Set frequency */\r | |
468 | \r | |
469 | t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc)\r | |
470 | {\r | |
471 | if (cptr) return SCPE_ARG;\r | |
472 | if ((val != 50) && (val != 60)) return SCPE_IERR;\r | |
473 | clk_tps = clk_default = val;\r | |
474 | return SCPE_OK;\r | |
475 | }\r | |
476 | \r | |
477 | /* Show frequency */\r | |
478 | \r | |
479 | t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc)\r | |
480 | {\r | |
481 | fprintf (st, "%dHz", clk_tps);\r | |
482 | return SCPE_OK;\r | |
483 | }\r |