First Commit of my working state

[simh.git] / PDP11 / pdp11_stddev.c

/* pdp11_stddev.c: PDP-11 standard I/O devices simulator\r
\r
   Copyright (c) 1993-2008, Robert M Supnik\r
\r
   Permission is hereby granted, free of charge, to any person obtaining a\r
   copy of this software and associated documentation files (the "Software"),\r
   to deal in the Software without restriction, including without limitation\r
   the rights to use, copy, modify, merge, publish, distribute, sublicense,\r
   and/or sell copies of the Software, and to permit persons to whom the\r
   Software is furnished to do so, subject to the following conditions:\r
\r
   The above copyright notice and this permission notice shall be included in\r
   all copies or substantial portions of the Software.\r
\r
   THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
   IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r
   FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL\r
   ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
   IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
   CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
\r
   Except as contained in this notice, the name of Robert M Supnik shall not be\r
   used in advertising or otherwise to promote the sale, use or other dealings\r
   in this Software without prior written authorization from Robert M Supnik.\r
\r
   tti,tto      DL11 terminal input/output\r
   clk          KW11L (and other) line frequency clock\r
\r
   20-May-08    RMS     Standardized clock delay at 1mips\r
   18-Jun-07    RMS     Added UNIT_IDLE flag to console input, clock\r
   29-Oct-06	RMS     Synced keyboard and clock\r
                        Added clock coscheduling support\r
   05-Jul-06    RMS     Added UC only support for early DOS/RSTS\r
   22-Nov-05    RMS     Revised for new terminal processing routines\r
   22-Sep-05    RMS     Fixed declarations (from Sterling Garwood)\r
   07-Jul-05    RMS     Removed extraneous externs\r
   11-Oct-04    RMS     Added clock model dependencies\r
   28-May-04    RMS     Removed SET TTI CTRL-C\r
   29-Dec-03    RMS     Added console backpressure support\r
   25-Apr-03    RMS     Revised for extended file support\r
   01-Mar-03    RMS     Added SET/SHOW CLOCK FREQ, SET TTI CTRL-C\r
   22-Nov-02    RMS     Changed terminal default to 7B for UNIX\r
   01-Nov-02    RMS     Added 7B/8B support to terminal\r
   29-Sep-02    RMS     Added vector display support\r
                        Split out paper tape\r
                        Split DL11 dibs\r
   30-May-02    RMS     Widened POS to 32b\r
   26-Jan-02    RMS     Revised for multiple timers\r
   09-Jan-02    RMS     Fixed bugs in KW11L (found by John Dundas)\r
   06-Jan-02    RMS     Split I/O address routines, revised enable/disable support\r
   29-Nov-01    RMS     Added read only unit support\r
   09-Nov-01    RMS     Added RQDX3 support\r
   07-Oct-01    RMS     Upgraded clock to full KW11L for RSTS/E autoconfigure\r
   07-Sep-01    RMS     Moved function prototypes, revised interrupt mechanism\r
   17-Jul-01    RMS     Moved function prototype\r
   04-Jul-01    RMS     Added DZ11 support\r
   05-Mar-01    RMS     Added clock calibration support\r
   30-Oct-00    RMS     Standardized register order\r
   25-Jun-98    RMS     Fixed bugs in paper tape error handling\r
*/\r
\r
#include "pdp11_defs.h"\r
\r
#define TTICSR_IMP      (CSR_DONE + CSR_IE)             /* terminal input */\r
#define TTICSR_RW       (CSR_IE)\r
#define TTOCSR_IMP      (CSR_DONE + CSR_IE)             /* terminal output */\r
#define TTOCSR_RW       (CSR_IE)\r
#define CLKCSR_IMP      (CSR_DONE + CSR_IE)             /* real-time clock */\r
#define CLKCSR_RW       (CSR_IE)\r
#define CLK_DELAY       16667\r
\r
extern int32 int_req[IPL_HLVL];\r
extern uint32 cpu_type;\r
\r
int32 tti_csr = 0;                                      /* control/status */\r
int32 tto_csr = 0;                                      /* control/status */\r
int32 clk_csr = 0;                                      /* control/status */\r
int32 clk_tps = 60;                                     /* ticks/second */\r
int32 clk_default = 60;                                 /* default ticks/second */\r
int32 clk_fie = 0;                                      /* force IE = 1 */\r
int32 clk_fnxm = 0;                                     /* force NXM on reg */\r
int32 tmxr_poll = CLK_DELAY;                            /* term mux poll */\r
int32 tmr_poll = CLK_DELAY;                             /* timer poll */\r
\r
t_stat tti_rd (int32 *data, int32 PA, int32 access);\r
t_stat tti_wr (int32 data, int32 PA, int32 access);\r
t_stat tti_svc (UNIT *uptr);\r
t_stat tti_reset (DEVICE *dptr);\r
t_stat tto_rd (int32 *data, int32 PA, int32 access);\r
t_stat tto_wr (int32 data, int32 PA, int32 access);\r
t_stat tto_svc (UNIT *uptr);\r
t_stat tto_reset (DEVICE *dptr);\r
t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc);\r
t_stat clk_rd (int32 *data, int32 PA, int32 access);\r
t_stat clk_wr (int32 data, int32 PA, int32 access);\r
t_stat clk_svc (UNIT *uptr);\r
int32 clk_inta (void);\r
t_stat clk_reset (DEVICE *dptr);\r
t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc);\r
t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc);\r
\r
/* TTI data structures\r
\r
   tti_dev      TTI device descriptor\r
   tti_unit     TTI unit descriptor\r
   tti_reg      TTI register list\r
*/\r
\r
DIB tti_dib = {\r
    IOBA_TTI, IOLN_TTI, &tti_rd, &tti_wr,\r
    1, IVCL (TTI), VEC_TTI, { NULL }\r
    };\r
\r
UNIT tti_unit = { UDATA (&tti_svc, UNIT_IDLE, 0), 0 };\r
\r
REG tti_reg[] = {\r
    { ORDATA (BUF, tti_unit.buf, 8) },\r
    { ORDATA (CSR, tti_csr, 16) },\r
    { FLDATA (INT, IREQ (TTI), INT_V_TTI) },\r
    { FLDATA (ERR, tti_csr, CSR_V_ERR) },\r
    { FLDATA (DONE, tti_csr, CSR_V_DONE) },\r
    { FLDATA (IE, tti_csr, CSR_V_IE) },\r
    { DRDATA (POS, tti_unit.pos, T_ADDR_W), PV_LEFT },\r
    { DRDATA (TIME, tti_unit.wait, 24), PV_LEFT },\r
    { NULL }\r
    };\r
\r
MTAB tti_mod[] = {\r
    { TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },\r
    { TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },\r
    { TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },\r
    { TT_MODE, TT_MODE_7P, "7b", NULL, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,\r
      NULL, &show_addr, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,\r
      NULL, &show_vec, NULL },\r
    { 0 }\r
    };\r
\r
DEVICE tti_dev = {\r
    "TTI", &tti_unit, tti_reg, tti_mod,\r
    1, 10, 31, 1, 8, 8,\r
    NULL, NULL, &tti_reset,\r
    NULL, NULL, NULL,\r
    &tti_dib, DEV_UBUS | DEV_QBUS\r
    };\r
\r
/* TTO data structures\r
\r
   tto_dev      TTO device descriptor\r
   tto_unit     TTO unit descriptor\r
   tto_reg      TTO register list\r
*/\r
\r
DIB tto_dib = {\r
    IOBA_TTO, IOLN_TTO, &tto_rd, &tto_wr,\r
    1, IVCL (TTO), VEC_TTO, { NULL }\r
    };\r
\r
UNIT tto_unit = { UDATA (&tto_svc, TT_MODE_7P, 0), SERIAL_OUT_WAIT };\r
\r
REG tto_reg[] = {\r
    { ORDATA (BUF, tto_unit.buf, 8) },\r
    { ORDATA (CSR, tto_csr, 16) },\r
    { FLDATA (INT, IREQ (TTO), INT_V_TTO) },\r
    { FLDATA (ERR, tto_csr, CSR_V_ERR) },\r
    { FLDATA (DONE, tto_csr, CSR_V_DONE) },\r
    { FLDATA (IE, tto_csr, CSR_V_IE) },\r
    { DRDATA (POS, tto_unit.pos, T_ADDR_W), PV_LEFT },\r
    { DRDATA (TIME, tto_unit.wait, 24), PV_LEFT },\r
    { NULL }\r
    };\r
\r
MTAB tto_mod[] = {\r
    { TT_MODE, TT_MODE_UC, "UC", "UC", &tty_set_mode },\r
    { TT_MODE, TT_MODE_7B, "7b", "7B", &tty_set_mode },\r
    { TT_MODE, TT_MODE_8B, "8b", "8B", &tty_set_mode },\r
    { TT_MODE, TT_MODE_7P, "7p", "7P", &tty_set_mode },\r
    { MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,\r
      NULL, &show_addr, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,\r
      NULL, &show_vec, NULL },\r
    { 0 }\r
    };\r
\r
DEVICE tto_dev = {\r
    "TTO", &tto_unit, tto_reg, tto_mod,\r
    1, 10, 31, 1, 8, 8,\r
    NULL, NULL, &tto_reset,\r
    NULL, NULL, NULL,\r
    &tto_dib, DEV_UBUS | DEV_QBUS\r
    };\r
\r
/* CLK data structures\r
\r
   clk_dev      CLK device descriptor\r
   clk_unit     CLK unit descriptor\r
   clk_reg      CLK register list\r
*/\r
\r
DIB clk_dib = {\r
    IOBA_CLK, IOLN_CLK, &clk_rd, &clk_wr,\r
    1, IVCL (CLK), VEC_CLK, { &clk_inta }\r
    };\r
\r
UNIT clk_unit = { UDATA (&clk_svc, UNIT_IDLE, 0), CLK_DELAY };\r
\r
REG clk_reg[] = {\r
    { ORDATA (CSR, clk_csr, 16) },\r
    { FLDATA (INT, IREQ (CLK), INT_V_CLK) },\r
    { FLDATA (DONE, clk_csr, CSR_V_DONE) },\r
    { FLDATA (IE, clk_csr, CSR_V_IE) },\r
    { DRDATA (TIME, clk_unit.wait, 24), REG_NZ + PV_LEFT },\r
    { DRDATA (TPS, clk_tps, 16), PV_LEFT + REG_HRO },\r
    { DRDATA (DEFTPS, clk_default, 16), PV_LEFT + REG_HRO },\r
    { FLDATA (FIE, clk_fie, 0), REG_HIDDEN },\r
    { FLDATA (FNXM, clk_fnxm, 0), REG_HIDDEN },\r
    { NULL }\r
    };\r
\r
MTAB clk_mod[] = {\r
    { MTAB_XTD|MTAB_VDV, 50, NULL, "50HZ",\r
      &clk_set_freq, NULL, NULL },\r
    { MTAB_XTD|MTAB_VDV, 60, NULL, "60HZ",\r
      &clk_set_freq, NULL, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, "FREQUENCY", NULL,\r
      NULL, &clk_show_freq, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, "ADDRESS", NULL,\r
      NULL, &show_addr, NULL },\r
    { MTAB_XTD|MTAB_VDV, 0, "VECTOR", NULL,\r
      NULL, &show_vec, NULL },\r
    { 0 }\r
    };\r
\r
DEVICE clk_dev = {\r
    "CLK", &clk_unit, clk_reg, clk_mod,\r
    1, 0, 0, 0, 0, 0,\r
    NULL, NULL, &clk_reset,\r
    NULL, NULL, NULL,\r
    &clk_dib, DEV_UBUS | DEV_QBUS\r
    };\r
\r
/* Terminal input address routines */\r
\r
t_stat tti_rd (int32 *data, int32 PA, int32 access)\r
{\r
switch ((PA >> 1) & 01) {                               /* decode PA<1> */\r
\r
    case 00:                                            /* tti csr */\r
        *data = tti_csr & TTICSR_IMP;\r
        return SCPE_OK;\r
\r
    case 01:                                            /* tti buf */\r
        tti_csr = tti_csr & ~CSR_DONE;\r
        CLR_INT (TTI);\r
        *data = tti_unit.buf & 0377;\r
        return SCPE_OK;\r
        }                                               /* end switch PA */\r
\r
return SCPE_NXM;\r
}\r
\r
t_stat tti_wr (int32 data, int32 PA, int32 access)\r
{\r
switch ((PA >> 1) & 01) {                               /* decode PA<1> */\r
\r
    case 00:                                            /* tti csr */\r
        if (PA & 1) return SCPE_OK;\r
        if ((data & CSR_IE) == 0) CLR_INT (TTI);\r
        else if ((tti_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)\r
            SET_INT (TTI);\r
        tti_csr = (tti_csr & ~TTICSR_RW) | (data & TTICSR_RW);\r
        return SCPE_OK;\r
\r
    case 01:                                            /* tti buf */\r
        return SCPE_OK;\r
        }                                               /* end switch PA */\r
\r
return SCPE_NXM;\r
}\r
\r
/* Terminal input service */\r
\r
t_stat tti_svc (UNIT *uptr)\r
{\r
int32 c;\r
\r
sim_activate (uptr, KBD_WAIT (uptr->wait, tmr_poll));   /* continue poll */\r
if ((c = sim_poll_kbd ()) < SCPE_KFLAG) return c;       /* no char or error? */\r
if (c & SCPE_BREAK) uptr->buf = 0;                      /* break? */\r
else uptr->buf = sim_tt_inpcvt (c, TT_GET_MODE (uptr->flags));\r
uptr->pos = uptr->pos + 1;\r
tti_csr = tti_csr | CSR_DONE;\r
if (tti_csr & CSR_IE) SET_INT (TTI);\r
return SCPE_OK;\r
}\r
\r
/* Terminal input reset */\r
\r
t_stat tti_reset (DEVICE *dptr)\r
{\r
tti_unit.buf = 0;\r
tti_csr = 0;\r
CLR_INT (TTI);\r
sim_activate_abs (&tti_unit, KBD_WAIT (tti_unit.wait, tmr_poll));\r
return SCPE_OK;\r
}\r
\r
/* Terminal output address routines */\r
\r
t_stat tto_rd (int32 *data, int32 PA, int32 access)\r
{\r
switch ((PA >> 1) & 01) {                               /* decode PA<1> */\r
\r
    case 00:                                            /* tto csr */\r
        *data = tto_csr & TTOCSR_IMP;\r
        return SCPE_OK;\r
\r
    case 01:                                            /* tto buf */\r
        *data = tto_unit.buf;\r
        return SCPE_OK;\r
        }                                               /* end switch PA */\r
\r
return SCPE_NXM;\r
}\r
\r
t_stat tto_wr (int32 data, int32 PA, int32 access)\r
{\r
switch ((PA >> 1) & 01) {                               /* decode PA<1> */\r
\r
    case 00:                                            /* tto csr */\r
        if (PA & 1) return SCPE_OK;\r
        if ((data & CSR_IE) == 0) CLR_INT (TTO);\r
        else if ((tto_csr & (CSR_DONE + CSR_IE)) == CSR_DONE)\r
            SET_INT (TTO);\r
        tto_csr = (tto_csr & ~TTOCSR_RW) | (data & TTOCSR_RW);\r
        return SCPE_OK;\r
\r
    case 01:                                            /* tto buf */\r
        if ((PA & 1) == 0) tto_unit.buf = data & 0377;\r
        tto_csr = tto_csr & ~CSR_DONE;\r
        CLR_INT (TTO);\r
        sim_activate (&tto_unit, tto_unit.wait);\r
        return SCPE_OK;\r
        }                                               /* end switch PA */\r
\r
return SCPE_NXM;\r
}\r
\r
/* Terminal output service */\r
\r
t_stat tto_svc (UNIT *uptr)\r
{\r
int32 c;\r
t_stat r;\r
\r
c = sim_tt_outcvt (uptr->buf, TT_GET_MODE (uptr->flags));\r
if (c >= 0) {\r
    if ((r = sim_putchar_s (c)) != SCPE_OK) {           /* output; error? */\r
        sim_activate (uptr, uptr->wait);                /* try again */\r
        return ((r == SCPE_STALL)? SCPE_OK: r);         /* !stall? report */\r
        }\r
    }\r
tto_csr = tto_csr | CSR_DONE;\r
if (tto_csr & CSR_IE) SET_INT (TTO);\r
uptr->pos = uptr->pos + 1;\r
return SCPE_OK;\r
}\r
\r
/* Terminal output reset */\r
\r
t_stat tto_reset (DEVICE *dptr)\r
{\r
tto_unit.buf = 0;\r
tto_csr = CSR_DONE;\r
CLR_INT (TTO);\r
sim_cancel (&tto_unit);                                 /* deactivate unit */\r
return SCPE_OK;\r
}\r
\r
t_stat tty_set_mode (UNIT *uptr, int32 val, char *cptr, void *desc)\r
{\r
tti_unit.flags = (tti_unit.flags & ~TT_MODE) | val;\r
tto_unit.flags = (tto_unit.flags & ~TT_MODE) | val;\r
return SCPE_OK;\r
}\r
\r
/* The line time clock has a few twists and turns through the history of 11's\r
\r
   LSI-11               no CSR\r
   LSI-11/23 (KDF11A)   no CSR\r
   PDP-11/23+ (KDF11B)  no monitor bit\r
   PDP-11/24 (KDF11U)   monitor bit clears on IAK\r
*/\r
\r
/* Clock I/O address routines */\r
\r
t_stat clk_rd (int32 *data, int32 PA, int32 access)\r
{\r
if (clk_fnxm) return SCPE_NXM;                          /* not there??? */\r
if (CPUT (HAS_LTCM)) *data = clk_csr & CLKCSR_IMP;      /* monitor bit? */\r
else *data = clk_csr & (CLKCSR_IMP & ~CSR_DONE);        /* no, just IE */\r
return SCPE_OK;\r
}\r
\r
t_stat clk_wr (int32 data, int32 PA, int32 access)\r
{\r
if (clk_fnxm) return SCPE_NXM;                          /* not there??? */\r
if (PA & 1) return SCPE_OK;\r
clk_csr = (clk_csr & ~CLKCSR_RW) | (data & CLKCSR_RW);\r
if (CPUT (HAS_LTCM) && ((data & CSR_DONE) == 0))        /* monitor bit? */\r
    clk_csr = clk_csr & ~CSR_DONE;                      /* clr if zero */\r
if ((((clk_csr & CSR_IE) == 0) && !clk_fie) ||          /* unless IE+DONE */\r
    ((clk_csr & CSR_DONE) == 0)) CLR_INT (CLK);         /* clr intr */\r
return SCPE_OK;\r
}\r
\r
/* Clock service */\r
\r
t_stat clk_svc (UNIT *uptr)\r
{\r
int32 t;\r
\r
clk_csr = clk_csr | CSR_DONE;                           /* set done */\r
if ((clk_csr & CSR_IE) || clk_fie) SET_INT (CLK);\r
t = sim_rtcn_calb (clk_tps, TMR_CLK);                   /* calibrate clock */\r
sim_activate (&clk_unit, t);                            /* reactivate unit */\r
tmr_poll = t;                                           /* set timer poll */\r
tmxr_poll = t;                                          /* set mux poll */\r
return SCPE_OK;\r
}\r
\r
/* Clock interrupt acknowledge */\r
\r
int32 clk_inta (void)\r
{\r
if (CPUT (CPUT_24)) clk_csr = clk_csr & ~CSR_DONE;\r
return clk_dib.vec;\r
}\r
\r
/* Clock coscheduling routine */\r
\r
int32 clk_cosched (int32 wait)\r
{\r
int32 t;\r
\r
t = sim_is_active (&clk_unit);\r
return (t? t - 1: wait);\r
}\r
\r
/* Clock reset */\r
\r
t_stat clk_reset (DEVICE *dptr)\r
{\r
if (CPUT (HAS_LTCR)) clk_fie = clk_fnxm = 0;            /* reg there? */\r
else clk_fie = clk_fnxm = 1;                            /* no, BEVENT */\r
clk_tps = clk_default;                                  /* set default tps */\r
clk_csr = CSR_DONE;                                     /* set done */\r
CLR_INT (CLK);\r
sim_rtcn_init (clk_unit.wait, TMR_CLK);                 /* init line clock */\r
sim_activate_abs (&clk_unit, clk_unit.wait);            /* activate unit */\r
tmr_poll = clk_unit.wait;                               /* set timer poll */\r
tmxr_poll = clk_unit.wait;                              /* set mux poll */\r
return SCPE_OK;\r
}\r
\r
/* Set frequency */\r
\r
t_stat clk_set_freq (UNIT *uptr, int32 val, char *cptr, void *desc)\r
{\r
if (cptr) return SCPE_ARG;\r
if ((val != 50) && (val != 60)) return SCPE_IERR;\r
clk_tps = clk_default = val;\r
return SCPE_OK;\r
}\r
\r
/* Show frequency */\r
\r
t_stat clk_show_freq (FILE *st, UNIT *uptr, int32 val, void *desc)\r
{\r
fprintf (st, "%dHz", clk_tps);\r
return SCPE_OK;\r
}\r