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1 | /* pdp18b_rf.c: fixed head disk simulator\r |
2 | \r | |
3 | Copyright (c) 1993-2006, Robert M Supnik\r | |
4 | \r | |
5 | Permission is hereby granted, free of charge, to any person obtaining a\r | |
6 | copy of this software and associated documentation files (the "Software"),\r | |
7 | to deal in the Software without restriction, including without limitation\r | |
8 | the rights to use, copy, modify, merge, publish, distribute, sublicense,\r | |
9 | and/or sell copies of the Software, and to permit persons to whom the\r | |
10 | Software is furnished to do so, subject to the following conditions:\r | |
11 | \r | |
12 | The above copyright notice and this permission notice shall be included in\r | |
13 | all copies or substantial portions of the Software.\r | |
14 | \r | |
15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r | |
16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,\r | |
17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL\r | |
18 | ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r | |
19 | IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r | |
20 | CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r | |
21 | \r | |
22 | Except as contained in this notice, the name of Robert M Supnik shall not be\r | |
23 | used in advertising or otherwise to promote the sale, use or other dealings\r | |
24 | in this Software without prior written authorization from Robert M Supnik.\r | |
25 | \r | |
26 | rf (PDP-9) RF09/RF09\r | |
27 | (PDP-15) RF15/RS09\r | |
28 | \r | |
29 | 04-Oct-06 RMS Fixed bug, DSCD does not clear function register\r | |
30 | 15-May-06 RMS Fixed bug in autosize attach (reported by David Gesswein)\r | |
31 | 14-Jan-04 RMS Revised IO device call interface\r | |
32 | Changed sim_fsize calling sequence\r | |
33 | 26-Oct-03 RMS Cleaned up buffer copy code\r | |
34 | 26-Jul-03 RMS Fixed bug in set size routine\r | |
35 | 14-Mar-03 RMS Fixed variable platter interaction with save/restore\r | |
36 | 03-Mar-03 RMS Fixed autosizing\r | |
37 | 12-Feb-03 RMS Removed 8 platter sizing hack\r | |
38 | 05-Feb-03 RMS Fixed decode bugs, added variable and autosizing\r | |
39 | 05-Oct-02 RMS Added DIB, dev number support\r | |
40 | 06-Jan-02 RMS Revised enable/disable support\r | |
41 | 25-Nov-01 RMS Revised interrupt structure\r | |
42 | 24-Nov-01 RMS Changed WLK to array\r | |
43 | 26-Apr-01 RMS Added device enable/disable support\r | |
44 | 15-Feb-01 RMS Fixed 3 cycle data break sequencing\r | |
45 | 30-Nov-99 RMS Added non-zero requirement to rf_time\r | |
46 | 14-Apr-99 RMS Changed t_addr to unsigned\r | |
47 | \r | |
48 | The RFxx is a head-per-track disk. It uses the multicycle data break\r | |
49 | facility. To minimize overhead, the entire RFxx is buffered in memory.\r | |
50 | \r | |
51 | Two timing parameters are provided:\r | |
52 | \r | |
53 | rf_time Interword timing. Must be non-zero.\r | |
54 | rf_burst Burst mode. If 0, DMA occurs cycle by cycle; otherwise,\r | |
55 | DMA occurs in a burst.\r | |
56 | */\r | |
57 | \r | |
58 | #include "pdp18b_defs.h"\r | |
59 | #include <math.h>\r | |
60 | \r | |
61 | #define UNIT_V_AUTO (UNIT_V_UF + 0) /* autosize */\r | |
62 | #define UNIT_V_PLAT (UNIT_V_UF + 1) /* #platters - 1 */\r | |
63 | #define UNIT_M_PLAT 07\r | |
64 | #define UNIT_PLAT (UNIT_M_PLAT << UNIT_V_PLAT)\r | |
65 | #define UNIT_GETP(x) ((((x) >> UNIT_V_PLAT) & UNIT_M_PLAT) + 1)\r | |
66 | #define UNIT_AUTO (1 << UNIT_V_AUTO)\r | |
67 | #define UNIT_PLAT (UNIT_M_PLAT << UNIT_V_PLAT)\r | |
68 | \r | |
69 | /* Constants */\r | |
70 | \r | |
71 | #define RF_NUMWD 2048 /* words/track */\r | |
72 | #define RF_NUMTR 128 /* tracks/disk */\r | |
73 | #define RF_DKSIZE (RF_NUMTR * RF_NUMWD) /* words/disk */\r | |
74 | #define RF_NUMDK 8 /* disks/controller */\r | |
75 | #define RF_WMASK (RF_NUMWD - 1) /* word mask */\r | |
76 | #define RF_WC 036 /* word count */\r | |
77 | #define RF_CA 037 /* current addr */\r | |
78 | \r | |
79 | /* Function/status register */\r | |
80 | \r | |
81 | #define RFS_ERR 0400000 /* error */\r | |
82 | #define RFS_HDW 0200000 /* hardware error */\r | |
83 | #define RFS_APE 0100000 /* addr parity error */\r | |
84 | #define RFS_MXF 0040000 /* missed transfer */\r | |
85 | #define RFS_WCE 0020000 /* write check error */\r | |
86 | #define RFS_DPE 0010000 /* data parity error */\r | |
87 | #define RFS_WLO 0004000 /* write lock error */\r | |
88 | #define RFS_NED 0002000 /* non-existent disk */\r | |
89 | #define RFS_DCH 0001000 /* data chan timing */\r | |
90 | #define RFS_PGE 0000400 /* programming error */\r | |
91 | #define RFS_DON 0000200 /* transfer complete */\r | |
92 | #define RFS_V_FNC 1 /* function */\r | |
93 | #define RFS_M_FNC 03\r | |
94 | #define RFS_FNC (RFS_M_FNC << RFS_V_FNC)\r | |
95 | #define FN_NOP 0\r | |
96 | #define FN_READ 1\r | |
97 | #define FN_WRITE 2\r | |
98 | #define FN_WCHK 3\r | |
99 | #define RFS_IE 0000001 /* interrupt enable */\r | |
100 | \r | |
101 | #define RFS_CLR 0000170 /* always clear */\r | |
102 | #define RFS_EFLGS (RFS_HDW | RFS_APE | RFS_MXF | RFS_WCE | \\r | |
103 | RFS_DPE | RFS_WLO | RFS_NED ) /* error flags */\r | |
104 | #define RFS_FR (RFS_FNC|RFS_IE)\r | |
105 | #define GET_FNC(x) (((x) >> RFS_V_FNC) & RFS_M_FNC)\r | |
106 | #define GET_POS(x) ((int) fmod (sim_gtime () / ((double) (x)), \\r | |
107 | ((double) RF_NUMWD)))\r | |
108 | #define RF_BUSY (sim_is_active (&rf_unit))\r | |
109 | \r | |
110 | extern int32 M[];\r | |
111 | extern int32 int_hwre[API_HLVL+1];\r | |
112 | extern UNIT cpu_unit;\r | |
113 | \r | |
114 | int32 rf_sta = 0; /* status register */\r | |
115 | int32 rf_da = 0; /* disk address */\r | |
116 | int32 rf_dbuf = 0; /* data buffer */\r | |
117 | int32 rf_wlk[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; /* write lock */\r | |
118 | int32 rf_time = 10; /* inter-word time */\r | |
119 | int32 rf_burst = 1; /* burst mode flag */\r | |
120 | int32 rf_stopioe = 1; /* stop on error */\r | |
121 | \r | |
122 | DEVICE rf_dev;\r | |
123 | int32 rf70 (int32 dev, int32 pulse, int32 dat);\r | |
124 | int32 rf72 (int32 dev, int32 pulse, int32 dat);\r | |
125 | int32 rf_iors (void);\r | |
126 | t_stat rf_svc (UNIT *uptr);\r | |
127 | t_stat rf_reset (DEVICE *dptr);\r | |
128 | int32 rf_updsta (int32 new);\r | |
129 | t_stat rf_attach (UNIT *uptr, char *cptr);\r | |
130 | t_stat rf_set_size (UNIT *uptr, int32 val, char *cptr, void *desc);\r | |
131 | \r | |
132 | /* RF data structures\r | |
133 | \r | |
134 | rf_dev RF device descriptor\r | |
135 | rf_unit RF unit descriptor\r | |
136 | rf_reg RF register list\r | |
137 | */\r | |
138 | \r | |
139 | DIB rf_dib = { DEV_RF, 3, &rf_iors, { &rf70, NULL, &rf72 } };\r | |
140 | \r | |
141 | UNIT rf_unit = {\r | |
142 | UDATA (&rf_svc, UNIT_FIX+UNIT_ATTABLE+UNIT_BUFABLE+UNIT_MUSTBUF+UNIT_AUTO,\r | |
143 | RF_DKSIZE)\r | |
144 | };\r | |
145 | \r | |
146 | REG rf_reg[] = {\r | |
147 | { ORDATA (STA, rf_sta, 18) },\r | |
148 | { ORDATA (DA, rf_da, 22) },\r | |
149 | { ORDATA (WC, M[RF_WC], 18) },\r | |
150 | { ORDATA (CA, M[RF_CA], 18) },\r | |
151 | { ORDATA (BUF, rf_dbuf, 18) },\r | |
152 | { FLDATA (INT, int_hwre[API_RF], INT_V_RF) },\r | |
153 | { BRDATA (WLK, rf_wlk, 8, 16, RF_NUMDK) },\r | |
154 | { DRDATA (TIME, rf_time, 24), PV_LEFT + REG_NZ },\r | |
155 | { FLDATA (BURST, rf_burst, 0) },\r | |
156 | { FLDATA (STOP_IOE, rf_stopioe, 0) },\r | |
157 | { DRDATA (CAPAC, rf_unit.capac, 31), PV_LEFT + REG_HRO },\r | |
158 | { ORDATA (DEVNO, rf_dib.dev, 6), REG_HRO },\r | |
159 | { NULL }\r | |
160 | };\r | |
161 | \r | |
162 | MTAB rf_mod[] = {\r | |
163 | { UNIT_PLAT, (0 << UNIT_V_PLAT), NULL, "1P", &rf_set_size },\r | |
164 | { UNIT_PLAT, (1 << UNIT_V_PLAT), NULL, "2P", &rf_set_size },\r | |
165 | { UNIT_PLAT, (2 << UNIT_V_PLAT), NULL, "3P", &rf_set_size },\r | |
166 | { UNIT_PLAT, (3 << UNIT_V_PLAT), NULL, "4P", &rf_set_size },\r | |
167 | { UNIT_PLAT, (4 << UNIT_V_PLAT), NULL, "5P", &rf_set_size },\r | |
168 | { UNIT_PLAT, (5 << UNIT_V_PLAT), NULL, "6P", &rf_set_size },\r | |
169 | { UNIT_PLAT, (6 << UNIT_V_PLAT), NULL, "7P", &rf_set_size },\r | |
170 | { UNIT_PLAT, (7 << UNIT_V_PLAT), NULL, "8P", &rf_set_size },\r | |
171 | { UNIT_AUTO, UNIT_AUTO, "autosize", "AUTOSIZE", NULL },\r | |
172 | { MTAB_XTD|MTAB_VDV, 0, "DEVNO", "DEVNO", &set_devno, &show_devno },\r | |
173 | { 0 }\r | |
174 | };\r | |
175 | \r | |
176 | DEVICE rf_dev = {\r | |
177 | "RF", &rf_unit, rf_reg, rf_mod,\r | |
178 | 1, 8, 21, 1, 8, 18,\r | |
179 | NULL, NULL, &rf_reset,\r | |
180 | NULL, &rf_attach, NULL,\r | |
181 | &rf_dib, DEV_DISABLE\r | |
182 | };\r | |
183 | \r | |
184 | /* IOT routines */\r | |
185 | \r | |
186 | int32 rf70 (int32 dev, int32 pulse, int32 dat)\r | |
187 | {\r | |
188 | int32 t, sb;\r | |
189 | \r | |
190 | sb = pulse & 060; /* subopcode */\r | |
191 | if (pulse & 01) {\r | |
192 | if ((sb == 000) && (rf_sta & (RFS_ERR | RFS_DON))) /* DSSF */\r | |
193 | dat = IOT_SKP | dat;\r | |
194 | else if (sb == 020) rf_reset (&rf_dev); /* DSCC */\r | |
195 | else if (sb == 040) { /* DSCF */\r | |
196 | if (RF_BUSY) rf_sta = rf_sta | RFS_PGE; /* busy inhibits */\r | |
197 | else rf_sta = rf_sta & ~(RFS_FNC | RFS_IE); /* clear func */\r | |
198 | }\r | |
199 | }\r | |
200 | if (pulse & 02) {\r | |
201 | if (RF_BUSY) rf_sta = rf_sta | RFS_PGE; /* busy sets PGE */\r | |
202 | else if (sb == 000) dat = dat | rf_dbuf; /* DRBR */\r | |
203 | else if (sb == 020) /* DRAL */\r | |
204 | dat = dat | (rf_da & DMASK);\r | |
205 | else if (sb == 040) /* DSFX */\r | |
206 | rf_sta = rf_sta ^ (dat & (RFS_FNC | RFS_IE)); /* xor func */\r | |
207 | else if (sb == 060) /* DRAH */\r | |
208 | dat = dat | (rf_da >> 18) | ((rf_sta & RFS_NED)? 010: 0);\r | |
209 | }\r | |
210 | if (pulse & 04) {\r | |
211 | if (RF_BUSY) rf_sta = rf_sta | RFS_PGE; /* busy sets PGE */\r | |
212 | else if (sb == 000) rf_dbuf = dat & DMASK; /* DLBR */\r | |
213 | else if (sb == 020) /* DLAL */\r | |
214 | rf_da = (rf_da & ~DMASK) | (dat & DMASK);\r | |
215 | else if (sb == 040) { /* DSCN */\r | |
216 | rf_sta = rf_sta & ~RFS_DON; /* clear done */\r | |
217 | if (GET_FNC (rf_sta) != FN_NOP) {\r | |
218 | t = (rf_da & RF_WMASK) - GET_POS (rf_time); /* delta to new */\r | |
219 | if (t < 0) t = t + RF_NUMWD; /* wrap around? */\r | |
220 | sim_activate (&rf_unit, t * rf_time); /* schedule op */\r | |
221 | }\r | |
222 | }\r | |
223 | else if (sb == 060) { /* DLAH */\r | |
224 | rf_da = (rf_da & DMASK) | ((dat & 07) << 18);\r | |
225 | if ((uint32) rf_da >= rf_unit.capac) /* for sizing */\r | |
226 | rf_updsta (RFS_NED);\r | |
227 | }\r | |
228 | }\r | |
229 | rf_updsta (0); /* update status */\r | |
230 | return dat;\r | |
231 | }\r | |
232 | \r | |
233 | int32 rf72 (int32 dev, int32 pulse, int32 dat)\r | |
234 | {\r | |
235 | int32 sb = pulse & 060;\r | |
236 | \r | |
237 | if (pulse & 02) {\r | |
238 | if (sb == 000) dat = dat | GET_POS (rf_time) | /* DLOK */\r | |
239 | (sim_is_active (&rf_unit)? 0400000: 0);\r | |
240 | else if (sb == 040) { /* DSCD */\r | |
241 | if (RF_BUSY) rf_sta = rf_sta | RFS_PGE; /* busy inhibits */\r | |
242 | else rf_sta = rf_sta & RFS_FR;\r | |
243 | rf_updsta (0);\r | |
244 | }\r | |
245 | else if (sb == 060) { /* DSRS */\r | |
246 | if (RF_BUSY) rf_sta = rf_sta | RFS_PGE; /* busy sets PGE */\r | |
247 | dat = dat | rf_updsta (0);\r | |
248 | }\r | |
249 | }\r | |
250 | return dat;\r | |
251 | }\r | |
252 | \r | |
253 | /* Unit service - assumes the entire disk is buffered */\r | |
254 | \r | |
255 | t_stat rf_svc (UNIT *uptr)\r | |
256 | {\r | |
257 | int32 f, pa, d, t;\r | |
258 | int32 *fbuf = uptr->filebuf;\r | |
259 | \r | |
260 | if ((uptr->flags & UNIT_BUF) == 0) { /* not buf? abort */\r | |
261 | rf_updsta (RFS_NED | RFS_DON); /* set nxd, done */\r | |
262 | return IORETURN (rf_stopioe, SCPE_UNATT);\r | |
263 | }\r | |
264 | \r | |
265 | f = GET_FNC (rf_sta); /* get function */\r | |
266 | do {\r | |
267 | if ((uint32) rf_da >= uptr->capac) { /* disk overflow? */\r | |
268 | rf_updsta (RFS_NED); /* nx disk error */\r | |
269 | break;\r | |
270 | }\r | |
271 | M[RF_WC] = (M[RF_WC] + 1) & DMASK; /* incr word count */\r | |
272 | pa = M[RF_CA] = (M[RF_CA] + 1) & AMASK; /* incr mem addr */\r | |
273 | if ((f == FN_READ) && MEM_ADDR_OK (pa)) /* read? */\r | |
274 | M[pa] = fbuf[rf_da];\r | |
275 | if ((f == FN_WCHK) && (M[pa] != fbuf[rf_da])) { /* write check? */\r | |
276 | rf_updsta (RFS_WCE); /* flag error */\r | |
277 | break;\r | |
278 | }\r | |
279 | if (f == FN_WRITE) { /* write? */\r | |
280 | d = (rf_da >> 18) & 07; /* disk */\r | |
281 | t = (rf_da >> 14) & 017; /* track groups */\r | |
282 | if ((rf_wlk[d] >> t) & 1) { /* write locked? */\r | |
283 | rf_updsta (RFS_WLO);\r | |
284 | break;\r | |
285 | }\r | |
286 | else { /* not locked */\r | |
287 | fbuf[rf_da] = M[pa]; /* write word */\r | |
288 | if (((uint32) rf_da) >= uptr->hwmark) uptr->hwmark = rf_da + 1;\r | |
289 | }\r | |
290 | }\r | |
291 | rf_da = rf_da + 1; /* incr disk addr */\r | |
292 | } while ((M[RF_WC] != 0) && (rf_burst != 0)); /* brk if wc, no brst */\r | |
293 | \r | |
294 | if ((M[RF_WC] != 0) && ((rf_sta & RFS_ERR) == 0)) /* more to do? */\r | |
295 | sim_activate (&rf_unit, rf_time); /* sched next */\r | |
296 | else rf_updsta (RFS_DON);\r | |
297 | return SCPE_OK;\r | |
298 | }\r | |
299 | \r | |
300 | /* Update status */\r | |
301 | \r | |
302 | int32 rf_updsta (int32 new)\r | |
303 | {\r | |
304 | rf_sta = (rf_sta | new) & ~(RFS_ERR | RFS_CLR);\r | |
305 | if (rf_sta & RFS_EFLGS) rf_sta = rf_sta | RFS_ERR;\r | |
306 | if ((rf_sta & (RFS_ERR | RFS_DON)) && (rf_sta & RFS_IE))\r | |
307 | SET_INT (RF);\r | |
308 | else CLR_INT (RF);\r | |
309 | return rf_sta;\r | |
310 | }\r | |
311 | \r | |
312 | /* Reset routine */\r | |
313 | \r | |
314 | t_stat rf_reset (DEVICE *dptr)\r | |
315 | {\r | |
316 | rf_sta = rf_da = rf_dbuf = 0;\r | |
317 | rf_updsta (0);\r | |
318 | sim_cancel (&rf_unit);\r | |
319 | return SCPE_OK;\r | |
320 | }\r | |
321 | \r | |
322 | /* IORS routine */\r | |
323 | \r | |
324 | int32 rf_iors (void)\r | |
325 | {\r | |
326 | return ((rf_sta & (RFS_ERR | RFS_DON))? IOS_RF: 0);\r | |
327 | }\r | |
328 | \r | |
329 | /* Attach routine */\r | |
330 | \r | |
331 | t_stat rf_attach (UNIT *uptr, char *cptr)\r | |
332 | {\r | |
333 | uint32 p, sz;\r | |
334 | uint32 ds_bytes = RF_DKSIZE * sizeof (int32);\r | |
335 | \r | |
336 | if ((uptr->flags & UNIT_AUTO) && (sz = sim_fsize_name (cptr))) {\r | |
337 | p = (sz + ds_bytes - 1) / ds_bytes;\r | |
338 | if (p >= RF_NUMDK) p = RF_NUMDK - 1;\r | |
339 | uptr->flags = (uptr->flags & ~UNIT_PLAT) |\r | |
340 | (p << UNIT_V_PLAT);\r | |
341 | }\r | |
342 | uptr->capac = UNIT_GETP (uptr->flags) * RF_DKSIZE;\r | |
343 | return attach_unit (uptr, cptr);\r | |
344 | }\r | |
345 | \r | |
346 | /* Change disk size */\r | |
347 | \r | |
348 | t_stat rf_set_size (UNIT *uptr, int32 val, char *cptr, void *desc)\r | |
349 | {\r | |
350 | if (val < 0) return SCPE_IERR;\r | |
351 | if (uptr->flags & UNIT_ATT) return SCPE_ALATT;\r | |
352 | uptr->capac = UNIT_GETP (val) * RF_DKSIZE;\r | |
353 | uptr->flags = uptr->flags & ~UNIT_AUTO;\r | |
354 | return SCPE_OK;\r | |
355 | }\r |